2013-11-22 21:17:14 +04:00
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/*
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* ARM mach-virt emulation
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*
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* Copyright (c) 2013 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Emulate a virtual board which works by passing Linux all the information
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* it needs about what devices are present via the device tree.
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* There are some restrictions about what we can do here:
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* + we can only present devices whose Linux drivers will work based
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* purely on the device tree with no platform data at all
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* + we want to present a very stripped-down minimalist platform,
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* both because this reduces the security attack surface from the guest
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* and also because it reduces our exposure to being broken when
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* the kernel updates its device tree bindings and requires further
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* information in a device binding that we aren't providing.
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* This is essentially the same approach kvmtool uses.
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*/
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2015-12-07 19:23:45 +03:00
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#include "qemu/osdep.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
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#include "qapi/error.h"
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2013-11-22 21:17:14 +04:00
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#include "hw/sysbus.h"
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#include "hw/arm/arm.h"
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#include "hw/arm/primecell.h"
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2015-05-29 13:28:54 +03:00
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#include "hw/arm/virt.h"
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2013-11-22 21:17:14 +04:00
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#include "hw/devices.h"
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#include "net/net.h"
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2014-10-07 15:59:13 +04:00
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#include "sysemu/block-backend.h"
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2013-11-22 21:17:14 +04:00
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#include "sysemu/device_tree.h"
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2016-05-12 15:22:27 +03:00
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#include "sysemu/numa.h"
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2013-11-22 21:17:14 +04:00
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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2016-06-14 17:59:13 +03:00
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#include "hw/compat.h"
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2014-09-12 17:06:48 +04:00
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#include "hw/loader.h"
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2013-11-22 21:17:14 +04:00
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#include "exec/address-spaces.h"
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#include "qemu/bitops.h"
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#include "qemu/error-report.h"
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2015-02-13 08:46:08 +03:00
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#include "hw/pci-host/gpex.h"
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2015-06-02 14:29:13 +03:00
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#include "hw/arm/sysbus-fdt.h"
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#include "hw/platform-bus.h"
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2015-06-19 16:17:44 +03:00
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#include "hw/arm/fdt.h"
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2016-07-14 18:51:37 +03:00
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#include "hw/intc/arm_gic.h"
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#include "hw/intc/arm_gicv3_common.h"
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2015-08-13 13:26:21 +03:00
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#include "kvm_arm.h"
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2015-09-07 12:39:29 +03:00
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#include "hw/smbios/smbios.h"
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2015-09-24 03:29:37 +03:00
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#include "qapi/visitor.h"
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2015-12-17 16:37:14 +03:00
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#include "standard-headers/linux/input.h"
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2013-11-22 21:17:14 +04:00
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2016-06-14 17:59:12 +03:00
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#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
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2016-06-14 17:59:12 +03:00
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static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
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void *data) \
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{ \
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MachineClass *mc = MACHINE_CLASS(oc); \
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virt_machine_##major##_##minor##_options(mc); \
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mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
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2016-06-14 17:59:12 +03:00
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if (latest) { \
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mc->alias = "virt"; \
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} \
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2016-06-14 17:59:12 +03:00
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} \
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static const TypeInfo machvirt_##major##_##minor##_info = { \
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.name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
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.parent = TYPE_VIRT_MACHINE, \
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.instance_init = virt_##major##_##minor##_instance_init, \
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.class_init = virt_##major##_##minor##_class_init, \
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}; \
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static void machvirt_machine_##major##_##minor##_init(void) \
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{ \
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type_register_static(&machvirt_##major##_##minor##_info); \
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} \
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type_init(machvirt_machine_##major##_##minor##_init);
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2016-06-14 17:59:12 +03:00
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#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
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DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
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#define DEFINE_VIRT_MACHINE(major, minor) \
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DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
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2016-06-14 17:59:12 +03:00
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2017-01-09 14:40:22 +03:00
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/* Number of external interrupt lines to configure the GIC with */
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#define NUM_IRQS 256
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#define PLATFORM_BUS_NUM_IRQS 64
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static ARMPlatformBusSystemParams platform_bus_params;
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2016-03-04 14:30:16 +03:00
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/* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
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* RAM can go up to the 256GB mark, leaving 256GB of the physical
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* address space unallocated and free for future use between 256G and 512G.
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* If we need to provide more RAM to VMs in the future then we need to:
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* * allocate a second bank of RAM starting at 2TB and working up
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* * fix the DT and ACPI table generation code in QEMU to correctly
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* report two split lumps of RAM to the guest
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* * fix KVM in the host kernel to allow guests with >40 bit address spaces
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* (We don't want to fill all the way up to 512GB with RAM because
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* we might want it for non-RAM purposes later. Conversely it seems
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* reasonable to assume that anybody configuring a VM with a quarter
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* of a terabyte of RAM will be doing it on a host with more than a
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* terabyte of physical address space.)
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*/
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#define RAMLIMIT_GB 255
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#define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
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2013-11-22 21:17:14 +04:00
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/* Addresses and sizes of our components.
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* 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
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* 128MB..256MB is used for miscellaneous device I/O.
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* 256MB..1GB is reserved for possible future PCI support (ie where the
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* PCI memory window will go if we add a PCI host controller).
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* 1GB and up is RAM (which may happily spill over into the
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* high memory region beyond 4GB).
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* This represents a compromise between how much RAM can be given to
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* a 32 bit VM and leaving space for expansion and in particular for PCI.
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2014-06-29 21:38:39 +04:00
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* Note that devices should generally be placed at multiples of 0x10000,
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* to accommodate guests using 64K pages.
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2013-11-22 21:17:14 +04:00
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*/
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static const MemMapEntry a15memmap[] = {
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/* Space up to 0x8000000 is reserved for a boot ROM */
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2015-06-02 14:29:14 +03:00
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[VIRT_FLASH] = { 0, 0x08000000 },
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[VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
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2013-11-22 21:17:14 +04:00
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/* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
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2015-06-02 14:29:14 +03:00
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[VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
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[VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
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[VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
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2015-09-24 03:29:37 +03:00
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/* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
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[VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
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/* This redistributor space allows up to 2*64kB*123 CPUs */
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[VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
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2015-06-02 14:29:14 +03:00
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[VIRT_UART] = { 0x09000000, 0x00001000 },
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[VIRT_RTC] = { 0x09010000, 0x00001000 },
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2015-10-08 18:02:56 +03:00
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[VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
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2015-12-17 16:37:13 +03:00
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[VIRT_GPIO] = { 0x09030000, 0x00001000 },
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2016-01-21 17:15:07 +03:00
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[VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
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2015-06-02 14:29:14 +03:00
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[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
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2013-11-22 21:17:14 +04:00
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/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
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2015-06-02 14:29:14 +03:00
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[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
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2016-03-04 14:30:17 +03:00
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[VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
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2015-06-02 14:29:14 +03:00
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[VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
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[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
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[VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
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2016-03-04 14:30:16 +03:00
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[VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },
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2015-09-07 12:39:29 +03:00
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/* Second PCIe window, 512GB wide at the 512GB boundary */
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[VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL },
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2013-11-22 21:17:14 +04:00
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};
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static const int a15irqmap[] = {
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[VIRT_UART] = 1,
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2014-06-29 21:38:39 +04:00
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[VIRT_RTC] = 2,
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2015-02-13 08:46:08 +03:00
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[VIRT_PCIE] = 3, /* ... to 6 */
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2015-12-17 16:37:13 +03:00
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[VIRT_GPIO] = 7,
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2016-01-21 17:15:07 +03:00
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[VIRT_SECURE_UART] = 8,
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2013-11-22 21:17:14 +04:00
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[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
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2015-06-02 16:56:23 +03:00
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[VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
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2015-06-02 14:29:13 +03:00
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[VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
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2013-11-22 21:17:14 +04:00
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};
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2017-01-09 14:40:21 +03:00
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static const char *valid_cpus[] = {
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2017-09-13 19:04:57 +03:00
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ARM_CPU_TYPE_NAME("cortex-a15"),
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ARM_CPU_TYPE_NAME("cortex-a53"),
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ARM_CPU_TYPE_NAME("cortex-a57"),
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ARM_CPU_TYPE_NAME("host"),
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2013-11-22 21:17:14 +04:00
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};
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2017-09-13 19:04:57 +03:00
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static bool cpu_type_valid(const char *cpu)
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2013-11-22 21:17:14 +04:00
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{
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int i;
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2017-01-09 14:40:21 +03:00
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for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
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if (strcmp(cpu, valid_cpus[i]) == 0) {
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return true;
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2013-11-22 21:17:14 +04:00
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}
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}
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2017-01-09 14:40:21 +03:00
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return false;
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2013-11-22 21:17:14 +04:00
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}
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2017-01-09 14:40:21 +03:00
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static void create_fdt(VirtMachineState *vms)
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2013-11-22 21:17:14 +04:00
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{
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2017-01-09 14:40:21 +03:00
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void *fdt = create_device_tree(&vms->fdt_size);
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2013-11-22 21:17:14 +04:00
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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2017-01-09 14:40:21 +03:00
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vms->fdt = fdt;
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2013-11-22 21:17:14 +04:00
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/* Header */
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2013-11-11 12:14:41 +04:00
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qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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2013-11-22 21:17:14 +04:00
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/*
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* /chosen and /memory nodes must exist for load_dtb
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* to fill in necessary properties later
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*/
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2013-11-11 12:14:41 +04:00
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qemu_fdt_add_subnode(fdt, "/chosen");
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qemu_fdt_add_subnode(fdt, "/memory");
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qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
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2013-11-22 21:17:14 +04:00
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/* Clock node, for the benefit of the UART. The kernel device tree
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* binding documentation claims the PL011 node clock properties are
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* optional but in practice if you omit them the kernel refuses to
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* probe for the device.
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*/
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2017-01-09 14:40:21 +03:00
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vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
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2013-11-11 12:14:41 +04:00
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qemu_fdt_add_subnode(fdt, "/apb-pclk");
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qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
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qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
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qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
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2013-11-22 21:17:14 +04:00
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"clk24mhz");
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2017-01-09 14:40:21 +03:00
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qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
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2013-11-22 21:17:14 +04:00
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2017-06-02 13:51:49 +03:00
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if (have_numa_distance) {
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int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
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uint32_t *matrix = g_malloc0(size);
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int idx, i, j;
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for (i = 0; i < nb_numa_nodes; i++) {
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for (j = 0; j < nb_numa_nodes; j++) {
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idx = (i * nb_numa_nodes + j) * 3;
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matrix[idx + 0] = cpu_to_be32(i);
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matrix[idx + 1] = cpu_to_be32(j);
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matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
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}
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}
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qemu_fdt_add_subnode(fdt, "/distance-map");
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qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
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"numa-distance-map-v1");
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qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
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matrix, size);
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g_free(matrix);
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}
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2014-06-19 21:06:27 +04:00
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}
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|
2017-01-09 14:40:21 +03:00
|
|
|
static void fdt_add_psci_node(const VirtMachineState *vms)
|
2014-06-19 21:06:27 +04:00
|
|
|
{
|
2014-10-24 15:19:13 +04:00
|
|
|
uint32_t cpu_suspend_fn;
|
|
|
|
uint32_t cpu_off_fn;
|
|
|
|
uint32_t cpu_on_fn;
|
|
|
|
uint32_t migrate_fn;
|
2017-01-09 14:40:21 +03:00
|
|
|
void *fdt = vms->fdt;
|
2014-06-19 21:06:27 +04:00
|
|
|
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
|
2017-01-20 14:15:10 +03:00
|
|
|
const char *psci_method;
|
2014-06-19 21:06:27 +04:00
|
|
|
|
2017-01-20 14:15:10 +03:00
|
|
|
switch (vms->psci_conduit) {
|
|
|
|
case QEMU_PSCI_CONDUIT_DISABLED:
|
2016-03-04 14:30:18 +03:00
|
|
|
return;
|
2017-01-20 14:15:10 +03:00
|
|
|
case QEMU_PSCI_CONDUIT_HVC:
|
|
|
|
psci_method = "hvc";
|
|
|
|
break;
|
|
|
|
case QEMU_PSCI_CONDUIT_SMC:
|
|
|
|
psci_method = "smc";
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
2016-03-04 14:30:18 +03:00
|
|
|
}
|
|
|
|
|
2014-10-24 15:19:13 +04:00
|
|
|
qemu_fdt_add_subnode(fdt, "/psci");
|
|
|
|
if (armcpu->psci_version == 2) {
|
|
|
|
const char comp[] = "arm,psci-0.2\0arm,psci";
|
|
|
|
qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
|
2014-08-19 21:56:27 +04:00
|
|
|
|
2014-10-24 15:19:13 +04:00
|
|
|
cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
|
|
|
|
if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
|
|
|
|
cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND;
|
|
|
|
cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON;
|
|
|
|
migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE;
|
|
|
|
} else {
|
|
|
|
cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND;
|
|
|
|
cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON;
|
|
|
|
migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE;
|
2014-06-19 21:06:27 +04:00
|
|
|
}
|
2014-10-24 15:19:13 +04:00
|
|
|
} else {
|
|
|
|
qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
|
2014-06-19 21:06:27 +04:00
|
|
|
|
2014-10-24 15:19:13 +04:00
|
|
|
cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND;
|
|
|
|
cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF;
|
|
|
|
cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON;
|
|
|
|
migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE;
|
2013-11-22 21:17:14 +04:00
|
|
|
}
|
2014-10-24 15:19:13 +04:00
|
|
|
|
|
|
|
/* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
|
|
|
|
* to the instruction that should be used to invoke PSCI functions.
|
|
|
|
* However, the device tree binding uses 'method' instead, so that is
|
|
|
|
* what we should use here.
|
|
|
|
*/
|
2017-01-20 14:15:10 +03:00
|
|
|
qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method);
|
2014-10-24 15:19:13 +04:00
|
|
|
|
|
|
|
qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn);
|
|
|
|
qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn);
|
|
|
|
qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn);
|
|
|
|
qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn);
|
2013-11-22 21:17:14 +04:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
static void fdt_add_timer_nodes(const VirtMachineState *vms)
|
2013-11-22 21:17:14 +04:00
|
|
|
{
|
2017-01-09 14:40:21 +03:00
|
|
|
/* On real hardware these interrupts are level-triggered.
|
|
|
|
* On KVM they were edge-triggered before host kernel version 4.4,
|
|
|
|
* and level-triggered afterwards.
|
|
|
|
* On emulated QEMU they are level-triggered.
|
|
|
|
*
|
|
|
|
* Getting the DTB info about them wrong is awkward for some
|
|
|
|
* guest kernels:
|
|
|
|
* pre-4.8 ignore the DT and leave the interrupt configured
|
|
|
|
* with whatever the GIC reset value (or the bootloader) left it at
|
|
|
|
* 4.8 before rc6 honour the incorrect data by programming it back
|
|
|
|
* into the GIC, causing problems
|
|
|
|
* 4.8rc6 and later ignore the DT and always write "level triggered"
|
|
|
|
* into the GIC
|
|
|
|
*
|
|
|
|
* For backwards-compatibility, virt-2.8 and earlier will continue
|
|
|
|
* to say these are edge-triggered, but later machines will report
|
|
|
|
* the correct information.
|
2013-11-22 21:17:14 +04:00
|
|
|
*/
|
2014-10-24 15:19:11 +04:00
|
|
|
ARMCPU *armcpu;
|
2017-01-09 14:40:21 +03:00
|
|
|
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
|
|
|
|
uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
|
|
|
|
|
|
|
|
if (vmc->claim_edge_triggered_timers) {
|
|
|
|
irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
|
|
|
|
}
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
if (vms->gic_version == 2) {
|
2015-09-24 03:29:37 +03:00
|
|
|
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
|
|
|
|
GIC_FDT_IRQ_PPI_CPU_WIDTH,
|
2017-01-09 14:40:21 +03:00
|
|
|
(1 << vms->smp_cpus) - 1);
|
2015-09-24 03:29:37 +03:00
|
|
|
}
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, "/timer");
|
2014-10-24 15:19:11 +04:00
|
|
|
|
|
|
|
armcpu = ARM_CPU(qemu_get_cpu(0));
|
|
|
|
if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
|
|
|
|
const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
|
2014-10-24 15:19:11 +04:00
|
|
|
compat, sizeof(compat));
|
|
|
|
} else {
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
|
2014-10-24 15:19:11 +04:00
|
|
|
"arm,armv7-timer");
|
|
|
|
}
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
|
|
|
|
qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
|
2015-05-29 13:28:56 +03:00
|
|
|
GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
|
|
|
|
GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
|
|
|
|
GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
|
|
|
|
GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
|
2013-11-22 21:17:14 +04:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
|
2013-11-22 21:17:14 +04:00
|
|
|
{
|
|
|
|
int cpu;
|
2015-09-07 12:39:31 +03:00
|
|
|
int addr_cells = 1;
|
2017-05-10 14:29:54 +03:00
|
|
|
const MachineState *ms = MACHINE(vms);
|
2015-09-07 12:39:31 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* From Documentation/devicetree/bindings/arm/cpus.txt
|
|
|
|
* On ARM v8 64-bit systems value should be set to 2,
|
|
|
|
* that corresponds to the MPIDR_EL1 register size.
|
|
|
|
* If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
|
|
|
|
* in the system, #address-cells can be set to 1, since
|
|
|
|
* MPIDR_EL1[63:32] bits are not used for CPUs
|
|
|
|
* identification.
|
|
|
|
*
|
|
|
|
* Here we actually don't know whether our system is 32- or 64-bit one.
|
|
|
|
* The simplest way to go is to examine affinity IDs of all our CPUs. If
|
|
|
|
* at least one of them has Aff3 populated, we set #address-cells to 2.
|
|
|
|
*/
|
2017-01-09 14:40:21 +03:00
|
|
|
for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
|
2015-09-07 12:39:31 +03:00
|
|
|
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
|
|
|
|
|
|
|
|
if (armcpu->mp_affinity & ARM_AFF3_MASK) {
|
|
|
|
addr_cells = 2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, "/cpus");
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
|
2013-11-22 21:17:14 +04:00
|
|
|
char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
|
|
|
|
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
|
2017-05-10 14:29:54 +03:00
|
|
|
CPUState *cs = CPU(armcpu);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
|
2013-11-22 21:17:14 +04:00
|
|
|
armcpu->dtb_compatible);
|
|
|
|
|
2017-01-20 14:15:10 +03:00
|
|
|
if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
|
|
|
|
&& vms->smp_cpus > 1) {
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename,
|
2013-11-22 21:17:14 +04:00
|
|
|
"enable-method", "psci");
|
|
|
|
}
|
|
|
|
|
2015-09-07 12:39:31 +03:00
|
|
|
if (addr_cells == 2) {
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
|
2015-09-07 12:39:31 +03:00
|
|
|
armcpu->mp_affinity);
|
|
|
|
} else {
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
|
2015-09-07 12:39:31 +03:00
|
|
|
armcpu->mp_affinity);
|
|
|
|
}
|
|
|
|
|
2017-05-10 14:29:54 +03:00
|
|
|
if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
|
|
|
|
ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
|
2016-05-12 15:22:27 +03:00
|
|
|
}
|
|
|
|
|
2013-11-22 21:17:14 +04:00
|
|
|
g_free(nodename);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void fdt_add_its_gic_node(VirtMachineState *vms)
|
2016-10-04 15:28:09 +03:00
|
|
|
{
|
2017-01-09 14:40:21 +03:00
|
|
|
vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
|
|
|
|
qemu_fdt_add_subnode(vms->fdt, "/intc/its");
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible",
|
2016-10-04 15:28:09 +03:00
|
|
|
"arm,gic-v3-its");
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0);
|
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg",
|
|
|
|
2, vms->memmap[VIRT_GIC_ITS].base,
|
|
|
|
2, vms->memmap[VIRT_GIC_ITS].size);
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle);
|
2016-10-04 15:28:09 +03:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void fdt_add_v2m_gic_node(VirtMachineState *vms)
|
2013-11-22 21:17:14 +04:00
|
|
|
{
|
2017-01-09 14:40:21 +03:00
|
|
|
vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
|
|
|
|
qemu_fdt_add_subnode(vms->fdt, "/intc/v2m");
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible",
|
2015-06-02 16:56:23 +03:00
|
|
|
"arm,gic-v2m-frame");
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0);
|
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg",
|
|
|
|
2, vms->memmap[VIRT_GIC_V2M].base,
|
|
|
|
2, vms->memmap[VIRT_GIC_V2M].size);
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle);
|
2015-06-02 16:56:23 +03:00
|
|
|
}
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
static void fdt_add_gic_node(VirtMachineState *vms)
|
2015-06-02 16:56:23 +03:00
|
|
|
{
|
2017-01-09 14:40:21 +03:00
|
|
|
vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
|
|
|
|
|
|
|
|
qemu_fdt_add_subnode(vms->fdt, "/intc");
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3);
|
|
|
|
qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0);
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2);
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2);
|
|
|
|
qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0);
|
2017-01-09 14:40:22 +03:00
|
|
|
if (vms->gic_version == 3) {
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible",
|
2015-09-24 03:29:37 +03:00
|
|
|
"arm,gic-v3");
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg",
|
|
|
|
2, vms->memmap[VIRT_GIC_DIST].base,
|
|
|
|
2, vms->memmap[VIRT_GIC_DIST].size,
|
|
|
|
2, vms->memmap[VIRT_GIC_REDIST].base,
|
|
|
|
2, vms->memmap[VIRT_GIC_REDIST].size);
|
2017-01-20 14:15:11 +03:00
|
|
|
if (vms->virt) {
|
|
|
|
qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts",
|
|
|
|
GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ,
|
|
|
|
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
|
|
|
|
}
|
2015-09-24 03:29:37 +03:00
|
|
|
} else {
|
|
|
|
/* 'cortex-a15-gic' means 'GIC v2' */
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible",
|
2015-09-24 03:29:37 +03:00
|
|
|
"arm,cortex-a15-gic");
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg",
|
|
|
|
2, vms->memmap[VIRT_GIC_DIST].base,
|
|
|
|
2, vms->memmap[VIRT_GIC_DIST].size,
|
|
|
|
2, vms->memmap[VIRT_GIC_CPU].base,
|
|
|
|
2, vms->memmap[VIRT_GIC_CPU].size);
|
2015-09-24 03:29:37 +03:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle);
|
2013-11-22 21:17:14 +04:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
static void fdt_add_pmu_nodes(const VirtMachineState *vms)
|
2016-06-14 17:59:12 +03:00
|
|
|
{
|
|
|
|
CPUState *cpu;
|
|
|
|
ARMCPU *armcpu;
|
|
|
|
uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
|
|
|
|
|
|
|
|
CPU_FOREACH(cpu) {
|
|
|
|
armcpu = ARM_CPU(cpu);
|
2017-09-04 17:21:54 +03:00
|
|
|
if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
|
2016-06-14 17:59:12 +03:00
|
|
|
return;
|
|
|
|
}
|
2017-09-04 17:21:54 +03:00
|
|
|
if (kvm_enabled()) {
|
2017-09-04 17:21:54 +03:00
|
|
|
if (kvm_irqchip_in_kernel()) {
|
|
|
|
kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
|
2017-09-04 17:21:54 +03:00
|
|
|
}
|
2017-09-04 17:21:54 +03:00
|
|
|
kvm_arm_pmu_init(cpu);
|
2017-09-04 17:21:54 +03:00
|
|
|
}
|
2016-06-14 17:59:12 +03:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
if (vms->gic_version == 2) {
|
2016-06-14 17:59:12 +03:00
|
|
|
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
|
|
|
|
GIC_FDT_IRQ_PPI_CPU_WIDTH,
|
2017-01-09 14:40:21 +03:00
|
|
|
(1 << vms->smp_cpus) - 1);
|
2016-06-14 17:59:12 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
armcpu = ARM_CPU(qemu_get_cpu(0));
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, "/pmu");
|
2016-06-14 17:59:12 +03:00
|
|
|
if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
|
|
|
|
const char compat[] = "arm,armv8-pmuv3";
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
|
2016-06-14 17:59:12 +03:00
|
|
|
compat, sizeof(compat));
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
|
2016-06-14 17:59:12 +03:00
|
|
|
GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void create_its(VirtMachineState *vms, DeviceState *gicdev)
|
2016-10-04 15:28:09 +03:00
|
|
|
{
|
|
|
|
const char *itsclass = its_class_name();
|
|
|
|
DeviceState *dev;
|
|
|
|
|
|
|
|
if (!itsclass) {
|
|
|
|
/* Do nothing if not supported */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev = qdev_create(NULL, itsclass);
|
|
|
|
|
|
|
|
object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
|
|
|
|
&error_abort);
|
|
|
|
qdev_init_nofail(dev);
|
2017-01-09 14:40:21 +03:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
|
2016-10-04 15:28:09 +03:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
fdt_add_its_gic_node(vms);
|
2016-10-04 15:28:09 +03:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
|
2015-06-02 16:56:23 +03:00
|
|
|
{
|
|
|
|
int i;
|
2017-01-09 14:40:21 +03:00
|
|
|
int irq = vms->irqmap[VIRT_GIC_V2M];
|
2015-06-02 16:56:23 +03:00
|
|
|
DeviceState *dev;
|
|
|
|
|
|
|
|
dev = qdev_create(NULL, "arm-gicv2m");
|
2017-01-09 14:40:21 +03:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
|
2015-06-02 16:56:23 +03:00
|
|
|
qdev_prop_set_uint32(dev, "base-spi", irq);
|
|
|
|
qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
|
|
|
|
for (i = 0; i < NUM_GICV2M_SPIS; i++) {
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
fdt_add_v2m_gic_node(vms);
|
2015-06-02 16:56:23 +03:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
static void create_gic(VirtMachineState *vms, qemu_irq *pic)
|
2014-05-01 18:24:46 +04:00
|
|
|
{
|
2015-09-24 03:29:37 +03:00
|
|
|
/* We create a standalone GIC */
|
2014-05-01 18:24:46 +04:00
|
|
|
DeviceState *gicdev;
|
|
|
|
SysBusDevice *gicbusdev;
|
2015-08-13 13:26:21 +03:00
|
|
|
const char *gictype;
|
2017-01-09 14:40:22 +03:00
|
|
|
int type = vms->gic_version, i;
|
2014-05-01 18:24:46 +04:00
|
|
|
|
2015-09-24 03:29:37 +03:00
|
|
|
gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
|
2014-05-01 18:24:46 +04:00
|
|
|
|
|
|
|
gicdev = qdev_create(NULL, gictype);
|
2015-09-24 03:29:37 +03:00
|
|
|
qdev_prop_set_uint32(gicdev, "revision", type);
|
2014-05-01 18:24:46 +04:00
|
|
|
qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
|
|
|
|
/* Note that the num-irq property counts both internal and external
|
|
|
|
* interrupts; there are always 32 of the former (mandated by GIC spec).
|
|
|
|
*/
|
|
|
|
qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
|
2015-09-08 19:38:44 +03:00
|
|
|
if (!kvm_irqchip_in_kernel()) {
|
2017-01-09 14:40:22 +03:00
|
|
|
qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
|
2015-09-08 19:38:44 +03:00
|
|
|
}
|
2014-05-01 18:24:46 +04:00
|
|
|
qdev_init_nofail(gicdev);
|
|
|
|
gicbusdev = SYS_BUS_DEVICE(gicdev);
|
2017-01-09 14:40:21 +03:00
|
|
|
sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
|
2015-09-24 03:29:37 +03:00
|
|
|
if (type == 3) {
|
2017-01-09 14:40:21 +03:00
|
|
|
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
|
2015-09-24 03:29:37 +03:00
|
|
|
} else {
|
2017-01-09 14:40:21 +03:00
|
|
|
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
|
2015-09-24 03:29:37 +03:00
|
|
|
}
|
2014-05-01 18:24:46 +04:00
|
|
|
|
2017-01-20 14:15:09 +03:00
|
|
|
/* Wire the outputs from each CPU's generic timer and the GICv3
|
|
|
|
* maintenance interrupt signal to the appropriate GIC PPI inputs,
|
|
|
|
* and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
|
2014-05-01 18:24:46 +04:00
|
|
|
*/
|
|
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
|
|
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
|
2015-08-13 13:26:18 +03:00
|
|
|
int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
|
2015-08-13 13:26:22 +03:00
|
|
|
int irq;
|
|
|
|
/* Mapping from the output timer irq lines from the CPU to the
|
|
|
|
* GIC PPI inputs we use for the virt board.
|
2014-05-01 18:24:46 +04:00
|
|
|
*/
|
2015-08-13 13:26:22 +03:00
|
|
|
const int timer_irq[] = {
|
|
|
|
[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
|
|
|
|
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
|
|
|
|
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
|
|
|
|
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
|
|
|
|
};
|
|
|
|
|
|
|
|
for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
|
|
|
|
qdev_connect_gpio_out(cpudev, irq,
|
|
|
|
qdev_get_gpio_in(gicdev,
|
|
|
|
ppibase + timer_irq[irq]));
|
|
|
|
}
|
2014-05-01 18:24:46 +04:00
|
|
|
|
2017-01-20 14:15:09 +03:00
|
|
|
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
|
|
|
|
qdev_get_gpio_in(gicdev, ppibase
|
|
|
|
+ ARCH_GICV3_MAINT_IRQ));
|
2017-09-04 17:21:53 +03:00
|
|
|
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
|
|
|
|
qdev_get_gpio_in(gicdev, ppibase
|
|
|
|
+ VIRTUAL_PMU_IRQ));
|
2017-01-20 14:15:09 +03:00
|
|
|
|
2014-05-01 18:24:46 +04:00
|
|
|
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
|
2015-05-12 13:57:18 +03:00
|
|
|
sysbus_connect_irq(gicbusdev, i + smp_cpus,
|
|
|
|
qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
|
2017-01-20 14:15:09 +03:00
|
|
|
sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
|
|
|
|
qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
|
|
|
|
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
|
|
|
|
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
|
2014-05-01 18:24:46 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < NUM_IRQS; i++) {
|
|
|
|
pic[i] = qdev_get_gpio_in(gicdev, i);
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
fdt_add_gic_node(vms);
|
2015-06-02 16:56:23 +03:00
|
|
|
|
2017-02-28 15:08:16 +03:00
|
|
|
if (type == 3 && vms->its) {
|
2017-01-09 14:40:21 +03:00
|
|
|
create_its(vms, gicdev);
|
2016-10-17 21:22:17 +03:00
|
|
|
} else if (type == 2) {
|
2017-01-09 14:40:21 +03:00
|
|
|
create_v2m(vms, pic);
|
2015-09-24 03:29:37 +03:00
|
|
|
}
|
2014-05-01 18:24:46 +04:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
|
2016-12-07 16:20:22 +03:00
|
|
|
MemoryRegion *mem, Chardev *chr)
|
2013-11-22 21:17:14 +04:00
|
|
|
{
|
|
|
|
char *nodename;
|
2017-01-09 14:40:21 +03:00
|
|
|
hwaddr base = vms->memmap[uart].base;
|
|
|
|
hwaddr size = vms->memmap[uart].size;
|
|
|
|
int irq = vms->irqmap[uart];
|
2013-11-22 21:17:14 +04:00
|
|
|
const char compat[] = "arm,pl011\0arm,primecell";
|
|
|
|
const char clocknames[] = "uartclk\0apb_pclk";
|
2016-01-21 17:15:07 +03:00
|
|
|
DeviceState *dev = qdev_create(NULL, "pl011");
|
|
|
|
SysBusDevice *s = SYS_BUS_DEVICE(dev);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2016-06-08 05:30:45 +03:00
|
|
|
qdev_prop_set_chr(dev, "chardev", chr);
|
2016-01-21 17:15:07 +03:00
|
|
|
qdev_init_nofail(dev);
|
|
|
|
memory_region_add_subregion(mem, base,
|
|
|
|
sysbus_mmio_get_region(s, 0));
|
|
|
|
sysbus_connect_irq(s, 0, pic[irq]);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
|
|
|
nodename = g_strdup_printf("/pl011@%" PRIx64, base);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
2013-11-22 21:17:14 +04:00
|
|
|
/* Note that we can't use setprop_string because of the embedded NUL */
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, nodename, "compatible",
|
2013-11-22 21:17:14 +04:00
|
|
|
compat, sizeof(compat));
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
|
2013-11-22 21:17:14 +04:00
|
|
|
2, base, 2, size);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
|
2013-11-22 21:17:14 +04:00
|
|
|
GIC_FDT_IRQ_TYPE_SPI, irq,
|
2014-09-12 17:06:50 +04:00
|
|
|
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
|
|
|
|
vms->clock_phandle, vms->clock_phandle);
|
|
|
|
qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
|
2013-11-22 21:17:14 +04:00
|
|
|
clocknames, sizeof(clocknames));
|
2014-09-12 17:06:47 +04:00
|
|
|
|
2016-01-21 17:15:07 +03:00
|
|
|
if (uart == VIRT_UART) {
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
|
2016-01-21 17:15:07 +03:00
|
|
|
} else {
|
|
|
|
/* Mark as not usable by the normal world */
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
|
2016-01-21 17:15:07 +03:00
|
|
|
}
|
|
|
|
|
2013-11-22 21:17:14 +04:00
|
|
|
g_free(nodename);
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
|
2014-06-29 21:38:39 +04:00
|
|
|
{
|
|
|
|
char *nodename;
|
2017-01-09 14:40:21 +03:00
|
|
|
hwaddr base = vms->memmap[VIRT_RTC].base;
|
|
|
|
hwaddr size = vms->memmap[VIRT_RTC].size;
|
|
|
|
int irq = vms->irqmap[VIRT_RTC];
|
2014-06-29 21:38:39 +04:00
|
|
|
const char compat[] = "arm,pl031\0arm,primecell";
|
|
|
|
|
|
|
|
sysbus_create_simple("pl031", base, pic[irq]);
|
|
|
|
|
|
|
|
nodename = g_strdup_printf("/pl031@%" PRIx64, base);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
|
|
|
qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
|
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
|
2014-06-29 21:38:39 +04:00
|
|
|
2, base, 2, size);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
|
2014-06-29 21:38:39 +04:00
|
|
|
GIC_FDT_IRQ_TYPE_SPI, irq,
|
2014-09-12 17:06:50 +04:00
|
|
|
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
|
2014-06-29 21:38:39 +04:00
|
|
|
g_free(nodename);
|
|
|
|
}
|
|
|
|
|
2016-03-30 19:27:22 +03:00
|
|
|
static DeviceState *gpio_key_dev;
|
2015-12-17 16:37:14 +03:00
|
|
|
static void virt_powerdown_req(Notifier *n, void *opaque)
|
|
|
|
{
|
|
|
|
/* use gpio Pin 3 for power button event */
|
2016-03-30 19:27:22 +03:00
|
|
|
qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
|
2015-12-17 16:37:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static Notifier virt_system_powerdown_notifier = {
|
|
|
|
.notify = virt_powerdown_req
|
|
|
|
};
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
|
2015-12-17 16:37:13 +03:00
|
|
|
{
|
|
|
|
char *nodename;
|
2016-03-30 19:27:22 +03:00
|
|
|
DeviceState *pl061_dev;
|
2017-01-09 14:40:21 +03:00
|
|
|
hwaddr base = vms->memmap[VIRT_GPIO].base;
|
|
|
|
hwaddr size = vms->memmap[VIRT_GPIO].size;
|
|
|
|
int irq = vms->irqmap[VIRT_GPIO];
|
2015-12-17 16:37:13 +03:00
|
|
|
const char compat[] = "arm,pl061\0arm,primecell";
|
|
|
|
|
2015-12-17 16:37:14 +03:00
|
|
|
pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
|
2015-12-17 16:37:13 +03:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
|
2015-12-17 16:37:13 +03:00
|
|
|
nodename = g_strdup_printf("/pl061@%" PRIx64, base);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
|
2015-12-17 16:37:13 +03:00
|
|
|
2, base, 2, size);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
|
|
|
|
qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
|
|
|
|
qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
|
2015-12-17 16:37:13 +03:00
|
|
|
GIC_FDT_IRQ_TYPE_SPI, irq,
|
|
|
|
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
|
2015-12-17 16:37:14 +03:00
|
|
|
|
2016-03-30 19:27:22 +03:00
|
|
|
gpio_key_dev = sysbus_create_simple("gpio-key", -1,
|
|
|
|
qdev_get_gpio_in(pl061_dev, 3));
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
|
2015-12-17 16:37:14 +03:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
|
2015-12-17 16:37:14 +03:00
|
|
|
"label", "GPIO Key Poweroff");
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
|
2015-12-17 16:37:14 +03:00
|
|
|
KEY_POWER);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
|
2015-12-17 16:37:14 +03:00
|
|
|
"gpios", phandle, 3, 0);
|
2015-12-17 16:37:13 +03:00
|
|
|
|
2015-12-17 16:37:14 +03:00
|
|
|
/* connect powerdown request */
|
|
|
|
qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
|
|
|
|
|
2015-12-17 16:37:13 +03:00
|
|
|
g_free(nodename);
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
|
2013-11-22 21:17:14 +04:00
|
|
|
{
|
|
|
|
int i;
|
2017-01-09 14:40:21 +03:00
|
|
|
hwaddr size = vms->memmap[VIRT_MMIO].size;
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2015-02-05 16:37:23 +03:00
|
|
|
/* We create the transports in forwards order. Since qbus_realize()
|
|
|
|
* prepends (not appends) new child buses, the incrementing loop below will
|
|
|
|
* create a list of virtio-mmio buses with decreasing base addresses.
|
|
|
|
*
|
|
|
|
* When a -device option is processed from the command line,
|
|
|
|
* qbus_find_recursive() picks the next free virtio-mmio bus in forwards
|
|
|
|
* order. The upshot is that -device options in increasing command line
|
|
|
|
* order are mapped to virtio-mmio buses with decreasing base addresses.
|
|
|
|
*
|
|
|
|
* When this code was originally written, that arrangement ensured that the
|
|
|
|
* guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
|
|
|
|
* the first -device on the command line. (The end-to-end order is a
|
|
|
|
* function of this loop, qbus_realize(), qbus_find_recursive(), and the
|
|
|
|
* guest kernel's name-to-address assignment strategy.)
|
|
|
|
*
|
|
|
|
* Meanwhile, the kernel's traversal seems to have been reversed; see eg.
|
|
|
|
* the message, if not necessarily the code, of commit 70161ff336.
|
|
|
|
* Therefore the loop now establishes the inverse of the original intent.
|
|
|
|
*
|
|
|
|
* Unfortunately, we can't counteract the kernel change by reversing the
|
|
|
|
* loop; it would break existing command lines.
|
|
|
|
*
|
|
|
|
* In any case, the kernel makes no guarantee about the stability of
|
|
|
|
* enumeration order of virtio devices (as demonstrated by it changing
|
|
|
|
* between kernel versions). For reliable and stable identification
|
|
|
|
* of disks users must use UUIDs or similar mechanisms.
|
2013-11-22 21:17:14 +04:00
|
|
|
*/
|
|
|
|
for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
|
2017-01-09 14:40:21 +03:00
|
|
|
int irq = vms->irqmap[VIRT_MMIO] + i;
|
|
|
|
hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
|
2013-11-22 21:17:14 +04:00
|
|
|
|
|
|
|
sysbus_create_simple("virtio-mmio", base, pic[irq]);
|
|
|
|
}
|
|
|
|
|
2015-02-05 16:37:23 +03:00
|
|
|
/* We add dtb nodes in reverse order so that they appear in the finished
|
|
|
|
* device tree lowest address first.
|
|
|
|
*
|
|
|
|
* Note that this mapping is independent of the loop above. The previous
|
|
|
|
* loop influences virtio device to virtio transport assignment, whereas
|
|
|
|
* this loop controls how virtio transports are laid out in the dtb.
|
|
|
|
*/
|
2013-11-22 21:17:14 +04:00
|
|
|
for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
|
|
|
|
char *nodename;
|
2017-01-09 14:40:21 +03:00
|
|
|
int irq = vms->irqmap[VIRT_MMIO] + i;
|
|
|
|
hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
|
2013-11-22 21:17:14 +04:00
|
|
|
|
|
|
|
nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename,
|
2013-11-11 12:14:41 +04:00
|
|
|
"compatible", "virtio,mmio");
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
|
2013-11-11 12:14:41 +04:00
|
|
|
2, base, 2, size);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
|
2013-11-11 12:14:41 +04:00
|
|
|
GIC_FDT_IRQ_TYPE_SPI, irq,
|
|
|
|
GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
|
2017-02-10 20:40:29 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
|
2013-11-22 21:17:14 +04:00
|
|
|
g_free(nodename);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-09-12 17:06:48 +04:00
|
|
|
static void create_one_flash(const char *name, hwaddr flashbase,
|
2016-03-04 14:30:18 +03:00
|
|
|
hwaddr flashsize, const char *file,
|
|
|
|
MemoryRegion *sysmem)
|
2014-09-12 17:06:48 +04:00
|
|
|
{
|
|
|
|
/* Create and map a single flash device. We use the same
|
|
|
|
* parameters as the flash devices on the Versatile Express board.
|
|
|
|
*/
|
|
|
|
DriveInfo *dinfo = drive_get_next(IF_PFLASH);
|
|
|
|
DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
|
2016-03-04 14:30:17 +03:00
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
2014-09-12 17:06:48 +04:00
|
|
|
const uint64_t sectorlength = 256 * 1024;
|
|
|
|
|
2015-03-09 21:17:26 +03:00
|
|
|
if (dinfo) {
|
|
|
|
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
|
|
|
|
&error_abort);
|
2014-09-12 17:06:48 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength);
|
|
|
|
qdev_prop_set_uint64(dev, "sector-length", sectorlength);
|
|
|
|
qdev_prop_set_uint8(dev, "width", 4);
|
|
|
|
qdev_prop_set_uint8(dev, "device-width", 2);
|
2015-04-08 14:53:29 +03:00
|
|
|
qdev_prop_set_bit(dev, "big-endian", false);
|
2014-09-12 17:06:48 +04:00
|
|
|
qdev_prop_set_uint16(dev, "id0", 0x89);
|
|
|
|
qdev_prop_set_uint16(dev, "id1", 0x18);
|
|
|
|
qdev_prop_set_uint16(dev, "id2", 0x00);
|
|
|
|
qdev_prop_set_uint16(dev, "id3", 0x00);
|
|
|
|
qdev_prop_set_string(dev, "name", name);
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
|
2016-03-04 14:30:18 +03:00
|
|
|
memory_region_add_subregion(sysmem, flashbase,
|
|
|
|
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
|
2014-09-12 17:06:48 +04:00
|
|
|
|
2016-03-04 14:30:17 +03:00
|
|
|
if (file) {
|
2015-03-05 05:58:32 +03:00
|
|
|
char *fn;
|
2015-04-01 19:57:29 +03:00
|
|
|
int image_size;
|
2014-09-12 17:06:48 +04:00
|
|
|
|
|
|
|
if (drive_get(IF_PFLASH, 0, 0)) {
|
|
|
|
error_report("The contents of the first flash device may be "
|
|
|
|
"specified with -bios or with -drive if=pflash... "
|
|
|
|
"but you cannot use both options at once");
|
|
|
|
exit(1);
|
|
|
|
}
|
2016-03-04 14:30:17 +03:00
|
|
|
fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file);
|
2015-04-01 19:57:29 +03:00
|
|
|
if (!fn) {
|
2016-03-04 14:30:17 +03:00
|
|
|
error_report("Could not find ROM image '%s'", file);
|
2015-04-01 19:57:29 +03:00
|
|
|
exit(1);
|
|
|
|
}
|
2016-03-04 14:30:17 +03:00
|
|
|
image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0));
|
2015-04-01 19:57:29 +03:00
|
|
|
g_free(fn);
|
|
|
|
if (image_size < 0) {
|
2016-03-04 14:30:17 +03:00
|
|
|
error_report("Could not load ROM image '%s'", file);
|
2014-09-12 17:06:48 +04:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
2016-03-04 14:30:17 +03:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void create_flash(const VirtMachineState *vms,
|
2016-03-04 14:30:18 +03:00
|
|
|
MemoryRegion *sysmem,
|
|
|
|
MemoryRegion *secure_sysmem)
|
2016-03-04 14:30:17 +03:00
|
|
|
{
|
|
|
|
/* Create two flash devices to fill the VIRT_FLASH space in the memmap.
|
|
|
|
* Any file passed via -bios goes in the first of these.
|
2016-03-04 14:30:18 +03:00
|
|
|
* sysmem is the system memory space. secure_sysmem is the secure view
|
|
|
|
* of the system, and the first flash device should be made visible only
|
|
|
|
* there. The second flash device is visible to both secure and nonsecure.
|
|
|
|
* If sysmem == secure_sysmem this means there is no separate Secure
|
|
|
|
* address space and both flash devices are generally visible.
|
2016-03-04 14:30:17 +03:00
|
|
|
*/
|
2017-01-09 14:40:21 +03:00
|
|
|
hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
|
|
|
|
hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
|
2016-03-04 14:30:17 +03:00
|
|
|
char *nodename;
|
2014-09-12 17:06:48 +04:00
|
|
|
|
2016-03-04 14:30:18 +03:00
|
|
|
create_one_flash("virt.flash0", flashbase, flashsize,
|
|
|
|
bios_name, secure_sysmem);
|
|
|
|
create_one_flash("virt.flash1", flashbase + flashsize, flashsize,
|
|
|
|
NULL, sysmem);
|
2014-09-12 17:06:48 +04:00
|
|
|
|
2016-03-04 14:30:18 +03:00
|
|
|
if (sysmem == secure_sysmem) {
|
|
|
|
/* Report both flash devices as a single node in the DT */
|
|
|
|
nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
|
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
|
2016-03-04 14:30:18 +03:00
|
|
|
2, flashbase, 2, flashsize,
|
|
|
|
2, flashbase + flashsize, 2, flashsize);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
|
2016-03-04 14:30:18 +03:00
|
|
|
g_free(nodename);
|
|
|
|
} else {
|
|
|
|
/* Report the devices as separate nodes so we can mark one as
|
|
|
|
* only visible to the secure world.
|
|
|
|
*/
|
|
|
|
nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
|
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
|
2016-03-04 14:30:18 +03:00
|
|
|
2, flashbase, 2, flashsize);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
|
2016-03-04 14:30:18 +03:00
|
|
|
g_free(nodename);
|
|
|
|
|
|
|
|
nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
|
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
|
2016-03-04 14:30:18 +03:00
|
|
|
2, flashbase + flashsize, 2, flashsize);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
|
2016-03-04 14:30:18 +03:00
|
|
|
g_free(nodename);
|
|
|
|
}
|
2014-09-12 17:06:48 +04:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:23 +03:00
|
|
|
static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
|
arm: add fw_cfg to "virt" board
fw_cfg already supports exposure over MMIO (used in ppc/mac_newworld.c,
ppc/mac_oldworld.c, sparc/sun4m.c); we can easily add it to the "virt"
board.
Because MMIO access is slow on ARM KVM, we enable the guest, with
fw_cfg_init_mem_wide(), to transfer up to 8 bytes with a single access.
This has been measured to speed up transfers up to 7.5-fold, relative to
single byte data access, on both ARM KVM and x86_64 TCG.
The MMIO register block of fw_cfg is advertized in the device tree. As
base address we pick 0x09020000, which conforms to the comment preceding
"a15memmap": it falls in the miscellaneous device I/O range 128MB..256MB,
and it is aligned at 64KB. The DTB properties follow the documentation in
the Linux source file "Documentation/devicetree/bindings/arm/fw-cfg.txt".
fw_cfg automatically exports a number of files to the guest; for example,
"bootorder" (see fw_cfg_machine_reset()).
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-9-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 15:11:42 +03:00
|
|
|
{
|
2017-01-09 14:40:21 +03:00
|
|
|
hwaddr base = vms->memmap[VIRT_FW_CFG].base;
|
|
|
|
hwaddr size = vms->memmap[VIRT_FW_CFG].size;
|
2016-11-15 15:17:15 +03:00
|
|
|
FWCfgState *fw_cfg;
|
arm: add fw_cfg to "virt" board
fw_cfg already supports exposure over MMIO (used in ppc/mac_newworld.c,
ppc/mac_oldworld.c, sparc/sun4m.c); we can easily add it to the "virt"
board.
Because MMIO access is slow on ARM KVM, we enable the guest, with
fw_cfg_init_mem_wide(), to transfer up to 8 bytes with a single access.
This has been measured to speed up transfers up to 7.5-fold, relative to
single byte data access, on both ARM KVM and x86_64 TCG.
The MMIO register block of fw_cfg is advertized in the device tree. As
base address we pick 0x09020000, which conforms to the comment preceding
"a15memmap": it falls in the miscellaneous device I/O range 128MB..256MB,
and it is aligned at 64KB. The DTB properties follow the documentation in
the Linux source file "Documentation/devicetree/bindings/arm/fw-cfg.txt".
fw_cfg automatically exports a number of files to the guest; for example,
"bootorder" (see fw_cfg_machine_reset()).
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-9-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 15:11:42 +03:00
|
|
|
char *nodename;
|
|
|
|
|
2016-11-15 15:17:15 +03:00
|
|
|
fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
|
arm: add fw_cfg to "virt" board
fw_cfg already supports exposure over MMIO (used in ppc/mac_newworld.c,
ppc/mac_oldworld.c, sparc/sun4m.c); we can easily add it to the "virt"
board.
Because MMIO access is slow on ARM KVM, we enable the guest, with
fw_cfg_init_mem_wide(), to transfer up to 8 bytes with a single access.
This has been measured to speed up transfers up to 7.5-fold, relative to
single byte data access, on both ARM KVM and x86_64 TCG.
The MMIO register block of fw_cfg is advertized in the device tree. As
base address we pick 0x09020000, which conforms to the comment preceding
"a15memmap": it falls in the miscellaneous device I/O range 128MB..256MB,
and it is aligned at 64KB. The DTB properties follow the documentation in
the Linux source file "Documentation/devicetree/bindings/arm/fw-cfg.txt".
fw_cfg automatically exports a number of files to the guest; for example,
"bootorder" (see fw_cfg_machine_reset()).
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-9-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 15:11:42 +03:00
|
|
|
|
|
|
|
nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename,
|
arm: add fw_cfg to "virt" board
fw_cfg already supports exposure over MMIO (used in ppc/mac_newworld.c,
ppc/mac_oldworld.c, sparc/sun4m.c); we can easily add it to the "virt"
board.
Because MMIO access is slow on ARM KVM, we enable the guest, with
fw_cfg_init_mem_wide(), to transfer up to 8 bytes with a single access.
This has been measured to speed up transfers up to 7.5-fold, relative to
single byte data access, on both ARM KVM and x86_64 TCG.
The MMIO register block of fw_cfg is advertized in the device tree. As
base address we pick 0x09020000, which conforms to the comment preceding
"a15memmap": it falls in the miscellaneous device I/O range 128MB..256MB,
and it is aligned at 64KB. The DTB properties follow the documentation in
the Linux source file "Documentation/devicetree/bindings/arm/fw-cfg.txt".
fw_cfg automatically exports a number of files to the guest; for example,
"bootorder" (see fw_cfg_machine_reset()).
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-9-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 15:11:42 +03:00
|
|
|
"compatible", "qemu,fw-cfg-mmio");
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
|
arm: add fw_cfg to "virt" board
fw_cfg already supports exposure over MMIO (used in ppc/mac_newworld.c,
ppc/mac_oldworld.c, sparc/sun4m.c); we can easily add it to the "virt"
board.
Because MMIO access is slow on ARM KVM, we enable the guest, with
fw_cfg_init_mem_wide(), to transfer up to 8 bytes with a single access.
This has been measured to speed up transfers up to 7.5-fold, relative to
single byte data access, on both ARM KVM and x86_64 TCG.
The MMIO register block of fw_cfg is advertized in the device tree. As
base address we pick 0x09020000, which conforms to the comment preceding
"a15memmap": it falls in the miscellaneous device I/O range 128MB..256MB,
and it is aligned at 64KB. The DTB properties follow the documentation in
the Linux source file "Documentation/devicetree/bindings/arm/fw-cfg.txt".
fw_cfg automatically exports a number of files to the guest; for example,
"bootorder" (see fw_cfg_machine_reset()).
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-9-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 15:11:42 +03:00
|
|
|
2, base, 2, size);
|
2017-02-10 20:40:29 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
|
arm: add fw_cfg to "virt" board
fw_cfg already supports exposure over MMIO (used in ppc/mac_newworld.c,
ppc/mac_oldworld.c, sparc/sun4m.c); we can easily add it to the "virt"
board.
Because MMIO access is slow on ARM KVM, we enable the guest, with
fw_cfg_init_mem_wide(), to transfer up to 8 bytes with a single access.
This has been measured to speed up transfers up to 7.5-fold, relative to
single byte data access, on both ARM KVM and x86_64 TCG.
The MMIO register block of fw_cfg is advertized in the device tree. As
base address we pick 0x09020000, which conforms to the comment preceding
"a15memmap": it falls in the miscellaneous device I/O range 128MB..256MB,
and it is aligned at 64KB. The DTB properties follow the documentation in
the Linux source file "Documentation/devicetree/bindings/arm/fw-cfg.txt".
fw_cfg automatically exports a number of files to the guest; for example,
"bootorder" (see fw_cfg_machine_reset()).
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-9-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 15:11:42 +03:00
|
|
|
g_free(nodename);
|
2017-01-09 14:40:23 +03:00
|
|
|
return fw_cfg;
|
arm: add fw_cfg to "virt" board
fw_cfg already supports exposure over MMIO (used in ppc/mac_newworld.c,
ppc/mac_oldworld.c, sparc/sun4m.c); we can easily add it to the "virt"
board.
Because MMIO access is slow on ARM KVM, we enable the guest, with
fw_cfg_init_mem_wide(), to transfer up to 8 bytes with a single access.
This has been measured to speed up transfers up to 7.5-fold, relative to
single byte data access, on both ARM KVM and x86_64 TCG.
The MMIO register block of fw_cfg is advertized in the device tree. As
base address we pick 0x09020000, which conforms to the comment preceding
"a15memmap": it falls in the miscellaneous device I/O range 128MB..256MB,
and it is aligned at 64KB. The DTB properties follow the documentation in
the Linux source file "Documentation/devicetree/bindings/arm/fw-cfg.txt".
fw_cfg automatically exports a number of files to the guest; for example,
"bootorder" (see fw_cfg_machine_reset()).
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-9-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 15:11:42 +03:00
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void create_pcie_irq_map(const VirtMachineState *vms,
|
2017-01-09 14:40:21 +03:00
|
|
|
uint32_t gic_phandle,
|
2015-02-13 08:46:08 +03:00
|
|
|
int first_irq, const char *nodename)
|
|
|
|
{
|
|
|
|
int devfn, pin;
|
2015-06-02 16:56:23 +03:00
|
|
|
uint32_t full_irq_map[4 * 4 * 10] = { 0 };
|
2015-02-13 08:46:08 +03:00
|
|
|
uint32_t *irq_map = full_irq_map;
|
|
|
|
|
|
|
|
for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
|
|
|
|
for (pin = 0; pin < 4; pin++) {
|
|
|
|
int irq_type = GIC_FDT_IRQ_TYPE_SPI;
|
|
|
|
int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
|
|
|
|
int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
uint32_t map[] = {
|
|
|
|
devfn << 8, 0, 0, /* devfn */
|
|
|
|
pin + 1, /* PCI pin */
|
2015-06-02 16:56:23 +03:00
|
|
|
gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
|
2015-02-13 08:46:08 +03:00
|
|
|
|
|
|
|
/* Convert map to big endian */
|
2015-06-02 16:56:23 +03:00
|
|
|
for (i = 0; i < 10; i++) {
|
2015-02-13 08:46:08 +03:00
|
|
|
irq_map[i] = cpu_to_be32(map[i]);
|
|
|
|
}
|
2015-06-02 16:56:23 +03:00
|
|
|
irq_map += 10;
|
2015-02-13 08:46:08 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
|
2015-02-13 08:46:08 +03:00
|
|
|
full_irq_map, sizeof(full_irq_map));
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
|
2015-02-13 08:46:08 +03:00
|
|
|
0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
|
|
|
|
0x7 /* PCI irq */);
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
static void create_pcie(const VirtMachineState *vms, qemu_irq *pic)
|
2015-02-13 08:46:08 +03:00
|
|
|
{
|
2017-01-09 14:40:21 +03:00
|
|
|
hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
|
|
|
|
hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
|
|
|
|
hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base;
|
|
|
|
hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size;
|
|
|
|
hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
|
|
|
|
hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
|
|
|
|
hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base;
|
|
|
|
hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size;
|
2015-05-29 13:28:54 +03:00
|
|
|
hwaddr base = base_mmio;
|
|
|
|
int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
|
2017-01-09 14:40:21 +03:00
|
|
|
int irq = vms->irqmap[VIRT_PCIE];
|
2015-02-13 08:46:08 +03:00
|
|
|
MemoryRegion *mmio_alias;
|
|
|
|
MemoryRegion *mmio_reg;
|
|
|
|
MemoryRegion *ecam_alias;
|
|
|
|
MemoryRegion *ecam_reg;
|
|
|
|
DeviceState *dev;
|
|
|
|
char *nodename;
|
|
|
|
int i;
|
2016-01-11 18:52:18 +03:00
|
|
|
PCIHostState *pci;
|
2015-02-13 08:46:08 +03:00
|
|
|
|
|
|
|
dev = qdev_create(NULL, TYPE_GPEX_HOST);
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
|
|
|
|
/* Map only the first size_ecam bytes of ECAM space */
|
|
|
|
ecam_alias = g_new0(MemoryRegion, 1);
|
|
|
|
ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
|
|
|
|
memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
|
|
|
|
ecam_reg, 0, size_ecam);
|
|
|
|
memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
|
|
|
|
|
|
|
|
/* Map the MMIO window into system address space so as to expose
|
|
|
|
* the section of PCI MMIO space which starts at the same base address
|
|
|
|
* (ie 1:1 mapping for that part of PCI MMIO space visible through
|
|
|
|
* the window).
|
|
|
|
*/
|
|
|
|
mmio_alias = g_new0(MemoryRegion, 1);
|
|
|
|
mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
|
|
|
|
memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
|
|
|
|
mmio_reg, base_mmio, size_mmio);
|
|
|
|
memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
|
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
if (vms->highmem) {
|
2015-09-07 12:39:29 +03:00
|
|
|
/* Map high MMIO space */
|
|
|
|
MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
|
|
|
|
|
|
|
|
memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
|
|
|
|
mmio_reg, base_mmio_high, size_mmio_high);
|
|
|
|
memory_region_add_subregion(get_system_memory(), base_mmio_high,
|
|
|
|
high_mmio_alias);
|
|
|
|
}
|
|
|
|
|
2015-02-13 08:46:08 +03:00
|
|
|
/* Map IO port space */
|
2015-05-29 13:28:54 +03:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
|
2015-02-13 08:46:08 +03:00
|
|
|
|
|
|
|
for (i = 0; i < GPEX_NUM_IRQS; i++) {
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
|
2017-09-14 20:43:19 +03:00
|
|
|
gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
|
2015-02-13 08:46:08 +03:00
|
|
|
}
|
|
|
|
|
2016-01-11 18:52:18 +03:00
|
|
|
pci = PCI_HOST_BRIDGE(dev);
|
|
|
|
if (pci->bus) {
|
|
|
|
for (i = 0; i < nb_nics; i++) {
|
|
|
|
NICInfo *nd = &nd_table[i];
|
|
|
|
|
|
|
|
if (!nd->model) {
|
|
|
|
nd->model = g_strdup("virtio");
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-02-13 08:46:08 +03:00
|
|
|
nodename = g_strdup_printf("/pcie@%" PRIx64, base);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename,
|
2015-02-13 08:46:08 +03:00
|
|
|
"compatible", "pci-host-ecam-generic");
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
|
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
|
|
|
|
qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
|
2015-02-13 08:46:08 +03:00
|
|
|
nr_pcie_buses - 1);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
|
2015-02-13 08:46:08 +03:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
if (vms->msi_phandle) {
|
|
|
|
qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
|
|
|
|
vms->msi_phandle);
|
2015-09-24 03:29:37 +03:00
|
|
|
}
|
2015-06-02 16:56:23 +03:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
|
2015-02-13 08:46:08 +03:00
|
|
|
2, base_ecam, 2, size_ecam);
|
2015-09-07 12:39:29 +03:00
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
if (vms->highmem) {
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
|
2015-09-07 12:39:29 +03:00
|
|
|
1, FDT_PCI_RANGE_IOPORT, 2, 0,
|
|
|
|
2, base_pio, 2, size_pio,
|
|
|
|
1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
|
|
|
|
2, base_mmio, 2, size_mmio,
|
|
|
|
1, FDT_PCI_RANGE_MMIO_64BIT,
|
|
|
|
2, base_mmio_high,
|
|
|
|
2, base_mmio_high, 2, size_mmio_high);
|
|
|
|
} else {
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
|
2015-09-07 12:39:29 +03:00
|
|
|
1, FDT_PCI_RANGE_IOPORT, 2, 0,
|
|
|
|
2, base_pio, 2, size_pio,
|
|
|
|
1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
|
|
|
|
2, base_mmio, 2, size_mmio);
|
|
|
|
}
|
2015-02-13 08:46:08 +03:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
|
|
|
|
create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
|
2015-02-13 08:46:08 +03:00
|
|
|
|
|
|
|
g_free(nodename);
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic)
|
2015-06-02 14:29:13 +03:00
|
|
|
{
|
|
|
|
DeviceState *dev;
|
|
|
|
SysBusDevice *s;
|
|
|
|
int i;
|
|
|
|
ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1);
|
|
|
|
MemoryRegion *sysmem = get_system_memory();
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
platform_bus_params.platform_bus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
|
|
|
|
platform_bus_params.platform_bus_size = vms->memmap[VIRT_PLATFORM_BUS].size;
|
|
|
|
platform_bus_params.platform_bus_first_irq = vms->irqmap[VIRT_PLATFORM_BUS];
|
2015-06-02 14:29:13 +03:00
|
|
|
platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS;
|
|
|
|
|
|
|
|
fdt_params->system_params = &platform_bus_params;
|
2017-01-09 14:40:21 +03:00
|
|
|
fdt_params->binfo = &vms->bootinfo;
|
2015-06-02 14:29:13 +03:00
|
|
|
fdt_params->intc = "/intc";
|
|
|
|
/*
|
|
|
|
* register a machine init done notifier that creates the device tree
|
|
|
|
* nodes of the platform bus and its children dynamic sysbus devices
|
|
|
|
*/
|
|
|
|
arm_register_platform_bus_fdt_creator(fdt_params);
|
|
|
|
|
|
|
|
dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
|
|
|
|
dev->id = TYPE_PLATFORM_BUS_DEVICE;
|
|
|
|
qdev_prop_set_uint32(dev, "num_irqs",
|
|
|
|
platform_bus_params.platform_bus_num_irqs);
|
|
|
|
qdev_prop_set_uint32(dev, "mmio_size",
|
|
|
|
platform_bus_params.platform_bus_size);
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
s = SYS_BUS_DEVICE(dev);
|
|
|
|
|
|
|
|
for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) {
|
|
|
|
int irqn = platform_bus_params.platform_bus_first_irq + i;
|
|
|
|
sysbus_connect_irq(s, i, pic[irqn]);
|
|
|
|
}
|
|
|
|
|
|
|
|
memory_region_add_subregion(sysmem,
|
|
|
|
platform_bus_params.platform_bus_base,
|
|
|
|
sysbus_mmio_get_region(s, 0));
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
static void create_secure_ram(VirtMachineState *vms,
|
2017-01-09 14:40:21 +03:00
|
|
|
MemoryRegion *secure_sysmem)
|
2016-03-04 14:30:17 +03:00
|
|
|
{
|
|
|
|
MemoryRegion *secram = g_new(MemoryRegion, 1);
|
|
|
|
char *nodename;
|
2017-01-09 14:40:21 +03:00
|
|
|
hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
|
|
|
|
hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
|
2016-03-04 14:30:17 +03:00
|
|
|
|
2017-07-07 17:42:53 +03:00
|
|
|
memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
|
|
|
|
&error_fatal);
|
2016-03-04 14:30:17 +03:00
|
|
|
memory_region_add_subregion(secure_sysmem, base, secram);
|
|
|
|
|
|
|
|
nodename = g_strdup_printf("/secram@%" PRIx64, base);
|
2017-01-09 14:40:21 +03:00
|
|
|
qemu_fdt_add_subnode(vms->fdt, nodename);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
|
|
|
|
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
|
|
|
|
qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
|
2016-03-04 14:30:17 +03:00
|
|
|
|
|
|
|
g_free(nodename);
|
|
|
|
}
|
|
|
|
|
2013-11-22 21:17:14 +04:00
|
|
|
static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
|
|
|
|
{
|
2017-01-09 14:40:21 +03:00
|
|
|
const VirtMachineState *board = container_of(binfo, VirtMachineState,
|
|
|
|
bootinfo);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
|
|
|
*fdt_size = board->fdt_size;
|
|
|
|
return board->fdt;
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
static void virt_build_smbios(VirtMachineState *vms)
|
2015-09-07 12:39:29 +03:00
|
|
|
{
|
|
|
|
uint8_t *smbios_tables, *smbios_anchor;
|
|
|
|
size_t smbios_tables_len, smbios_anchor_len;
|
2015-10-16 13:14:53 +03:00
|
|
|
const char *product = "QEMU Virtual Machine";
|
2015-09-07 12:39:29 +03:00
|
|
|
|
2017-01-09 14:40:23 +03:00
|
|
|
if (!vms->fw_cfg) {
|
2015-09-07 12:39:29 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-10-16 13:14:53 +03:00
|
|
|
if (kvm_enabled()) {
|
|
|
|
product = "KVM Virtual Machine";
|
|
|
|
}
|
|
|
|
|
|
|
|
smbios_set_defaults("QEMU", product,
|
2015-09-07 12:39:29 +03:00
|
|
|
"1.0", false, true, SMBIOS_ENTRY_POINT_30);
|
|
|
|
|
|
|
|
smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len,
|
|
|
|
&smbios_anchor, &smbios_anchor_len);
|
|
|
|
|
|
|
|
if (smbios_anchor) {
|
2017-01-09 14:40:23 +03:00
|
|
|
fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
|
2015-09-07 12:39:29 +03:00
|
|
|
smbios_tables, smbios_tables_len);
|
2017-01-09 14:40:23 +03:00
|
|
|
fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
|
2015-09-07 12:39:29 +03:00
|
|
|
smbios_anchor, smbios_anchor_len);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-29 13:28:59 +03:00
|
|
|
static
|
2017-01-09 14:40:22 +03:00
|
|
|
void virt_machine_done(Notifier *notifier, void *data)
|
2015-05-29 13:28:59 +03:00
|
|
|
{
|
2017-01-09 14:40:22 +03:00
|
|
|
VirtMachineState *vms = container_of(notifier, VirtMachineState,
|
|
|
|
machine_done);
|
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
virt_acpi_setup(vms);
|
|
|
|
virt_build_smbios(vms);
|
2015-05-29 13:28:59 +03:00
|
|
|
}
|
|
|
|
|
2017-05-03 15:56:56 +03:00
|
|
|
static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
|
|
|
|
{
|
|
|
|
uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
|
|
|
|
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
|
|
|
|
|
|
|
|
if (!vmc->disallow_affinity_adjustment) {
|
|
|
|
/* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
|
|
|
|
* GIC's target-list limitations. 32-bit KVM hosts currently
|
|
|
|
* always create clusters of 4 CPUs, but that is expected to
|
|
|
|
* change when they gain support for gicv3. When KVM is enabled
|
|
|
|
* it will override the changes we make here, therefore our
|
|
|
|
* purposes are to make TCG consistent (with 64-bit KVM hosts)
|
|
|
|
* and to improve SGI efficiency.
|
|
|
|
*/
|
|
|
|
if (vms->gic_version == 3) {
|
|
|
|
clustersz = GICV3_TARGETLIST_BITS;
|
|
|
|
} else {
|
|
|
|
clustersz = GIC_TARGETLIST_BITS;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return arm_cpu_mp_affinity(idx, clustersz);
|
|
|
|
}
|
|
|
|
|
2014-05-07 18:42:57 +04:00
|
|
|
static void machvirt_init(MachineState *machine)
|
2013-11-22 21:17:14 +04:00
|
|
|
{
|
2014-12-16 02:09:49 +03:00
|
|
|
VirtMachineState *vms = VIRT_MACHINE(machine);
|
2016-07-14 18:51:37 +03:00
|
|
|
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
|
2017-05-03 15:56:57 +03:00
|
|
|
MachineClass *mc = MACHINE_GET_CLASS(machine);
|
|
|
|
const CPUArchIdList *possible_cpus;
|
2013-11-22 21:17:14 +04:00
|
|
|
qemu_irq pic[NUM_IRQS];
|
|
|
|
MemoryRegion *sysmem = get_system_memory();
|
2016-01-21 17:15:07 +03:00
|
|
|
MemoryRegion *secure_sysmem = NULL;
|
2016-02-11 14:17:32 +03:00
|
|
|
int n, virt_max_cpus;
|
2013-11-22 21:17:14 +04:00
|
|
|
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
2016-03-04 14:30:18 +03:00
|
|
|
bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2015-09-24 03:29:37 +03:00
|
|
|
/* We can probe only here because during property set
|
|
|
|
* KVM is not available yet
|
|
|
|
*/
|
2017-01-09 14:40:22 +03:00
|
|
|
if (!vms->gic_version) {
|
2016-06-06 18:59:29 +03:00
|
|
|
if (!kvm_enabled()) {
|
|
|
|
error_report("gic-version=host requires KVM");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
vms->gic_version = kvm_arm_vgic_probe();
|
|
|
|
if (!vms->gic_version) {
|
2015-11-10 16:37:33 +03:00
|
|
|
error_report("Unable to determine GIC version supported by host");
|
2015-09-24 03:29:37 +03:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-09-13 19:04:57 +03:00
|
|
|
if (!cpu_type_valid(machine->cpu_type)) {
|
|
|
|
error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
|
2013-11-22 21:17:14 +04:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2016-03-04 14:30:18 +03:00
|
|
|
/* If we have an EL3 boot ROM then the assumption is that it will
|
|
|
|
* implement PSCI itself, so disable QEMU's internal implementation
|
|
|
|
* so it doesn't get in the way. Instead of starting secondary
|
|
|
|
* CPUs in PSCI powerdown state we will start them all running and
|
|
|
|
* let the boot ROM sort them out.
|
2017-01-20 14:15:11 +03:00
|
|
|
* The usual case is that we do use QEMU's PSCI implementation;
|
|
|
|
* if the guest has EL2 then we will use SMC as the conduit,
|
|
|
|
* and otherwise we will use HVC (for backwards compatibility and
|
|
|
|
* because if we're using KVM then we must use HVC).
|
2016-03-04 14:30:18 +03:00
|
|
|
*/
|
2017-01-20 14:15:10 +03:00
|
|
|
if (vms->secure && firmware_loaded) {
|
|
|
|
vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
|
2017-01-20 14:15:11 +03:00
|
|
|
} else if (vms->virt) {
|
|
|
|
vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
|
2017-01-20 14:15:10 +03:00
|
|
|
} else {
|
|
|
|
vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
|
|
|
|
}
|
2016-03-04 14:30:18 +03:00
|
|
|
|
2015-10-27 15:00:50 +03:00
|
|
|
/* The maximum number of CPUs depends on the GIC version, or on how
|
|
|
|
* many redistributors we can fit into the memory map.
|
|
|
|
*/
|
2017-01-09 14:40:22 +03:00
|
|
|
if (vms->gic_version == 3) {
|
2017-01-09 14:40:21 +03:00
|
|
|
virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000;
|
2015-10-27 15:00:50 +03:00
|
|
|
} else {
|
2016-02-11 14:17:32 +03:00
|
|
|
virt_max_cpus = GIC_NCPU;
|
2015-10-27 15:00:50 +03:00
|
|
|
}
|
|
|
|
|
2016-02-11 14:17:32 +03:00
|
|
|
if (max_cpus > virt_max_cpus) {
|
2015-10-27 15:00:50 +03:00
|
|
|
error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
|
|
|
|
"supported by machine 'mach-virt' (%d)",
|
2016-02-11 14:17:32 +03:00
|
|
|
max_cpus, virt_max_cpus);
|
2015-10-27 15:00:50 +03:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
vms->smp_cpus = smp_cpus;
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
if (machine->ram_size > vms->memmap[VIRT_MEM].size) {
|
2016-03-04 14:30:16 +03:00
|
|
|
error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB);
|
2013-11-22 21:17:14 +04:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2017-01-20 14:15:11 +03:00
|
|
|
if (vms->virt && kvm_enabled()) {
|
|
|
|
error_report("mach-virt: KVM does not support providing "
|
|
|
|
"Virtualization extensions to the guest CPU");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2016-01-21 17:15:07 +03:00
|
|
|
if (vms->secure) {
|
|
|
|
if (kvm_enabled()) {
|
|
|
|
error_report("mach-virt: KVM does not support Security extensions");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The Secure view of the world is the same as the NonSecure,
|
|
|
|
* but with a few extra devices. Create it as a container region
|
|
|
|
* containing the system memory at low priority; any secure-only
|
|
|
|
* devices go in at higher priority and take precedence.
|
|
|
|
*/
|
|
|
|
secure_sysmem = g_new(MemoryRegion, 1);
|
|
|
|
memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
|
|
|
|
UINT64_MAX);
|
|
|
|
memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
create_fdt(vms);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-05-03 15:56:57 +03:00
|
|
|
possible_cpus = mc->possible_cpu_arch_ids(machine);
|
|
|
|
for (n = 0; n < possible_cpus->len; n++) {
|
|
|
|
Object *cpuobj;
|
2017-05-03 15:56:58 +03:00
|
|
|
CPUState *cs;
|
2017-05-03 15:56:56 +03:00
|
|
|
|
2017-05-03 15:56:57 +03:00
|
|
|
if (n >= smp_cpus) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-09-13 19:04:57 +03:00
|
|
|
cpuobj = object_new(machine->cpu_type);
|
2017-05-03 15:56:57 +03:00
|
|
|
object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
|
2017-05-03 15:56:56 +03:00
|
|
|
"mp-affinity", NULL);
|
2015-02-13 08:46:08 +03:00
|
|
|
|
2017-05-03 15:56:58 +03:00
|
|
|
cs = CPU(cpuobj);
|
|
|
|
cs->cpu_index = n;
|
|
|
|
|
2017-05-30 19:23:56 +03:00
|
|
|
numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
|
|
|
|
&error_fatal);
|
2017-05-10 14:29:48 +03:00
|
|
|
|
2014-12-16 02:09:49 +03:00
|
|
|
if (!vms->secure) {
|
|
|
|
object_property_set_bool(cpuobj, false, "has_el3", NULL);
|
|
|
|
}
|
|
|
|
|
2017-01-20 14:15:11 +03:00
|
|
|
if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
|
2017-01-20 14:15:10 +03:00
|
|
|
object_property_set_bool(cpuobj, false, "has_el2", NULL);
|
|
|
|
}
|
|
|
|
|
2017-01-20 14:15:10 +03:00
|
|
|
if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
|
|
|
|
object_property_set_int(cpuobj, vms->psci_conduit,
|
2016-03-04 14:30:18 +03:00
|
|
|
"psci-conduit", NULL);
|
2014-10-24 15:19:13 +04:00
|
|
|
|
2016-03-04 14:30:18 +03:00
|
|
|
/* Secondary CPUs start in PSCI powered-down state */
|
|
|
|
if (n > 0) {
|
|
|
|
object_property_set_bool(cpuobj, true,
|
|
|
|
"start-powered-off", NULL);
|
|
|
|
}
|
2013-11-22 21:17:14 +04:00
|
|
|
}
|
2014-03-17 20:31:46 +04:00
|
|
|
|
2016-10-28 16:12:31 +03:00
|
|
|
if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
|
|
|
|
object_property_set_bool(cpuobj, false, "pmu", NULL);
|
|
|
|
}
|
|
|
|
|
2014-03-17 20:31:46 +04:00
|
|
|
if (object_property_find(cpuobj, "reset-cbar", NULL)) {
|
2017-01-09 14:40:21 +03:00
|
|
|
object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base,
|
2014-03-17 20:31:46 +04:00
|
|
|
"reset-cbar", &error_abort);
|
|
|
|
}
|
|
|
|
|
2016-01-21 17:15:07 +03:00
|
|
|
object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
|
|
|
|
&error_abort);
|
2016-01-21 17:15:07 +03:00
|
|
|
if (vms->secure) {
|
|
|
|
object_property_set_link(cpuobj, OBJECT(secure_sysmem),
|
|
|
|
"secure-memory", &error_abort);
|
|
|
|
}
|
2016-01-21 17:15:07 +03:00
|
|
|
|
2013-11-22 21:17:14 +04:00
|
|
|
object_property_set_bool(cpuobj, true, "realized", NULL);
|
2017-02-28 15:08:15 +03:00
|
|
|
object_unref(cpuobj);
|
2013-11-22 21:17:14 +04:00
|
|
|
}
|
2017-01-09 14:40:22 +03:00
|
|
|
fdt_add_timer_nodes(vms);
|
2017-01-09 14:40:21 +03:00
|
|
|
fdt_add_cpu_nodes(vms);
|
|
|
|
fdt_add_psci_node(vms);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2015-04-04 15:24:38 +03:00
|
|
|
memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
|
|
|
|
machine->ram_size);
|
2017-01-09 14:40:21 +03:00
|
|
|
memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
|
2014-09-12 17:06:48 +04:00
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
create_gic(vms, pic);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
fdt_add_pmu_nodes(vms);
|
2016-06-14 17:59:12 +03:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
create_uart(vms, pic, VIRT_UART, sysmem, serial_hds[0]);
|
2016-01-21 17:15:07 +03:00
|
|
|
|
|
|
|
if (vms->secure) {
|
2017-01-09 14:40:21 +03:00
|
|
|
create_secure_ram(vms, secure_sysmem);
|
|
|
|
create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]);
|
2016-01-21 17:15:07 +03:00
|
|
|
}
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
create_rtc(vms, pic);
|
2014-06-29 21:38:39 +04:00
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
create_pcie(vms, pic);
|
2015-02-13 08:46:08 +03:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
create_gpio(vms, pic);
|
2015-12-17 16:37:13 +03:00
|
|
|
|
2013-11-22 21:17:14 +04:00
|
|
|
/* Create mmio transports, so the user can create virtio backends
|
|
|
|
* (which will be automatically plugged in to the transports). If
|
|
|
|
* no backend is created the transport will just sit harmlessly idle.
|
|
|
|
*/
|
2017-01-09 14:40:21 +03:00
|
|
|
create_virtio_devices(vms, pic);
|
2013-11-22 21:17:14 +04:00
|
|
|
|
2017-01-09 14:40:23 +03:00
|
|
|
vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
|
|
|
|
rom_set_fw(vms->fw_cfg);
|
2015-05-29 13:28:59 +03:00
|
|
|
|
2017-01-09 14:40:22 +03:00
|
|
|
vms->machine_done.notify = virt_machine_done;
|
|
|
|
qemu_add_machine_init_done_notifier(&vms->machine_done);
|
arm: add fw_cfg to "virt" board
fw_cfg already supports exposure over MMIO (used in ppc/mac_newworld.c,
ppc/mac_oldworld.c, sparc/sun4m.c); we can easily add it to the "virt"
board.
Because MMIO access is slow on ARM KVM, we enable the guest, with
fw_cfg_init_mem_wide(), to transfer up to 8 bytes with a single access.
This has been measured to speed up transfers up to 7.5-fold, relative to
single byte data access, on both ARM KVM and x86_64 TCG.
The MMIO register block of fw_cfg is advertized in the device tree. As
base address we pick 0x09020000, which conforms to the comment preceding
"a15memmap": it falls in the miscellaneous device I/O range 128MB..256MB,
and it is aligned at 64KB. The DTB properties follow the documentation in
the Linux source file "Documentation/devicetree/bindings/arm/fw-cfg.txt".
fw_cfg automatically exports a number of files to the guest; for example,
"bootorder" (see fw_cfg_machine_reset()).
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 1419250305-31062-9-git-send-email-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22 15:11:42 +03:00
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
vms->bootinfo.ram_size = machine->ram_size;
|
|
|
|
vms->bootinfo.kernel_filename = machine->kernel_filename;
|
|
|
|
vms->bootinfo.kernel_cmdline = machine->kernel_cmdline;
|
|
|
|
vms->bootinfo.initrd_filename = machine->initrd_filename;
|
|
|
|
vms->bootinfo.nb_cpus = smp_cpus;
|
|
|
|
vms->bootinfo.board_id = -1;
|
|
|
|
vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
|
|
|
|
vms->bootinfo.get_dtb = machvirt_dtb;
|
|
|
|
vms->bootinfo.firmware_loaded = firmware_loaded;
|
|
|
|
arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo);
|
2015-06-02 14:29:13 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* arm_load_kernel machine init done notifier registration must
|
|
|
|
* happen before the platform_bus_create call. In this latter,
|
|
|
|
* another notifier is registered which adds platform bus nodes.
|
|
|
|
* Notifiers are executed in registration reverse order.
|
|
|
|
*/
|
2017-01-09 14:40:21 +03:00
|
|
|
create_platform_bus(vms, pic);
|
2013-11-22 21:17:14 +04:00
|
|
|
}
|
|
|
|
|
2014-12-16 02:09:44 +03:00
|
|
|
static bool virt_get_secure(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
|
|
|
|
|
|
|
return vms->secure;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void virt_set_secure(Object *obj, bool value, Error **errp)
|
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
|
|
|
|
|
|
|
vms->secure = value;
|
|
|
|
}
|
|
|
|
|
2017-01-20 14:15:11 +03:00
|
|
|
static bool virt_get_virt(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
|
|
|
|
|
|
|
return vms->virt;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void virt_set_virt(Object *obj, bool value, Error **errp)
|
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
|
|
|
|
|
|
|
vms->virt = value;
|
|
|
|
}
|
|
|
|
|
2015-09-07 12:39:29 +03:00
|
|
|
static bool virt_get_highmem(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
|
|
|
|
|
|
|
return vms->highmem;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void virt_set_highmem(Object *obj, bool value, Error **errp)
|
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
|
|
|
|
|
|
|
vms->highmem = value;
|
|
|
|
}
|
|
|
|
|
2017-02-28 15:08:16 +03:00
|
|
|
static bool virt_get_its(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
|
|
|
|
|
|
|
return vms->its;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void virt_set_its(Object *obj, bool value, Error **errp)
|
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
|
|
|
|
|
|
|
vms->its = value;
|
|
|
|
}
|
|
|
|
|
2015-09-24 03:29:37 +03:00
|
|
|
static char *virt_get_gic_version(Object *obj, Error **errp)
|
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
|
|
|
const char *val = vms->gic_version == 3 ? "3" : "2";
|
|
|
|
|
|
|
|
return g_strdup(val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
|
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
|
|
|
|
|
|
|
if (!strcmp(value, "3")) {
|
|
|
|
vms->gic_version = 3;
|
|
|
|
} else if (!strcmp(value, "2")) {
|
|
|
|
vms->gic_version = 2;
|
|
|
|
} else if (!strcmp(value, "host")) {
|
|
|
|
vms->gic_version = 0; /* Will probe later */
|
|
|
|
} else {
|
2015-12-17 19:35:15 +03:00
|
|
|
error_setg(errp, "Invalid gic-version value");
|
|
|
|
error_append_hint(errp, "Valid values are 3, 2, host.\n");
|
2015-09-24 03:29:37 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-05-10 14:29:45 +03:00
|
|
|
static CpuInstanceProperties
|
|
|
|
virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_GET_CLASS(ms);
|
|
|
|
const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
|
|
|
|
|
|
|
|
assert(cpu_index < possible_cpus->len);
|
|
|
|
return possible_cpus->cpus[cpu_index].props;
|
|
|
|
}
|
|
|
|
|
2017-06-01 13:53:28 +03:00
|
|
|
static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
|
|
|
|
{
|
|
|
|
return idx % nb_numa_nodes;
|
|
|
|
}
|
|
|
|
|
2017-05-03 15:56:57 +03:00
|
|
|
static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
|
|
|
|
{
|
|
|
|
int n;
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(ms);
|
|
|
|
|
|
|
|
if (ms->possible_cpus) {
|
|
|
|
assert(ms->possible_cpus->len == max_cpus);
|
|
|
|
return ms->possible_cpus;
|
|
|
|
}
|
|
|
|
|
|
|
|
ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
|
|
|
|
sizeof(CPUArchId) * max_cpus);
|
|
|
|
ms->possible_cpus->len = max_cpus;
|
|
|
|
for (n = 0; n < ms->possible_cpus->len; n++) {
|
|
|
|
ms->possible_cpus->cpus[n].arch_id =
|
|
|
|
virt_cpu_mp_affinity(vms, n);
|
|
|
|
ms->possible_cpus->cpus[n].props.has_thread_id = true;
|
|
|
|
ms->possible_cpus->cpus[n].props.thread_id = n;
|
|
|
|
}
|
|
|
|
return ms->possible_cpus;
|
|
|
|
}
|
|
|
|
|
2016-03-16 20:05:59 +03:00
|
|
|
static void virt_machine_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
2016-03-16 20:05:59 +03:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->init = machvirt_init;
|
|
|
|
/* Start max_cpus at the maximum QEMU supports. We'll further restrict
|
|
|
|
* it later in machvirt_init, where we have more information about the
|
|
|
|
* configuration of the particular instance.
|
|
|
|
*/
|
2016-10-19 15:05:40 +03:00
|
|
|
mc->max_cpus = 255;
|
2016-03-16 20:05:59 +03:00
|
|
|
mc->has_dynamic_sysbus = true;
|
|
|
|
mc->block_default_type = IF_VIRTIO;
|
|
|
|
mc->no_cdrom = 1;
|
|
|
|
mc->pci_allow_0_address = true;
|
2016-10-24 18:26:50 +03:00
|
|
|
/* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
|
|
|
|
mc->minimum_page_bits = 12;
|
2017-05-03 15:56:57 +03:00
|
|
|
mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
|
2017-05-10 14:29:45 +03:00
|
|
|
mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
|
2017-09-13 19:04:57 +03:00
|
|
|
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
|
2017-06-01 13:53:28 +03:00
|
|
|
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
|
2016-03-16 20:05:59 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo virt_machine_info = {
|
|
|
|
.name = TYPE_VIRT_MACHINE,
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.abstract = true,
|
|
|
|
.instance_size = sizeof(VirtMachineState),
|
|
|
|
.class_size = sizeof(VirtMachineClass),
|
|
|
|
.class_init = virt_machine_class_init,
|
|
|
|
};
|
|
|
|
|
2016-06-14 17:59:12 +03:00
|
|
|
static void machvirt_machine_init(void)
|
|
|
|
{
|
|
|
|
type_register_static(&virt_machine_info);
|
|
|
|
}
|
|
|
|
type_init(machvirt_machine_init);
|
|
|
|
|
2017-11-24 12:43:46 +03:00
|
|
|
static void virt_2_11_instance_init(Object *obj)
|
2014-12-16 02:09:44 +03:00
|
|
|
{
|
|
|
|
VirtMachineState *vms = VIRT_MACHINE(obj);
|
2017-02-28 15:08:16 +03:00
|
|
|
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
|
2014-12-16 02:09:44 +03:00
|
|
|
|
2015-09-08 19:38:44 +03:00
|
|
|
/* EL3 is disabled by default on virt: this makes us consistent
|
|
|
|
* between KVM and TCG for this board, and it also allows us to
|
|
|
|
* boot UEFI blobs which assume no TrustZone support.
|
|
|
|
*/
|
|
|
|
vms->secure = false;
|
2014-12-16 02:09:44 +03:00
|
|
|
object_property_add_bool(obj, "secure", virt_get_secure,
|
|
|
|
virt_set_secure, NULL);
|
|
|
|
object_property_set_description(obj, "secure",
|
|
|
|
"Set on/off to enable/disable the ARM "
|
|
|
|
"Security Extensions (TrustZone)",
|
|
|
|
NULL);
|
2015-09-07 12:39:29 +03:00
|
|
|
|
2017-01-20 14:15:11 +03:00
|
|
|
/* EL2 is also disabled by default, for similar reasons */
|
|
|
|
vms->virt = false;
|
|
|
|
object_property_add_bool(obj, "virtualization", virt_get_virt,
|
|
|
|
virt_set_virt, NULL);
|
|
|
|
object_property_set_description(obj, "virtualization",
|
|
|
|
"Set on/off to enable/disable emulating a "
|
|
|
|
"guest CPU which implements the ARM "
|
|
|
|
"Virtualization Extensions",
|
|
|
|
NULL);
|
|
|
|
|
2015-09-07 12:39:29 +03:00
|
|
|
/* High memory is enabled by default */
|
|
|
|
vms->highmem = true;
|
|
|
|
object_property_add_bool(obj, "highmem", virt_get_highmem,
|
|
|
|
virt_set_highmem, NULL);
|
|
|
|
object_property_set_description(obj, "highmem",
|
|
|
|
"Set on/off to enable/disable using "
|
|
|
|
"physical address space above 32 bits",
|
|
|
|
NULL);
|
2015-09-24 03:29:37 +03:00
|
|
|
/* Default GIC type is v2 */
|
|
|
|
vms->gic_version = 2;
|
|
|
|
object_property_add_str(obj, "gic-version", virt_get_gic_version,
|
|
|
|
virt_set_gic_version, NULL);
|
|
|
|
object_property_set_description(obj, "gic-version",
|
|
|
|
"Set GIC version. "
|
|
|
|
"Valid values are 2, 3 and host", NULL);
|
2017-01-09 14:40:21 +03:00
|
|
|
|
2017-02-28 15:08:16 +03:00
|
|
|
if (vmc->no_its) {
|
|
|
|
vms->its = false;
|
|
|
|
} else {
|
|
|
|
/* Default allows ITS instantiation */
|
|
|
|
vms->its = true;
|
|
|
|
object_property_add_bool(obj, "its", virt_get_its,
|
|
|
|
virt_set_its, NULL);
|
|
|
|
object_property_set_description(obj, "its",
|
|
|
|
"Set on/off to enable/disable "
|
|
|
|
"ITS instantiation",
|
|
|
|
NULL);
|
|
|
|
}
|
|
|
|
|
2017-01-09 14:40:21 +03:00
|
|
|
vms->memmap = a15memmap;
|
|
|
|
vms->irqmap = a15irqmap;
|
2014-12-16 02:09:44 +03:00
|
|
|
}
|
|
|
|
|
2017-11-24 12:43:46 +03:00
|
|
|
static void virt_machine_2_11_options(MachineClass *mc)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
DEFINE_VIRT_MACHINE_AS_LATEST(2, 11)
|
|
|
|
|
|
|
|
#define VIRT_COMPAT_2_10 \
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HW_COMPAT_2_10
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static void virt_2_10_instance_init(Object *obj)
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{
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virt_2_11_instance_init(obj);
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}
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2017-08-07 14:49:41 +03:00
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static void virt_machine_2_10_options(MachineClass *mc)
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{
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2017-11-24 12:43:46 +03:00
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virt_machine_2_11_options(mc);
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SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10);
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2017-08-07 14:49:41 +03:00
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}
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2017-11-24 12:43:46 +03:00
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DEFINE_VIRT_MACHINE(2, 10)
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2017-08-07 14:49:41 +03:00
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#define VIRT_COMPAT_2_9 \
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HW_COMPAT_2_9
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static void virt_2_9_instance_init(Object *obj)
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{
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virt_2_10_instance_init(obj);
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}
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2016-12-27 17:59:26 +03:00
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static void virt_machine_2_9_options(MachineClass *mc)
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{
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2017-08-07 14:49:41 +03:00
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virt_machine_2_10_options(mc);
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SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9);
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2016-12-27 17:59:26 +03:00
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}
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2017-08-07 14:49:41 +03:00
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DEFINE_VIRT_MACHINE(2, 9)
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2016-12-27 17:59:26 +03:00
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#define VIRT_COMPAT_2_8 \
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HW_COMPAT_2_8
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static void virt_2_8_instance_init(Object *obj)
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{
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virt_2_9_instance_init(obj);
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}
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2016-10-04 15:28:08 +03:00
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static void virt_machine_2_8_options(MachineClass *mc)
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{
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2017-01-09 14:40:21 +03:00
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VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
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2016-12-27 17:59:26 +03:00
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virt_machine_2_9_options(mc);
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SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8);
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2017-01-09 14:40:21 +03:00
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/* For 2.8 and earlier we falsely claimed in the DT that
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* our timers were edge-triggered, not level-triggered.
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*/
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vmc->claim_edge_triggered_timers = true;
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2016-10-04 15:28:08 +03:00
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}
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2016-12-27 17:59:26 +03:00
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DEFINE_VIRT_MACHINE(2, 8)
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2016-10-04 15:28:08 +03:00
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#define VIRT_COMPAT_2_7 \
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HW_COMPAT_2_7
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static void virt_2_7_instance_init(Object *obj)
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{
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virt_2_8_instance_init(obj);
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}
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2016-06-14 17:59:13 +03:00
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static void virt_machine_2_7_options(MachineClass *mc)
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{
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2016-10-17 21:22:17 +03:00
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VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
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2016-10-04 15:28:08 +03:00
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virt_machine_2_8_options(mc);
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SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7);
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2016-10-17 21:22:17 +03:00
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/* ITS was introduced with 2.8 */
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vmc->no_its = true;
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2016-10-24 18:26:50 +03:00
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/* Stick with 1K pages for migration compatibility */
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mc->minimum_page_bits = 0;
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2016-06-14 17:59:13 +03:00
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}
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2016-10-04 15:28:08 +03:00
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DEFINE_VIRT_MACHINE(2, 7)
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2016-06-14 17:59:13 +03:00
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#define VIRT_COMPAT_2_6 \
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HW_COMPAT_2_6
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static void virt_2_6_instance_init(Object *obj)
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{
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virt_2_7_instance_init(obj);
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}
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2016-06-14 17:59:12 +03:00
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static void virt_machine_2_6_options(MachineClass *mc)
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2014-12-16 02:09:43 +03:00
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{
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2016-07-14 18:51:37 +03:00
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VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
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2016-06-14 17:59:13 +03:00
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virt_machine_2_7_options(mc);
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SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6);
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2016-07-14 18:51:37 +03:00
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vmc->disallow_affinity_adjustment = true;
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2016-10-28 16:12:31 +03:00
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/* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
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vmc->no_pmu = true;
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2014-12-16 02:09:43 +03:00
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}
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2016-06-14 17:59:13 +03:00
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DEFINE_VIRT_MACHINE(2, 6)
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