2020-09-11 08:20:50 +03:00
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/*
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* Nuvoton NPCM7xx Timer Controller
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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2021-01-08 22:09:41 +03:00
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#include "hw/qdev-clock.h"
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2020-10-24 00:06:34 +03:00
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#include "hw/qdev-properties.h"
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2020-09-11 08:20:50 +03:00
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#include "hw/timer/npcm7xx_timer.h"
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#include "migration/vmstate.h"
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#include "qemu/bitops.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/timer.h"
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#include "qemu/units.h"
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#include "trace.h"
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/* 32-bit register indices. */
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enum NPCM7xxTimerRegisters {
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NPCM7XX_TIMER_TCSR0,
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NPCM7XX_TIMER_TCSR1,
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NPCM7XX_TIMER_TICR0,
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NPCM7XX_TIMER_TICR1,
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NPCM7XX_TIMER_TDR0,
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NPCM7XX_TIMER_TDR1,
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NPCM7XX_TIMER_TISR,
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NPCM7XX_TIMER_WTCR,
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NPCM7XX_TIMER_TCSR2,
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NPCM7XX_TIMER_TCSR3,
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NPCM7XX_TIMER_TICR2,
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NPCM7XX_TIMER_TICR3,
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NPCM7XX_TIMER_TDR2,
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NPCM7XX_TIMER_TDR3,
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NPCM7XX_TIMER_TCSR4 = 0x0040 / sizeof(uint32_t),
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NPCM7XX_TIMER_TICR4 = 0x0048 / sizeof(uint32_t),
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NPCM7XX_TIMER_TDR4 = 0x0050 / sizeof(uint32_t),
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NPCM7XX_TIMER_REGS_END,
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};
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/* Register field definitions. */
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#define NPCM7XX_TCSR_CEN BIT(30)
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#define NPCM7XX_TCSR_IE BIT(29)
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#define NPCM7XX_TCSR_PERIODIC BIT(27)
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#define NPCM7XX_TCSR_CRST BIT(26)
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#define NPCM7XX_TCSR_CACT BIT(25)
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#define NPCM7XX_TCSR_RSVD 0x01ffff00
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#define NPCM7XX_TCSR_PRESCALE_START 0
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#define NPCM7XX_TCSR_PRESCALE_LEN 8
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2020-10-24 00:06:34 +03:00
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#define NPCM7XX_WTCR_WTCLK(rv) extract32(rv, 10, 2)
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#define NPCM7XX_WTCR_FREEZE_EN BIT(9)
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#define NPCM7XX_WTCR_WTE BIT(7)
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#define NPCM7XX_WTCR_WTIE BIT(6)
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#define NPCM7XX_WTCR_WTIS(rv) extract32(rv, 4, 2)
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#define NPCM7XX_WTCR_WTIF BIT(3)
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#define NPCM7XX_WTCR_WTRF BIT(2)
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#define NPCM7XX_WTCR_WTRE BIT(1)
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#define NPCM7XX_WTCR_WTR BIT(0)
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/*
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* The number of clock cycles between interrupt and reset in watchdog, used
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* by the software to handle the interrupt before system is reset.
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*/
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#define NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES 1024
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/* Start or resume the timer. */
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static void npcm7xx_timer_start(NPCM7xxBaseTimer *t)
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{
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int64_t now;
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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t->expires_ns = now + t->remaining_ns;
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timer_mod(&t->qtimer, t->expires_ns);
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}
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/* Stop counting. Record the time remaining so we can continue later. */
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static void npcm7xx_timer_pause(NPCM7xxBaseTimer *t)
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{
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int64_t now;
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timer_del(&t->qtimer);
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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t->remaining_ns = t->expires_ns - now;
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}
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/* Delete the timer and reset it to default state. */
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static void npcm7xx_timer_clear(NPCM7xxBaseTimer *t)
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{
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timer_del(&t->qtimer);
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t->expires_ns = 0;
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t->remaining_ns = 0;
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}
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2020-09-11 08:20:50 +03:00
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/*
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* Returns the index of timer in the tc->timer array. This can be used to
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* locate the registers that belong to this timer.
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*/
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static int npcm7xx_timer_index(NPCM7xxTimerCtrlState *tc, NPCM7xxTimer *timer)
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{
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int index = timer - tc->timer;
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g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL);
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return index;
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}
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/* Return the value by which to divide the reference clock rate. */
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static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
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{
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return extract32(tcsr, NPCM7XX_TCSR_PRESCALE_START,
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NPCM7XX_TCSR_PRESCALE_LEN) + 1;
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}
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/* Convert a timer cycle count to a time interval in nanoseconds. */
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static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
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{
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2021-01-08 22:09:41 +03:00
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int64_t ticks = count;
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2020-09-11 08:20:50 +03:00
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2021-01-08 22:09:41 +03:00
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ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
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2020-09-11 08:20:50 +03:00
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2021-01-08 22:09:41 +03:00
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return clock_ticks_to_ns(t->ctrl->clock, ticks);
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2020-09-11 08:20:50 +03:00
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}
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/* Convert a time interval in nanoseconds to a timer cycle count. */
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static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
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{
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2023-09-22 21:14:11 +03:00
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if (ns < 0) {
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return 0;
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}
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2021-02-19 17:45:37 +03:00
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return clock_ns_to_ticks(t->ctrl->clock, ns) /
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npcm7xx_tcsr_prescaler(t->tcsr);
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2020-09-11 08:20:50 +03:00
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}
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2020-10-24 00:06:34 +03:00
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static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
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{
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switch (NPCM7XX_WTCR_WTCLK(t->wtcr)) {
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case 0:
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return 1;
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case 1:
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return 256;
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case 2:
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return 2048;
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case 3:
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return 65536;
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default:
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g_assert_not_reached();
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}
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}
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static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
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int64_t cycles)
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{
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2021-01-08 22:09:41 +03:00
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int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
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int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
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2020-10-24 00:06:34 +03:00
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/*
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* The reset function always clears the current timer. The caller of the
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* this needs to decide whether to start the watchdog timer based on
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* specific flag in WTCR.
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*/
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npcm7xx_timer_clear(&t->base_timer);
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t->base_timer.remaining_ns = ns;
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}
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static void npcm7xx_watchdog_timer_reset(NPCM7xxWatchdogTimer *t)
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{
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int64_t cycles = 1;
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uint32_t s = NPCM7XX_WTCR_WTIS(t->wtcr);
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g_assert(s <= 3);
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cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT;
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cycles <<= 2 * s;
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npcm7xx_watchdog_timer_reset_cycles(t, cycles);
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}
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2020-09-11 08:20:50 +03:00
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/*
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* Raise the interrupt line if there's a pending interrupt and interrupts are
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* enabled for this timer. If not, lower it.
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*/
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static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
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{
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NPCM7xxTimerCtrlState *tc = t->ctrl;
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int index = npcm7xx_timer_index(tc, t);
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bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index));
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qemu_set_irq(t->irq, pending);
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trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
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}
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/*
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* Called when the counter reaches zero. Sets the interrupt flag, and either
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* restarts or disables the timer.
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*/
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static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
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{
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NPCM7xxTimerCtrlState *tc = t->ctrl;
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int index = npcm7xx_timer_index(tc, t);
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tc->tisr |= BIT(index);
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if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
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2020-10-24 00:06:34 +03:00
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t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
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2020-09-11 08:20:50 +03:00
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if (t->tcsr & NPCM7XX_TCSR_CEN) {
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2020-10-24 00:06:34 +03:00
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npcm7xx_timer_start(&t->base_timer);
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2020-09-11 08:20:50 +03:00
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}
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} else {
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t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
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}
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npcm7xx_timer_check_interrupt(t);
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}
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/*
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* Restart the timer from its initial value. If the timer was enabled and stays
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* enabled, adjust the QEMU timer according to the new count. If the timer is
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* transitioning from disabled to enabled, the caller is expected to start the
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* timer later.
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*/
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static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
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{
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2020-10-24 00:06:34 +03:00
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t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
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2020-09-11 08:20:50 +03:00
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if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
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2020-10-24 00:06:34 +03:00
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npcm7xx_timer_start(&t->base_timer);
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2020-09-11 08:20:50 +03:00
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}
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}
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/* Register read and write handlers */
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static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
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{
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if (t->tcsr & NPCM7XX_TCSR_CEN) {
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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2020-10-24 00:06:34 +03:00
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return npcm7xx_timer_ns_to_count(t, t->base_timer.expires_ns - now);
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2020-09-11 08:20:50 +03:00
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}
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2020-10-24 00:06:34 +03:00
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return npcm7xx_timer_ns_to_count(t, t->base_timer.remaining_ns);
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2020-09-11 08:20:50 +03:00
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}
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static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
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{
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uint32_t old_tcsr = t->tcsr;
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uint32_t tdr;
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if (new_tcsr & NPCM7XX_TCSR_RSVD) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits in 0x%08x ignored\n",
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__func__, new_tcsr);
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new_tcsr &= ~NPCM7XX_TCSR_RSVD;
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}
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if (new_tcsr & NPCM7XX_TCSR_CACT) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read-only bits in 0x%08x ignored\n",
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__func__, new_tcsr);
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new_tcsr &= ~NPCM7XX_TCSR_CACT;
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}
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if ((new_tcsr & NPCM7XX_TCSR_CRST) && (new_tcsr & NPCM7XX_TCSR_CEN)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: both CRST and CEN set; ignoring CEN.\n",
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__func__);
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new_tcsr &= ~NPCM7XX_TCSR_CEN;
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}
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/* Calculate the value of TDR before potentially changing the prescaler. */
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tdr = npcm7xx_timer_read_tdr(t);
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t->tcsr = (t->tcsr & NPCM7XX_TCSR_CACT) | new_tcsr;
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if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
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/* Recalculate time remaining based on the current TDR value. */
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2020-10-24 00:06:34 +03:00
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t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
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2020-09-11 08:20:50 +03:00
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if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
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2020-10-24 00:06:34 +03:00
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npcm7xx_timer_start(&t->base_timer);
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2020-09-11 08:20:50 +03:00
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}
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}
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if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_IE) {
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npcm7xx_timer_check_interrupt(t);
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}
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if (new_tcsr & NPCM7XX_TCSR_CRST) {
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npcm7xx_timer_restart(t, old_tcsr);
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t->tcsr &= ~NPCM7XX_TCSR_CRST;
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}
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if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
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if (new_tcsr & NPCM7XX_TCSR_CEN) {
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t->tcsr |= NPCM7XX_TCSR_CACT;
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2020-10-24 00:06:34 +03:00
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npcm7xx_timer_start(&t->base_timer);
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2020-09-11 08:20:50 +03:00
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} else {
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t->tcsr &= ~NPCM7XX_TCSR_CACT;
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2020-10-24 00:06:34 +03:00
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npcm7xx_timer_pause(&t->base_timer);
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if (t->base_timer.remaining_ns <= 0) {
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2020-10-24 00:06:33 +03:00
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npcm7xx_timer_reached_zero(t);
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}
|
2020-09-11 08:20:50 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void npcm7xx_timer_write_ticr(NPCM7xxTimer *t, uint32_t new_ticr)
|
|
|
|
{
|
|
|
|
t->ticr = new_ticr;
|
|
|
|
|
|
|
|
npcm7xx_timer_restart(t, t->tcsr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState *s, uint32_t value)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
s->tisr &= ~value;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->timer); i++) {
|
|
|
|
if (value & (1U << i)) {
|
|
|
|
npcm7xx_timer_check_interrupt(&s->timer[i]);
|
|
|
|
}
|
2020-10-24 00:06:34 +03:00
|
|
|
|
2020-09-11 08:20:50 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-24 00:06:34 +03:00
|
|
|
static void npcm7xx_timer_write_wtcr(NPCM7xxWatchdogTimer *t, uint32_t new_wtcr)
|
|
|
|
{
|
|
|
|
uint32_t old_wtcr = t->wtcr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* WTIF and WTRF are cleared by writing 1. Writing 0 makes these bits
|
|
|
|
* unchanged.
|
|
|
|
*/
|
|
|
|
if (new_wtcr & NPCM7XX_WTCR_WTIF) {
|
|
|
|
new_wtcr &= ~NPCM7XX_WTCR_WTIF;
|
|
|
|
} else if (old_wtcr & NPCM7XX_WTCR_WTIF) {
|
|
|
|
new_wtcr |= NPCM7XX_WTCR_WTIF;
|
|
|
|
}
|
|
|
|
if (new_wtcr & NPCM7XX_WTCR_WTRF) {
|
|
|
|
new_wtcr &= ~NPCM7XX_WTCR_WTRF;
|
|
|
|
} else if (old_wtcr & NPCM7XX_WTCR_WTRF) {
|
|
|
|
new_wtcr |= NPCM7XX_WTCR_WTRF;
|
|
|
|
}
|
|
|
|
|
|
|
|
t->wtcr = new_wtcr;
|
|
|
|
|
|
|
|
if (new_wtcr & NPCM7XX_WTCR_WTR) {
|
|
|
|
t->wtcr &= ~NPCM7XX_WTCR_WTR;
|
|
|
|
npcm7xx_watchdog_timer_reset(t);
|
|
|
|
if (new_wtcr & NPCM7XX_WTCR_WTE) {
|
|
|
|
npcm7xx_timer_start(&t->base_timer);
|
|
|
|
}
|
|
|
|
} else if ((old_wtcr ^ new_wtcr) & NPCM7XX_WTCR_WTE) {
|
|
|
|
if (new_wtcr & NPCM7XX_WTCR_WTE) {
|
|
|
|
npcm7xx_timer_start(&t->base_timer);
|
|
|
|
} else {
|
|
|
|
npcm7xx_timer_pause(&t->base_timer);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2020-09-11 08:20:50 +03:00
|
|
|
static hwaddr npcm7xx_tcsr_index(hwaddr reg)
|
|
|
|
{
|
|
|
|
switch (reg) {
|
|
|
|
case NPCM7XX_TIMER_TCSR0:
|
|
|
|
return 0;
|
|
|
|
case NPCM7XX_TIMER_TCSR1:
|
|
|
|
return 1;
|
|
|
|
case NPCM7XX_TIMER_TCSR2:
|
|
|
|
return 2;
|
|
|
|
case NPCM7XX_TIMER_TCSR3:
|
|
|
|
return 3;
|
|
|
|
case NPCM7XX_TIMER_TCSR4:
|
|
|
|
return 4;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static hwaddr npcm7xx_ticr_index(hwaddr reg)
|
|
|
|
{
|
|
|
|
switch (reg) {
|
|
|
|
case NPCM7XX_TIMER_TICR0:
|
|
|
|
return 0;
|
|
|
|
case NPCM7XX_TIMER_TICR1:
|
|
|
|
return 1;
|
|
|
|
case NPCM7XX_TIMER_TICR2:
|
|
|
|
return 2;
|
|
|
|
case NPCM7XX_TIMER_TICR3:
|
|
|
|
return 3;
|
|
|
|
case NPCM7XX_TIMER_TICR4:
|
|
|
|
return 4;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static hwaddr npcm7xx_tdr_index(hwaddr reg)
|
|
|
|
{
|
|
|
|
switch (reg) {
|
|
|
|
case NPCM7XX_TIMER_TDR0:
|
|
|
|
return 0;
|
|
|
|
case NPCM7XX_TIMER_TDR1:
|
|
|
|
return 1;
|
|
|
|
case NPCM7XX_TIMER_TDR2:
|
|
|
|
return 2;
|
|
|
|
case NPCM7XX_TIMER_TDR3:
|
|
|
|
return 3;
|
|
|
|
case NPCM7XX_TIMER_TDR4:
|
|
|
|
return 4;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size)
|
|
|
|
{
|
|
|
|
NPCM7xxTimerCtrlState *s = opaque;
|
|
|
|
uint64_t value = 0;
|
|
|
|
hwaddr reg;
|
|
|
|
|
|
|
|
reg = offset / sizeof(uint32_t);
|
|
|
|
switch (reg) {
|
|
|
|
case NPCM7XX_TIMER_TCSR0:
|
|
|
|
case NPCM7XX_TIMER_TCSR1:
|
|
|
|
case NPCM7XX_TIMER_TCSR2:
|
|
|
|
case NPCM7XX_TIMER_TCSR3:
|
|
|
|
case NPCM7XX_TIMER_TCSR4:
|
|
|
|
value = s->timer[npcm7xx_tcsr_index(reg)].tcsr;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case NPCM7XX_TIMER_TICR0:
|
|
|
|
case NPCM7XX_TIMER_TICR1:
|
|
|
|
case NPCM7XX_TIMER_TICR2:
|
|
|
|
case NPCM7XX_TIMER_TICR3:
|
|
|
|
case NPCM7XX_TIMER_TICR4:
|
|
|
|
value = s->timer[npcm7xx_ticr_index(reg)].ticr;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case NPCM7XX_TIMER_TDR0:
|
|
|
|
case NPCM7XX_TIMER_TDR1:
|
|
|
|
case NPCM7XX_TIMER_TDR2:
|
|
|
|
case NPCM7XX_TIMER_TDR3:
|
|
|
|
case NPCM7XX_TIMER_TDR4:
|
|
|
|
value = npcm7xx_timer_read_tdr(&s->timer[npcm7xx_tdr_index(reg)]);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case NPCM7XX_TIMER_TISR:
|
|
|
|
value = s->tisr;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case NPCM7XX_TIMER_WTCR:
|
2020-10-24 00:06:34 +03:00
|
|
|
value = s->watchdog_timer.wtcr;
|
2020-09-11 08:20:50 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: invalid offset 0x%04" HWADDR_PRIx "\n",
|
|
|
|
__func__, offset);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
trace_npcm7xx_timer_read(DEVICE(s)->canonical_path, offset, value);
|
|
|
|
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void npcm7xx_timer_write(void *opaque, hwaddr offset,
|
|
|
|
uint64_t v, unsigned size)
|
|
|
|
{
|
|
|
|
uint32_t reg = offset / sizeof(uint32_t);
|
|
|
|
NPCM7xxTimerCtrlState *s = opaque;
|
|
|
|
uint32_t value = v;
|
|
|
|
|
|
|
|
trace_npcm7xx_timer_write(DEVICE(s)->canonical_path, offset, value);
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
case NPCM7XX_TIMER_TCSR0:
|
|
|
|
case NPCM7XX_TIMER_TCSR1:
|
|
|
|
case NPCM7XX_TIMER_TCSR2:
|
|
|
|
case NPCM7XX_TIMER_TCSR3:
|
|
|
|
case NPCM7XX_TIMER_TCSR4:
|
|
|
|
npcm7xx_timer_write_tcsr(&s->timer[npcm7xx_tcsr_index(reg)], value);
|
|
|
|
return;
|
|
|
|
|
|
|
|
case NPCM7XX_TIMER_TICR0:
|
|
|
|
case NPCM7XX_TIMER_TICR1:
|
|
|
|
case NPCM7XX_TIMER_TICR2:
|
|
|
|
case NPCM7XX_TIMER_TICR3:
|
|
|
|
case NPCM7XX_TIMER_TICR4:
|
|
|
|
npcm7xx_timer_write_ticr(&s->timer[npcm7xx_ticr_index(reg)], value);
|
|
|
|
return;
|
|
|
|
|
|
|
|
case NPCM7XX_TIMER_TDR0:
|
|
|
|
case NPCM7XX_TIMER_TDR1:
|
|
|
|
case NPCM7XX_TIMER_TDR2:
|
|
|
|
case NPCM7XX_TIMER_TDR3:
|
|
|
|
case NPCM7XX_TIMER_TDR4:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
|
|
|
|
__func__, offset);
|
|
|
|
return;
|
|
|
|
|
|
|
|
case NPCM7XX_TIMER_TISR:
|
|
|
|
npcm7xx_timer_write_tisr(s, value);
|
|
|
|
return;
|
|
|
|
|
|
|
|
case NPCM7XX_TIMER_WTCR:
|
2020-10-24 00:06:34 +03:00
|
|
|
npcm7xx_timer_write_wtcr(&s->watchdog_timer, value);
|
2020-09-11 08:20:50 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: invalid offset 0x%04" HWADDR_PRIx "\n",
|
|
|
|
__func__, offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct MemoryRegionOps npcm7xx_timer_ops = {
|
|
|
|
.read = npcm7xx_timer_read,
|
|
|
|
.write = npcm7xx_timer_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
.unaligned = false,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Called when the QEMU timer expires. */
|
|
|
|
static void npcm7xx_timer_expired(void *opaque)
|
|
|
|
{
|
|
|
|
NPCM7xxTimer *t = opaque;
|
|
|
|
|
|
|
|
if (t->tcsr & NPCM7XX_TCSR_CEN) {
|
|
|
|
npcm7xx_timer_reached_zero(t);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
|
|
|
|
{
|
|
|
|
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
|
|
|
|
NPCM7xxTimer *t = &s->timer[i];
|
|
|
|
|
2020-10-24 00:06:34 +03:00
|
|
|
npcm7xx_timer_clear(&t->base_timer);
|
2020-09-11 08:20:50 +03:00
|
|
|
t->tcsr = 0x00000005;
|
|
|
|
t->ticr = 0x00000000;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->tisr = 0x00000000;
|
2020-10-24 00:06:34 +03:00
|
|
|
/*
|
|
|
|
* Set WTCLK to 1(default) and reset all flags except WTRF.
|
|
|
|
* WTRF is not reset during a core domain reset.
|
|
|
|
*/
|
|
|
|
s->watchdog_timer.wtcr = 0x00000400 | (s->watchdog_timer.wtcr &
|
|
|
|
NPCM7XX_WTCR_WTRF);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void npcm7xx_watchdog_timer_expired(void *opaque)
|
|
|
|
{
|
|
|
|
NPCM7xxWatchdogTimer *t = opaque;
|
|
|
|
|
|
|
|
if (t->wtcr & NPCM7XX_WTCR_WTE) {
|
|
|
|
if (t->wtcr & NPCM7XX_WTCR_WTIF) {
|
|
|
|
if (t->wtcr & NPCM7XX_WTCR_WTRE) {
|
|
|
|
t->wtcr |= NPCM7XX_WTCR_WTRF;
|
|
|
|
/* send reset signal to CLK module*/
|
|
|
|
qemu_irq_raise(t->reset_signal);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
t->wtcr |= NPCM7XX_WTCR_WTIF;
|
|
|
|
if (t->wtcr & NPCM7XX_WTCR_WTIE) {
|
|
|
|
/* send interrupt */
|
|
|
|
qemu_irq_raise(t->irq);
|
|
|
|
}
|
|
|
|
npcm7xx_watchdog_timer_reset_cycles(t,
|
|
|
|
NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES);
|
|
|
|
npcm7xx_timer_start(&t->base_timer);
|
|
|
|
}
|
|
|
|
}
|
2020-09-11 08:20:50 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void npcm7xx_timer_hold_reset(Object *obj)
|
|
|
|
{
|
|
|
|
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
|
|
|
|
qemu_irq_lower(s->timer[i].irq);
|
|
|
|
}
|
2020-10-24 00:06:34 +03:00
|
|
|
qemu_irq_lower(s->watchdog_timer.irq);
|
2020-09-11 08:20:50 +03:00
|
|
|
}
|
|
|
|
|
2021-01-08 22:09:41 +03:00
|
|
|
static void npcm7xx_timer_init(Object *obj)
|
2020-09-11 08:20:50 +03:00
|
|
|
{
|
2021-01-08 22:09:41 +03:00
|
|
|
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
|
|
|
|
DeviceState *dev = DEVICE(obj);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
2020-09-11 08:20:50 +03:00
|
|
|
int i;
|
2020-10-24 00:06:34 +03:00
|
|
|
NPCM7xxWatchdogTimer *w;
|
2020-09-11 08:20:50 +03:00
|
|
|
|
|
|
|
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
|
|
|
|
NPCM7xxTimer *t = &s->timer[i];
|
|
|
|
t->ctrl = s;
|
2020-10-24 00:06:34 +03:00
|
|
|
timer_init_ns(&t->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
|
|
|
|
npcm7xx_timer_expired, t);
|
2020-09-11 08:20:50 +03:00
|
|
|
sysbus_init_irq(sbd, &t->irq);
|
|
|
|
}
|
|
|
|
|
2020-10-24 00:06:34 +03:00
|
|
|
w = &s->watchdog_timer;
|
|
|
|
w->ctrl = s;
|
|
|
|
timer_init_ns(&w->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
|
|
|
|
npcm7xx_watchdog_timer_expired, w);
|
|
|
|
sysbus_init_irq(sbd, &w->irq);
|
|
|
|
|
2021-01-08 22:09:41 +03:00
|
|
|
memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
|
2020-09-11 08:20:50 +03:00
|
|
|
TYPE_NPCM7XX_TIMER, 4 * KiB);
|
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
2020-10-24 00:06:34 +03:00
|
|
|
qdev_init_gpio_out_named(dev, &w->reset_signal,
|
|
|
|
NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
|
2021-02-19 17:45:34 +03:00
|
|
|
s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL, 0);
|
2020-09-11 08:20:50 +03:00
|
|
|
}
|
|
|
|
|
2020-10-24 00:06:34 +03:00
|
|
|
static const VMStateDescription vmstate_npcm7xx_base_timer = {
|
|
|
|
.name = "npcm7xx-base-timer",
|
2020-09-11 08:20:50 +03:00
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
|
|
|
.fields = (VMStateField[]) {
|
2020-10-24 00:06:34 +03:00
|
|
|
VMSTATE_TIMER(qtimer, NPCM7xxBaseTimer),
|
|
|
|
VMSTATE_INT64(expires_ns, NPCM7xxBaseTimer),
|
|
|
|
VMSTATE_INT64(remaining_ns, NPCM7xxBaseTimer),
|
|
|
|
VMSTATE_END_OF_LIST(),
|
|
|
|
},
|
|
|
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};
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|
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static const VMStateDescription vmstate_npcm7xx_timer = {
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|
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.name = "npcm7xx-timer",
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|
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.version_id = 1,
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.minimum_version_id = 1,
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|
|
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.fields = (VMStateField[]) {
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|
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VMSTATE_STRUCT(base_timer, NPCM7xxTimer,
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|
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0, vmstate_npcm7xx_base_timer,
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|
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|
NPCM7xxBaseTimer),
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2020-09-11 08:20:50 +03:00
|
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|
VMSTATE_UINT32(tcsr, NPCM7xxTimer),
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|
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VMSTATE_UINT32(ticr, NPCM7xxTimer),
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|
|
|
VMSTATE_END_OF_LIST(),
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|
|
|
},
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|
|
|
};
|
|
|
|
|
2020-10-24 00:06:34 +03:00
|
|
|
static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
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|
|
|
.name = "npcm7xx-watchdog-timer",
|
2020-09-11 08:20:50 +03:00
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
2020-10-24 00:06:34 +03:00
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_STRUCT(base_timer, NPCM7xxWatchdogTimer,
|
|
|
|
0, vmstate_npcm7xx_base_timer,
|
|
|
|
NPCM7xxBaseTimer),
|
|
|
|
VMSTATE_UINT32(wtcr, NPCM7xxWatchdogTimer),
|
|
|
|
VMSTATE_END_OF_LIST(),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
|
|
|
|
.name = "npcm7xx-timer-ctrl",
|
2021-01-08 22:09:41 +03:00
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 2,
|
2020-09-11 08:20:50 +03:00
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
|
2021-01-08 22:09:41 +03:00
|
|
|
VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
|
2020-09-11 08:20:50 +03:00
|
|
|
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
|
|
|
|
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
|
|
|
|
NPCM7xxTimer),
|
2020-10-24 00:06:34 +03:00
|
|
|
VMSTATE_STRUCT(watchdog_timer, NPCM7xxTimerCtrlState,
|
|
|
|
0, vmstate_npcm7xx_watchdog_timer,
|
|
|
|
NPCM7xxWatchdogTimer),
|
2020-09-11 08:20:50 +03:00
|
|
|
VMSTATE_END_OF_LIST(),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
|
|
|
|
|
|
|
|
dc->desc = "NPCM7xx Timer Controller";
|
|
|
|
dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
|
|
|
|
rc->phases.enter = npcm7xx_timer_enter_reset;
|
|
|
|
rc->phases.hold = npcm7xx_timer_hold_reset;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo npcm7xx_timer_info = {
|
|
|
|
.name = TYPE_NPCM7XX_TIMER,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(NPCM7xxTimerCtrlState),
|
|
|
|
.class_init = npcm7xx_timer_class_init,
|
2021-01-08 22:09:41 +03:00
|
|
|
.instance_init = npcm7xx_timer_init,
|
2020-09-11 08:20:50 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
static void npcm7xx_timer_register_type(void)
|
|
|
|
{
|
|
|
|
type_register_static(&npcm7xx_timer_info);
|
|
|
|
}
|
|
|
|
type_init(npcm7xx_timer_register_type);
|