2013-12-17 23:42:38 +04:00
|
|
|
#ifndef ALLWINNER_H_
|
|
|
|
|
|
|
|
|
|
#include "qemu-common.h"
|
|
|
|
|
#include "qemu/error-report.h"
|
|
|
|
|
#include "hw/char/serial.h"
|
|
|
|
|
#include "hw/arm/arm.h"
|
|
|
|
|
#include "hw/timer/allwinner-a10-pit.h"
|
|
|
|
|
#include "hw/intc/allwinner-a10-pic.h"
|
2014-01-31 02:02:07 +04:00
|
|
|
#include "hw/net/allwinner_emac.h"
|
2015-11-06 22:09:01 +03:00
|
|
|
#include "hw/ide/pci.h"
|
|
|
|
|
#include "hw/ide/ahci.h"
|
2013-12-17 23:42:38 +04:00
|
|
|
|
|
|
|
|
#include "sysemu/sysemu.h"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#define AW_A10_PIC_REG_BASE 0x01c20400
|
|
|
|
|
#define AW_A10_PIT_REG_BASE 0x01c20c00
|
|
|
|
|
#define AW_A10_UART0_REG_BASE 0x01c28000
|
2014-01-31 02:02:07 +04:00
|
|
|
#define AW_A10_EMAC_BASE 0x01c0b000
|
2015-11-06 22:09:01 +03:00
|
|
|
#define AW_A10_SATA_BASE 0x01c18000
|
2013-12-17 23:42:38 +04:00
|
|
|
|
|
|
|
|
#define AW_A10_SDRAM_BASE 0x40000000
|
|
|
|
|
|
|
|
|
|
#define TYPE_AW_A10 "allwinner-a10"
|
|
|
|
|
#define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10)
|
|
|
|
|
|
|
|
|
|
typedef struct AwA10State {
|
|
|
|
|
/*< private >*/
|
|
|
|
|
DeviceState parent_obj;
|
|
|
|
|
/*< public >*/
|
|
|
|
|
|
|
|
|
|
ARMCPU cpu;
|
|
|
|
|
qemu_irq irq[AW_A10_PIC_INT_NR];
|
|
|
|
|
AwA10PITState timer;
|
|
|
|
|
AwA10PICState intc;
|
2014-01-31 02:02:07 +04:00
|
|
|
AwEmacState emac;
|
2015-11-06 22:09:01 +03:00
|
|
|
AllwinnerAHCIState sata;
|
2013-12-17 23:42:38 +04:00
|
|
|
} AwA10State;
|
|
|
|
|
|
|
|
|
|
#define ALLWINNER_H_
|
|
|
|
|
#endif
|
