64 lines
2.0 KiB
ArmAsm
64 lines
2.0 KiB
ArmAsm
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/*
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* Test s390x-softmmu precise self-modifying code handling.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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.org 0x8e
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program_interruption_code:
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.org 0x150
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program_old_psw:
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.org 0x1D0 /* program new PSW */
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.quad 0x180000000,pgm /* 64-bit mode */
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.org 0x200 /* lowcore padding */
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.globl _start
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_start:
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lctlg %c0,%c0,c0
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lghi %r0,15
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/* Test 1: replace sgr with agr. */
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lghi %r1,21
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vl %v0,patch1
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jg 1f /* start a new TB */
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0:
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.org . + 6 /* pad patched code to 16 bytes */
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1:
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vstl %v0,%r0,0b /* start writing before TB */
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sgr %r1,%r1 /* this becomes `agr %r1,%r1` */
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cgijne %r1,42,failure
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/* Test 2: replace agr with division by zero. */
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vl %v0,patch2
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jg 1f /* start a new TB */
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0:
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.org . + 6 /* pad patched code to 16 bytes */
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1:
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vstl %v0,%r0,0b /* start writing before TB */
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sgr %r1,%r1 /* this becomes `d %r0,zero` */
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failure:
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lpswe failure_psw
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pgm:
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chhsi program_interruption_code,0x9 /* divide exception? */
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jne failure
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clc program_old_psw(16),expected_old_psw2 /* correct old PSW? */
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jne failure
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lpswe success_psw
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patch1:
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.fill 12 /* replaces padding and stpq */
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agr %r1,%r1 /* replaces sgr */
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patch2:
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.fill 12 /* replaces padding and stpq */
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d %r0,zero /* replaces sgr */
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zero:
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.long 0
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expected_old_psw2:
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.quad 0x200180000000,failure /* cc is from addition */
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.align 8
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c0:
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.quad 0x60000 /* AFP, VX */
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success_psw:
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.quad 0x2000000000000,0xfff /* see is_special_wait_psw() */
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failure_psw:
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.quad 0x2000000000000,0 /* disabled wait */
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