2020-11-30 00:24:40 +03:00
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# MIPS SIMD Architecture Module instruction set
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#
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# Copyright (C) 2020 Philippe Mathieu-Daudé
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#
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# SPDX-License-Identifier: LGPL-2.1-or-later
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#
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# Reference:
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# MIPS Architecture for Programmers Volume IV-j
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2021-05-29 21:06:13 +03:00
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# - The MIPS32 SIMD Architecture Module, Revision 1.12
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# (Document Number: MD00866-2B-MSA32-AFP-01.12)
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# - The MIPS64 SIMD Architecture Module, Revision 1.12
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# (Document Number: MD00868-1D-MSA64-AFP-01.12)
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2020-11-30 00:24:40 +03:00
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2021-07-27 22:13:49 +03:00
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&r rs rt rd sa
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2020-12-08 20:59:36 +03:00
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2021-10-19 09:18:25 +03:00
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&msa_bz df wt sa
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2021-10-19 09:22:31 +03:00
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&msa_ldi df wd sa
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2021-10-19 09:27:58 +03:00
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&msa_i df wd ws sa
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2021-10-19 09:47:29 +03:00
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&msa_bit df wd ws m
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%bit_df 16:7 !function=bit_df
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%bit_m 16:7 !function=bit_m
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2020-11-30 00:24:40 +03:00
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2021-07-27 22:13:49 +03:00
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@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
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2021-10-19 11:02:55 +03:00
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@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
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2021-10-19 09:18:25 +03:00
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@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
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@bz ...... ... df:2 wt:5 sa:16 &msa_bz
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2021-10-19 09:27:58 +03:00
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@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i
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@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i
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2021-10-19 10:54:17 +03:00
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@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i
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2021-10-19 10:56:51 +03:00
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@i8 ...... .. sa:s8 ws:5 wd:5 ...... &msa_i df=0
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2021-10-19 09:22:31 +03:00
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@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
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2021-10-19 09:47:29 +03:00
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@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%bit_df m=%bit_m
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2020-11-30 00:24:40 +03:00
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2020-12-08 20:59:36 +03:00
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LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
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2021-05-29 21:06:13 +03:00
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DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
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2020-12-08 20:59:36 +03:00
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2021-10-19 09:18:25 +03:00
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BZ_V 010001 01011 ..... ................ @bz_v
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BNZ_V 010001 01111 ..... ................ @bz_v
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BZ 010001 110 .. ..... ................ @bz
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BNZ 010001 111 .. ..... ................ @bz
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2020-11-30 00:24:40 +03:00
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2021-10-19 09:22:31 +03:00
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{
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2021-10-19 10:56:51 +03:00
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ANDI 011110 00 ........ ..... ..... 000000 @i8
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ORI 011110 01 ........ ..... ..... 000000 @i8
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NORI 011110 10 ........ ..... ..... 000000 @i8
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XORI 011110 11 ........ ..... ..... 000000 @i8
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BMNZI 011110 00 ........ ..... ..... 000001 @i8
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BMZI 011110 01 ........ ..... ..... 000001 @i8
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BSELI 011110 10 ........ ..... ..... 000001 @i8
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2021-10-19 10:54:17 +03:00
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SHF 011110 .. ........ ..... ..... 000010 @i8_df
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2021-10-19 09:27:58 +03:00
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ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
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SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
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MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
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MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5
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MINI_S 011110 100 .. ..... ..... ..... 000110 @s5
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MINI_U 011110 101 .. ..... ..... ..... 000110 @u5
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CEQI 011110 000 .. ..... ..... ..... 000111 @s5
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CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5
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CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5
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CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5
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CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5
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2021-10-19 09:22:31 +03:00
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LDI 011110 110 .. .......... ..... 000111 @ldi
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2021-10-19 09:47:29 +03:00
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SLLI 011110 000 ....... ..... ..... 001001 @bit
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SRAI 011110 001 ....... ..... ..... 001001 @bit
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SRLI 011110 010 ....... ..... ..... 001001 @bit
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BCLRI 011110 011 ....... ..... ..... 001001 @bit
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BSETI 011110 100 ....... ..... ..... 001001 @bit
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BNEGI 011110 101 ....... ..... ..... 001001 @bit
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BINSLI 011110 110 ....... ..... ..... 001001 @bit
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BINSRI 011110 111 ....... ..... ..... 001001 @bit
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SAT_S 011110 000 ....... ..... ..... 001010 @bit
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SAT_U 011110 001 ....... ..... ..... 001010 @bit
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SRARI 011110 010 ....... ..... ..... 001010 @bit
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SRLRI 011110 011 ....... ..... ..... 001010 @bit
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2021-10-19 11:02:55 +03:00
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LD 011110 .......... ..... ..... 1000 .. @ldst
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ST 011110 .......... ..... ..... 1001 .. @ldst
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2021-10-19 09:22:31 +03:00
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MSA 011110 --------------------------
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}
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