2003-08-05 03:30:47 +04:00
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/*
|
2004-02-06 22:47:52 +03:00
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* QEMU VGA Emulator.
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2007-09-17 01:08:06 +04:00
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*
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2003-08-05 03:30:47 +04:00
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* Copyright (c) 2003 Fabrice Bellard
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2007-09-17 01:08:06 +04:00
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*
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2003-08-05 03:30:47 +04:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-01-26 21:17:13 +03:00
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#include "qemu/osdep.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
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#include "qapi/error.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/hw.h"
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2013-03-18 20:36:02 +04:00
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#include "vga.h"
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2012-11-28 15:06:30 +04:00
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#include "ui/console.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/i386/pc.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/pci/pci.h"
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2013-03-18 20:36:02 +04:00
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#include "vga_int.h"
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2012-11-28 15:06:30 +04:00
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#include "ui/pixel_ops.h"
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2012-12-17 21:20:00 +04:00
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#include "qemu/timer.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/xen/xen.h"
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2012-03-11 20:11:27 +04:00
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#include "trace.h"
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2003-08-05 03:30:47 +04:00
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2003-08-09 03:50:57 +04:00
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//#define DEBUG_VGA_MEM
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2004-01-04 18:55:00 +03:00
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//#define DEBUG_VGA_REG
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2012-07-04 21:49:54 +04:00
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/* 16 state changes per vertical frame @60 Hz */
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#define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
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2012-01-29 21:29:12 +04:00
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/*
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* Video Graphics Array (VGA)
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*
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* Chipset docs for original IBM VGA:
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* http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
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*
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* FreeVGA site:
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* http://www.osdever.net/FreeVGA/home.htm
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*
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* Standard VGA features and Bochs VBE extensions are implemented.
|
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*/
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2003-08-05 03:30:47 +04:00
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/* force some bits to zero */
|
2004-06-05 14:30:49 +04:00
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const uint8_t sr_mask[8] = {
|
2009-03-07 18:46:23 +03:00
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0x03,
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0x3d,
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0x0f,
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0x3f,
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0x0e,
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0x00,
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0x00,
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0xff,
|
2003-08-05 03:30:47 +04:00
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};
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2004-06-05 14:30:49 +04:00
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const uint8_t gr_mask[16] = {
|
2009-03-07 18:46:23 +03:00
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0x0f, /* 0x00 */
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0x0f, /* 0x01 */
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0x0f, /* 0x02 */
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0x1f, /* 0x03 */
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0x03, /* 0x04 */
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0x7b, /* 0x05 */
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0x0f, /* 0x06 */
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0x0f, /* 0x07 */
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0xff, /* 0x08 */
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0x00, /* 0x09 */
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0x00, /* 0x0a */
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0x00, /* 0x0b */
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0x00, /* 0x0c */
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0x00, /* 0x0d */
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0x00, /* 0x0e */
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0x00, /* 0x0f */
|
2003-08-05 03:30:47 +04:00
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};
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|
#define cbswap_32(__x) \
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((uint32_t)( \
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(((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
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(((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
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(((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
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(((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
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|
2009-07-27 18:13:06 +04:00
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#ifdef HOST_WORDS_BIGENDIAN
|
2003-08-05 03:30:47 +04:00
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#define PAT(x) cbswap_32(x)
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#else
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#define PAT(x) (x)
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#endif
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|
2009-07-27 18:13:06 +04:00
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#ifdef HOST_WORDS_BIGENDIAN
|
2003-10-31 01:10:22 +03:00
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#define BIG 1
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#else
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#define BIG 0
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|
#endif
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|
2009-07-27 18:13:06 +04:00
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#ifdef HOST_WORDS_BIGENDIAN
|
2003-10-31 01:10:22 +03:00
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#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
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#else
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#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
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#endif
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2003-08-05 03:30:47 +04:00
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static const uint32_t mask16[16] = {
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PAT(0x00000000),
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PAT(0x000000ff),
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PAT(0x0000ff00),
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PAT(0x0000ffff),
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PAT(0x00ff0000),
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PAT(0x00ff00ff),
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PAT(0x00ffff00),
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PAT(0x00ffffff),
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PAT(0xff000000),
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PAT(0xff0000ff),
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PAT(0xff00ff00),
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PAT(0xff00ffff),
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PAT(0xffff0000),
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PAT(0xffff00ff),
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PAT(0xffffff00),
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PAT(0xffffffff),
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};
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#undef PAT
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|
2009-07-27 18:13:06 +04:00
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#ifdef HOST_WORDS_BIGENDIAN
|
2003-08-05 03:30:47 +04:00
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#define PAT(x) (x)
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#else
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#define PAT(x) cbswap_32(x)
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#endif
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static uint32_t expand4[256];
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static uint16_t expand2[256];
|
2003-08-09 03:50:57 +04:00
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static uint8_t expand4to8[16];
|
2003-08-05 03:30:47 +04:00
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|
2016-04-26 15:48:06 +03:00
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static void vbe_update_vgaregs(VGACommonState *s);
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|
2016-04-26 15:11:34 +03:00
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static inline bool vbe_enabled(VGACommonState *s)
|
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|
|
{
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|
return s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED;
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|
|
|
}
|
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|
|
2016-05-17 11:54:54 +03:00
|
|
|
static inline uint8_t sr(VGACommonState *s, int idx)
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|
|
|
{
|
|
|
|
return vbe_enabled(s) ? s->sr_vbe[idx] : s->sr[idx];
|
|
|
|
}
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|
2011-08-22 21:12:12 +04:00
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static void vga_update_memory_access(VGACommonState *s)
|
|
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{
|
2012-10-23 14:30:10 +04:00
|
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hwaddr base, offset, size;
|
2011-08-22 21:12:12 +04:00
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|
2012-11-12 17:29:47 +04:00
|
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|
if (s->legacy_address_space == NULL) {
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|
return;
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|
}
|
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|
2014-06-11 14:19:25 +04:00
|
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|
if (s->has_chain4_alias) {
|
|
|
|
memory_region_del_subregion(s->legacy_address_space, &s->chain4_alias);
|
2014-06-11 14:42:01 +04:00
|
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|
object_unparent(OBJECT(&s->chain4_alias));
|
2014-06-11 14:19:25 +04:00
|
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|
s->has_chain4_alias = false;
|
|
|
|
s->plane_updated = 0xf;
|
|
|
|
}
|
2016-05-17 11:54:54 +03:00
|
|
|
if ((sr(s, VGA_SEQ_PLANE_WRITE) & VGA_SR02_ALL_PLANES) ==
|
|
|
|
VGA_SR02_ALL_PLANES && sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
|
2011-08-22 21:12:12 +04:00
|
|
|
offset = 0;
|
2012-01-29 21:02:07 +04:00
|
|
|
switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
|
2011-08-22 21:12:12 +04:00
|
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|
case 0:
|
|
|
|
base = 0xa0000;
|
|
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|
size = 0x20000;
|
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|
|
break;
|
|
|
|
case 1:
|
|
|
|
base = 0xa0000;
|
|
|
|
size = 0x10000;
|
|
|
|
offset = s->bank_offset;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
base = 0xb0000;
|
|
|
|
size = 0x8000;
|
|
|
|
break;
|
|
|
|
case 3:
|
2011-08-25 13:10:13 +04:00
|
|
|
default:
|
2011-08-22 21:12:12 +04:00
|
|
|
base = 0xb8000;
|
|
|
|
size = 0x8000;
|
|
|
|
break;
|
|
|
|
}
|
2016-04-26 09:49:10 +03:00
|
|
|
assert(offset + size <= s->vram_size);
|
2014-06-11 14:19:25 +04:00
|
|
|
memory_region_init_alias(&s->chain4_alias, memory_region_owner(&s->vram),
|
2013-06-07 05:21:13 +04:00
|
|
|
"vga.chain4", &s->vram, offset, size);
|
2011-08-22 21:12:12 +04:00
|
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|
memory_region_add_subregion_overlap(s->legacy_address_space, base,
|
2014-06-11 14:19:25 +04:00
|
|
|
&s->chain4_alias, 2);
|
|
|
|
s->has_chain4_alias = true;
|
2011-08-22 21:12:12 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
static void vga_dumb_update_retrace_info(VGACommonState *s)
|
2008-09-28 04:42:12 +04:00
|
|
|
{
|
|
|
|
(void) s;
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
static void vga_precise_update_retrace_info(VGACommonState *s)
|
2008-09-28 04:42:12 +04:00
|
|
|
{
|
|
|
|
int htotal_chars;
|
|
|
|
int hretr_start_char;
|
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|
|
int hretr_skew_chars;
|
|
|
|
int hretr_end_char;
|
|
|
|
|
|
|
|
int vtotal_lines;
|
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|
|
int vretr_start_line;
|
|
|
|
int vretr_end_line;
|
|
|
|
|
2010-04-25 22:58:25 +04:00
|
|
|
int dots;
|
|
|
|
#if 0
|
|
|
|
int div2, sldiv2;
|
|
|
|
#endif
|
2008-09-28 04:42:12 +04:00
|
|
|
int clocking_mode;
|
|
|
|
int clock_sel;
|
2008-11-12 20:36:08 +03:00
|
|
|
const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
|
2008-09-28 04:42:12 +04:00
|
|
|
int64_t chars_per_sec;
|
|
|
|
struct vga_precise_retrace *r = &s->retrace_info.precise;
|
|
|
|
|
2012-01-29 21:02:07 +04:00
|
|
|
htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
|
|
|
|
hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
|
|
|
|
hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
|
|
|
|
hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
|
2008-09-28 04:42:12 +04:00
|
|
|
|
2012-01-29 21:02:07 +04:00
|
|
|
vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
|
|
|
|
(((s->cr[VGA_CRTC_OVERFLOW] & 1) |
|
|
|
|
((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
|
|
|
|
vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
|
|
|
|
((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
|
|
|
|
((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
|
|
|
|
vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
|
2008-09-28 04:42:12 +04:00
|
|
|
|
2016-05-17 11:54:54 +03:00
|
|
|
clocking_mode = (sr(s, VGA_SEQ_CLOCK_MODE) >> 3) & 1;
|
2008-09-28 04:42:12 +04:00
|
|
|
clock_sel = (s->msr >> 2) & 3;
|
2008-09-28 06:43:18 +04:00
|
|
|
dots = (s->msr & 1) ? 8 : 9;
|
2008-09-28 04:42:12 +04:00
|
|
|
|
2008-11-12 20:36:08 +03:00
|
|
|
chars_per_sec = clk_hz[clock_sel] / dots;
|
2008-09-28 04:42:12 +04:00
|
|
|
|
|
|
|
htotal_chars <<= clocking_mode;
|
|
|
|
|
|
|
|
r->total_chars = vtotal_lines * htotal_chars;
|
|
|
|
if (r->freq) {
|
2016-03-21 19:02:30 +03:00
|
|
|
r->ticks_per_char = NANOSECONDS_PER_SECOND / (r->total_chars * r->freq);
|
2008-09-28 04:42:12 +04:00
|
|
|
} else {
|
2016-03-21 19:02:30 +03:00
|
|
|
r->ticks_per_char = NANOSECONDS_PER_SECOND / chars_per_sec;
|
2008-09-28 04:42:12 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
r->vstart = vretr_start_line;
|
|
|
|
r->vend = r->vstart + vretr_end_line + 1;
|
|
|
|
|
|
|
|
r->hstart = hretr_start_char + hretr_skew_chars;
|
|
|
|
r->hend = r->hstart + hretr_end_char + 1;
|
|
|
|
r->htotal = htotal_chars;
|
|
|
|
|
2008-09-28 06:43:18 +04:00
|
|
|
#if 0
|
2012-01-29 21:02:07 +04:00
|
|
|
div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
|
|
|
|
sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
|
2008-09-28 04:42:12 +04:00
|
|
|
printf (
|
2008-09-28 06:43:18 +04:00
|
|
|
"hz=%f\n"
|
2008-09-28 04:42:12 +04:00
|
|
|
"htotal = %d\n"
|
|
|
|
"hretr_start = %d\n"
|
|
|
|
"hretr_skew = %d\n"
|
|
|
|
"hretr_end = %d\n"
|
|
|
|
"vtotal = %d\n"
|
|
|
|
"vretr_start = %d\n"
|
|
|
|
"vretr_end = %d\n"
|
|
|
|
"div2 = %d sldiv2 = %d\n"
|
|
|
|
"clocking_mode = %d\n"
|
|
|
|
"clock_sel = %d %d\n"
|
|
|
|
"dots = %d\n"
|
2010-05-22 12:02:12 +04:00
|
|
|
"ticks/char = %" PRId64 "\n"
|
2008-09-28 04:42:12 +04:00
|
|
|
"\n",
|
2016-03-21 19:02:30 +03:00
|
|
|
(double) NANOSECONDS_PER_SECOND / (r->ticks_per_char * r->total_chars),
|
2008-09-28 04:42:12 +04:00
|
|
|
htotal_chars,
|
|
|
|
hretr_start_char,
|
|
|
|
hretr_skew_chars,
|
|
|
|
hretr_end_char,
|
|
|
|
vtotal_lines,
|
|
|
|
vretr_start_line,
|
|
|
|
vretr_end_line,
|
|
|
|
div2, sldiv2,
|
|
|
|
clocking_mode,
|
|
|
|
clock_sel,
|
2008-11-12 20:36:08 +03:00
|
|
|
clk_hz[clock_sel],
|
2008-09-28 04:42:12 +04:00
|
|
|
dots,
|
|
|
|
r->ticks_per_char
|
|
|
|
);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
static uint8_t vga_precise_retrace(VGACommonState *s)
|
2008-09-28 04:42:12 +04:00
|
|
|
{
|
|
|
|
struct vga_precise_retrace *r = &s->retrace_info.precise;
|
|
|
|
uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
|
|
|
|
|
|
|
|
if (r->total_chars) {
|
|
|
|
int cur_line, cur_line_char, cur_char;
|
|
|
|
int64_t cur_tick;
|
|
|
|
|
2013-08-21 19:03:08 +04:00
|
|
|
cur_tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
2008-09-28 04:42:12 +04:00
|
|
|
|
|
|
|
cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
|
|
|
|
cur_line = cur_char / r->htotal;
|
|
|
|
|
|
|
|
if (cur_line >= r->vstart && cur_line <= r->vend) {
|
|
|
|
val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
|
2008-09-28 06:43:18 +04:00
|
|
|
} else {
|
|
|
|
cur_line_char = cur_char % r->htotal;
|
|
|
|
if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
|
|
|
|
val |= ST01_DISP_ENABLE;
|
|
|
|
}
|
2008-09-28 04:42:12 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
|
|
|
} else {
|
|
|
|
return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
static uint8_t vga_dumb_retrace(VGACommonState *s)
|
2008-09-28 04:42:12 +04:00
|
|
|
{
|
|
|
|
return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:19 +04:00
|
|
|
int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
|
|
|
|
{
|
2012-01-29 21:02:07 +04:00
|
|
|
if (s->msr & VGA_MIS_COLOR) {
|
2009-08-31 18:07:19 +04:00
|
|
|
/* Color */
|
|
|
|
return (addr >= 0x3b0 && addr <= 0x3bf);
|
|
|
|
} else {
|
|
|
|
/* Monochrome */
|
|
|
|
return (addr >= 0x3d0 && addr <= 0x3df);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:13 +04:00
|
|
|
uint32_t vga_ioport_read(void *opaque, uint32_t addr)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
2009-08-31 18:07:13 +04:00
|
|
|
VGACommonState *s = opaque;
|
2003-08-05 03:30:47 +04:00
|
|
|
int val, index;
|
|
|
|
|
2009-08-31 18:07:19 +04:00
|
|
|
if (vga_ioport_invalid(s, addr)) {
|
2003-08-05 03:30:47 +04:00
|
|
|
val = 0xff;
|
|
|
|
} else {
|
|
|
|
switch(addr) {
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_ATT_W:
|
2003-08-05 03:30:47 +04:00
|
|
|
if (s->ar_flip_flop == 0) {
|
|
|
|
val = s->ar_index;
|
|
|
|
} else {
|
|
|
|
val = 0;
|
|
|
|
}
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_ATT_R:
|
2003-08-05 03:30:47 +04:00
|
|
|
index = s->ar_index & 0x1f;
|
2012-01-29 21:02:07 +04:00
|
|
|
if (index < VGA_ATT_C) {
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->ar[index];
|
2012-01-29 21:02:07 +04:00
|
|
|
} else {
|
2003-08-05 03:30:47 +04:00
|
|
|
val = 0;
|
2012-01-29 21:02:07 +04:00
|
|
|
}
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_MIS_W:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->st00;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_SEQ_I:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->sr_index;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_SEQ_D:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->sr[s->sr_index];
|
2004-01-04 18:55:00 +03:00
|
|
|
#ifdef DEBUG_VGA_REG
|
|
|
|
printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
|
|
|
|
#endif
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_PEL_IR:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->dac_state;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_PEL_IW:
|
2009-08-31 18:07:21 +04:00
|
|
|
val = s->dac_write_index;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_PEL_D:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
|
|
|
|
if (++s->dac_sub_index == 3) {
|
|
|
|
s->dac_sub_index = 0;
|
|
|
|
s->dac_read_index++;
|
|
|
|
}
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_FTC_R:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->fcr;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_MIS_R:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->msr;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_GFX_I:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->gr_index;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_GFX_D:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->gr[s->gr_index];
|
2004-01-04 18:55:00 +03:00
|
|
|
#ifdef DEBUG_VGA_REG
|
|
|
|
printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
|
|
|
|
#endif
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_CRT_IM:
|
|
|
|
case VGA_CRT_IC:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->cr_index;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_CRT_DM:
|
|
|
|
case VGA_CRT_DC:
|
2003-08-05 03:30:47 +04:00
|
|
|
val = s->cr[s->cr_index];
|
2004-01-04 18:55:00 +03:00
|
|
|
#ifdef DEBUG_VGA_REG
|
|
|
|
printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
|
|
|
|
#endif
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_IS1_RM:
|
|
|
|
case VGA_IS1_RC:
|
2003-08-05 03:30:47 +04:00
|
|
|
/* just toggle to fool polling */
|
2008-09-28 04:42:12 +04:00
|
|
|
val = s->st01 = s->retrace(s);
|
2003-08-05 03:30:47 +04:00
|
|
|
s->ar_flip_flop = 0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
val = 0x00;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2017-02-08 16:51:32 +03:00
|
|
|
trace_vga_std_read_io(addr, val);
|
2003-08-05 03:30:47 +04:00
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:13 +04:00
|
|
|
void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
2009-08-31 18:07:13 +04:00
|
|
|
VGACommonState *s = opaque;
|
2004-04-25 21:59:00 +04:00
|
|
|
int index;
|
2003-08-05 03:30:47 +04:00
|
|
|
|
|
|
|
/* check port range access depending on color/monochrome mode */
|
2009-08-31 18:07:19 +04:00
|
|
|
if (vga_ioport_invalid(s, addr)) {
|
2003-08-05 03:30:47 +04:00
|
|
|
return;
|
2009-08-31 18:07:19 +04:00
|
|
|
}
|
2017-02-08 16:51:32 +03:00
|
|
|
trace_vga_std_write_io(addr, val);
|
2003-08-05 03:30:47 +04:00
|
|
|
|
|
|
|
switch(addr) {
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_ATT_W:
|
2003-08-05 03:30:47 +04:00
|
|
|
if (s->ar_flip_flop == 0) {
|
|
|
|
val &= 0x3f;
|
|
|
|
s->ar_index = val;
|
|
|
|
} else {
|
|
|
|
index = s->ar_index & 0x1f;
|
|
|
|
switch(index) {
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->ar[index] = val & 0x3f;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_ATC_MODE:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->ar[index] = val & ~0x10;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_ATC_OVERSCAN:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->ar[index] = val;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_ATC_PLANE_ENABLE:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->ar[index] = val & ~0xc0;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_ATC_PEL:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->ar[index] = val & ~0xf0;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_ATC_COLOR_PAGE:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->ar[index] = val & ~0xf0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
s->ar_flip_flop ^= 1;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_MIS_W:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->msr = val & ~0x10;
|
2008-09-28 04:42:12 +04:00
|
|
|
s->update_retrace_info(s);
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_SEQ_I:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->sr_index = val & 7;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_SEQ_D:
|
2004-01-04 18:55:00 +03:00
|
|
|
#ifdef DEBUG_VGA_REG
|
|
|
|
printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
|
|
|
#endif
|
2003-08-05 03:30:47 +04:00
|
|
|
s->sr[s->sr_index] = val & sr_mask[s->sr_index];
|
2012-01-29 21:02:07 +04:00
|
|
|
if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
|
|
|
|
s->update_retrace_info(s);
|
|
|
|
}
|
2011-08-22 21:12:12 +04:00
|
|
|
vga_update_memory_access(s);
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_PEL_IR:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->dac_read_index = val;
|
|
|
|
s->dac_sub_index = 0;
|
|
|
|
s->dac_state = 3;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_PEL_IW:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->dac_write_index = val;
|
|
|
|
s->dac_sub_index = 0;
|
|
|
|
s->dac_state = 0;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_PEL_D:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->dac_cache[s->dac_sub_index] = val;
|
|
|
|
if (++s->dac_sub_index == 3) {
|
|
|
|
memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
|
|
|
|
s->dac_sub_index = 0;
|
|
|
|
s->dac_write_index++;
|
|
|
|
}
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_GFX_I:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->gr_index = val & 0x0f;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_GFX_D:
|
2004-01-04 18:55:00 +03:00
|
|
|
#ifdef DEBUG_VGA_REG
|
|
|
|
printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
|
|
|
|
#endif
|
2003-08-05 03:30:47 +04:00
|
|
|
s->gr[s->gr_index] = val & gr_mask[s->gr_index];
|
2016-04-26 15:48:06 +03:00
|
|
|
vbe_update_vgaregs(s);
|
2011-08-22 21:12:12 +04:00
|
|
|
vga_update_memory_access(s);
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_CRT_IM:
|
|
|
|
case VGA_CRT_IC:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->cr_index = val;
|
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_CRT_DM:
|
|
|
|
case VGA_CRT_DC:
|
2004-01-04 18:55:00 +03:00
|
|
|
#ifdef DEBUG_VGA_REG
|
|
|
|
printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
|
|
|
|
#endif
|
2003-08-05 03:30:47 +04:00
|
|
|
/* handle CR0-7 protection */
|
2012-08-27 18:33:20 +04:00
|
|
|
if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
|
|
|
|
s->cr_index <= VGA_CRTC_OVERFLOW) {
|
|
|
|
/* can always write bit 4 of CR7 */
|
|
|
|
if (s->cr_index == VGA_CRTC_OVERFLOW) {
|
|
|
|
s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
|
|
|
|
(val & 0x10);
|
2016-04-26 15:48:06 +03:00
|
|
|
vbe_update_vgaregs(s);
|
2012-01-29 21:02:07 +04:00
|
|
|
}
|
2012-08-27 18:33:20 +04:00
|
|
|
return;
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
2009-08-31 18:07:23 +04:00
|
|
|
s->cr[s->cr_index] = val;
|
2016-04-26 15:48:06 +03:00
|
|
|
vbe_update_vgaregs(s);
|
2008-09-28 04:42:12 +04:00
|
|
|
|
|
|
|
switch(s->cr_index) {
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_CRTC_H_TOTAL:
|
|
|
|
case VGA_CRTC_H_SYNC_START:
|
|
|
|
case VGA_CRTC_H_SYNC_END:
|
|
|
|
case VGA_CRTC_V_TOTAL:
|
|
|
|
case VGA_CRTC_OVERFLOW:
|
|
|
|
case VGA_CRTC_V_SYNC_END:
|
|
|
|
case VGA_CRTC_MODE:
|
2008-09-28 04:42:12 +04:00
|
|
|
s->update_retrace_info(s);
|
|
|
|
break;
|
|
|
|
}
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
2012-01-29 21:02:07 +04:00
|
|
|
case VGA_IS1_RM:
|
|
|
|
case VGA_IS1_RC:
|
2003-08-05 03:30:47 +04:00
|
|
|
s->fcr = val & 0x10;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-08-26 17:35:23 +04:00
|
|
|
/*
|
|
|
|
* Sanity check vbe register writes.
|
|
|
|
*
|
|
|
|
* As we don't have a way to signal errors to the guest in the bochs
|
|
|
|
* dispi interface we'll go adjust the registers to the closest valid
|
|
|
|
* value.
|
|
|
|
*/
|
|
|
|
static void vbe_fixup_regs(VGACommonState *s)
|
|
|
|
{
|
|
|
|
uint16_t *r = s->vbe_regs;
|
|
|
|
uint32_t bits, linelength, maxy, offset;
|
|
|
|
|
2016-04-26 15:11:34 +03:00
|
|
|
if (!vbe_enabled(s)) {
|
2014-08-26 17:35:23 +04:00
|
|
|
/* vbe is turned off -- nothing to do */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check depth */
|
|
|
|
switch (r[VBE_DISPI_INDEX_BPP]) {
|
|
|
|
case 4:
|
|
|
|
case 8:
|
|
|
|
case 16:
|
|
|
|
case 24:
|
|
|
|
case 32:
|
|
|
|
bits = r[VBE_DISPI_INDEX_BPP];
|
|
|
|
break;
|
|
|
|
case 15:
|
|
|
|
bits = 16;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
bits = r[VBE_DISPI_INDEX_BPP] = 8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check width */
|
|
|
|
r[VBE_DISPI_INDEX_XRES] &= ~7u;
|
|
|
|
if (r[VBE_DISPI_INDEX_XRES] == 0) {
|
|
|
|
r[VBE_DISPI_INDEX_XRES] = 8;
|
|
|
|
}
|
|
|
|
if (r[VBE_DISPI_INDEX_XRES] > VBE_DISPI_MAX_XRES) {
|
|
|
|
r[VBE_DISPI_INDEX_XRES] = VBE_DISPI_MAX_XRES;
|
|
|
|
}
|
|
|
|
r[VBE_DISPI_INDEX_VIRT_WIDTH] &= ~7u;
|
|
|
|
if (r[VBE_DISPI_INDEX_VIRT_WIDTH] > VBE_DISPI_MAX_XRES) {
|
|
|
|
r[VBE_DISPI_INDEX_VIRT_WIDTH] = VBE_DISPI_MAX_XRES;
|
|
|
|
}
|
|
|
|
if (r[VBE_DISPI_INDEX_VIRT_WIDTH] < r[VBE_DISPI_INDEX_XRES]) {
|
|
|
|
r[VBE_DISPI_INDEX_VIRT_WIDTH] = r[VBE_DISPI_INDEX_XRES];
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check height */
|
|
|
|
linelength = r[VBE_DISPI_INDEX_VIRT_WIDTH] * bits / 8;
|
|
|
|
maxy = s->vbe_size / linelength;
|
|
|
|
if (r[VBE_DISPI_INDEX_YRES] == 0) {
|
|
|
|
r[VBE_DISPI_INDEX_YRES] = 1;
|
|
|
|
}
|
|
|
|
if (r[VBE_DISPI_INDEX_YRES] > VBE_DISPI_MAX_YRES) {
|
|
|
|
r[VBE_DISPI_INDEX_YRES] = VBE_DISPI_MAX_YRES;
|
|
|
|
}
|
|
|
|
if (r[VBE_DISPI_INDEX_YRES] > maxy) {
|
|
|
|
r[VBE_DISPI_INDEX_YRES] = maxy;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check offset */
|
|
|
|
if (r[VBE_DISPI_INDEX_X_OFFSET] > VBE_DISPI_MAX_XRES) {
|
|
|
|
r[VBE_DISPI_INDEX_X_OFFSET] = VBE_DISPI_MAX_XRES;
|
|
|
|
}
|
|
|
|
if (r[VBE_DISPI_INDEX_Y_OFFSET] > VBE_DISPI_MAX_YRES) {
|
|
|
|
r[VBE_DISPI_INDEX_Y_OFFSET] = VBE_DISPI_MAX_YRES;
|
|
|
|
}
|
|
|
|
offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
|
|
|
|
offset += r[VBE_DISPI_INDEX_Y_OFFSET] * linelength;
|
|
|
|
if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
|
|
|
|
r[VBE_DISPI_INDEX_Y_OFFSET] = 0;
|
|
|
|
offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
|
|
|
|
if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
|
|
|
|
r[VBE_DISPI_INDEX_X_OFFSET] = 0;
|
|
|
|
offset = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* update vga state */
|
|
|
|
r[VBE_DISPI_INDEX_VIRT_HEIGHT] = maxy;
|
|
|
|
s->vbe_line_offset = linelength;
|
|
|
|
s->vbe_start_addr = offset / 4;
|
|
|
|
}
|
|
|
|
|
2016-04-26 16:24:18 +03:00
|
|
|
/* we initialize the VGA graphic mode */
|
|
|
|
static void vbe_update_vgaregs(VGACommonState *s)
|
|
|
|
{
|
|
|
|
int h, shift_control;
|
|
|
|
|
|
|
|
if (!vbe_enabled(s)) {
|
|
|
|
/* vbe is turned off -- nothing to do */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* graphic mode + memory map 1 */
|
|
|
|
s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
|
|
|
|
VGA_GR06_GRAPHICS_MODE;
|
|
|
|
s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
|
|
|
|
s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
|
|
|
|
/* width */
|
|
|
|
s->cr[VGA_CRTC_H_DISP] =
|
|
|
|
(s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
|
|
|
|
/* height (only meaningful if < 1024) */
|
|
|
|
h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
|
|
|
|
s->cr[VGA_CRTC_V_DISP_END] = h;
|
|
|
|
s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
|
|
|
|
((h >> 7) & 0x02) | ((h >> 3) & 0x40);
|
|
|
|
/* line compare to 1023 */
|
|
|
|
s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
|
|
|
|
s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
|
|
|
|
s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
|
|
|
|
|
|
|
|
if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
|
|
|
|
shift_control = 0;
|
2016-05-17 11:54:54 +03:00
|
|
|
s->sr_vbe[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
|
2016-04-26 16:24:18 +03:00
|
|
|
} else {
|
|
|
|
shift_control = 2;
|
|
|
|
/* set chain 4 mode */
|
2016-05-17 11:54:54 +03:00
|
|
|
s->sr_vbe[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
|
2016-04-26 16:24:18 +03:00
|
|
|
/* activate all planes */
|
2016-05-17 11:54:54 +03:00
|
|
|
s->sr_vbe[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
|
2016-04-26 16:24:18 +03:00
|
|
|
}
|
|
|
|
s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
|
|
|
|
(shift_control << 5);
|
|
|
|
s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
|
|
|
|
}
|
|
|
|
|
2004-05-27 02:58:01 +04:00
|
|
|
static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
|
2004-02-06 22:47:52 +03:00
|
|
|
{
|
2009-08-31 18:07:24 +04:00
|
|
|
VGACommonState *s = opaque;
|
2016-06-14 00:57:58 +03:00
|
|
|
return s->vbe_index;
|
2004-05-27 02:58:01 +04:00
|
|
|
}
|
2004-02-06 22:47:52 +03:00
|
|
|
|
2012-10-15 10:02:55 +04:00
|
|
|
uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
|
2004-05-27 02:58:01 +04:00
|
|
|
{
|
2009-08-31 18:07:24 +04:00
|
|
|
VGACommonState *s = opaque;
|
2004-05-27 02:58:01 +04:00
|
|
|
uint32_t val;
|
|
|
|
|
2010-03-25 13:38:52 +03:00
|
|
|
if (s->vbe_index < VBE_DISPI_INDEX_NB) {
|
2006-06-13 20:37:40 +04:00
|
|
|
if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
|
|
|
|
switch(s->vbe_index) {
|
|
|
|
/* XXX: do not hardcode ? */
|
|
|
|
case VBE_DISPI_INDEX_XRES:
|
|
|
|
val = VBE_DISPI_MAX_XRES;
|
|
|
|
break;
|
|
|
|
case VBE_DISPI_INDEX_YRES:
|
|
|
|
val = VBE_DISPI_MAX_YRES;
|
|
|
|
break;
|
|
|
|
case VBE_DISPI_INDEX_BPP:
|
|
|
|
val = VBE_DISPI_MAX_BPP;
|
|
|
|
break;
|
|
|
|
default:
|
2007-09-17 01:08:06 +04:00
|
|
|
val = s->vbe_regs[s->vbe_index];
|
2006-06-13 20:37:40 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
2007-09-17 01:08:06 +04:00
|
|
|
val = s->vbe_regs[s->vbe_index];
|
2006-06-13 20:37:40 +04:00
|
|
|
}
|
2010-03-25 13:38:52 +03:00
|
|
|
} else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
|
2014-08-26 16:16:30 +04:00
|
|
|
val = s->vbe_size / (64 * 1024);
|
2006-06-13 20:37:40 +04:00
|
|
|
} else {
|
2004-05-27 02:58:01 +04:00
|
|
|
val = 0;
|
2006-06-13 20:37:40 +04:00
|
|
|
}
|
2017-02-08 16:51:32 +03:00
|
|
|
trace_vga_vbe_read(s->vbe_index, val);
|
2004-02-06 22:47:52 +03:00
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2012-10-15 10:02:55 +04:00
|
|
|
void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
|
2004-05-27 02:58:01 +04:00
|
|
|
{
|
2009-08-31 18:07:24 +04:00
|
|
|
VGACommonState *s = opaque;
|
2004-05-27 02:58:01 +04:00
|
|
|
s->vbe_index = val;
|
|
|
|
}
|
|
|
|
|
2012-10-15 10:02:55 +04:00
|
|
|
void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
|
2004-02-06 22:47:52 +03:00
|
|
|
{
|
2009-08-31 18:07:24 +04:00
|
|
|
VGACommonState *s = opaque;
|
2004-02-06 22:47:52 +03:00
|
|
|
|
2004-05-27 02:58:01 +04:00
|
|
|
if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
|
2017-02-08 16:51:32 +03:00
|
|
|
trace_vga_vbe_write(s->vbe_index, val);
|
2004-02-06 22:47:52 +03:00
|
|
|
switch(s->vbe_index) {
|
|
|
|
case VBE_DISPI_INDEX_ID:
|
2004-02-07 02:58:08 +03:00
|
|
|
if (val == VBE_DISPI_ID0 ||
|
|
|
|
val == VBE_DISPI_ID1 ||
|
2006-09-22 01:46:53 +04:00
|
|
|
val == VBE_DISPI_ID2 ||
|
|
|
|
val == VBE_DISPI_ID3 ||
|
|
|
|
val == VBE_DISPI_ID4) {
|
2004-02-07 02:58:08 +03:00
|
|
|
s->vbe_regs[s->vbe_index] = val;
|
|
|
|
}
|
2004-02-06 22:47:52 +03:00
|
|
|
break;
|
|
|
|
case VBE_DISPI_INDEX_XRES:
|
|
|
|
case VBE_DISPI_INDEX_YRES:
|
|
|
|
case VBE_DISPI_INDEX_BPP:
|
2014-08-26 17:35:23 +04:00
|
|
|
case VBE_DISPI_INDEX_VIRT_WIDTH:
|
|
|
|
case VBE_DISPI_INDEX_X_OFFSET:
|
|
|
|
case VBE_DISPI_INDEX_Y_OFFSET:
|
|
|
|
s->vbe_regs[s->vbe_index] = val;
|
|
|
|
vbe_fixup_regs(s);
|
2016-04-26 16:39:22 +03:00
|
|
|
vbe_update_vgaregs(s);
|
2004-02-06 22:47:52 +03:00
|
|
|
break;
|
|
|
|
case VBE_DISPI_INDEX_BANK:
|
2016-04-26 09:49:10 +03:00
|
|
|
val &= s->vbe_bank_mask;
|
2004-02-07 02:58:08 +03:00
|
|
|
s->vbe_regs[s->vbe_index] = val;
|
2004-04-29 02:26:05 +04:00
|
|
|
s->bank_offset = (val << 16);
|
2011-08-22 21:12:12 +04:00
|
|
|
vga_update_memory_access(s);
|
2004-02-06 22:47:52 +03:00
|
|
|
break;
|
|
|
|
case VBE_DISPI_INDEX_ENABLE:
|
2006-06-13 20:37:40 +04:00
|
|
|
if ((val & VBE_DISPI_ENABLED) &&
|
|
|
|
!(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
|
2004-02-06 22:47:52 +03:00
|
|
|
|
2014-08-26 17:35:23 +04:00
|
|
|
s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0;
|
2004-02-06 22:47:52 +03:00
|
|
|
s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
|
|
|
|
s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
|
2014-08-26 17:35:23 +04:00
|
|
|
s->vbe_regs[VBE_DISPI_INDEX_ENABLE] |= VBE_DISPI_ENABLED;
|
|
|
|
vbe_fixup_regs(s);
|
2016-04-26 16:24:18 +03:00
|
|
|
vbe_update_vgaregs(s);
|
2006-06-13 20:37:40 +04:00
|
|
|
|
2014-06-22 12:28:05 +04:00
|
|
|
/* clear the screen */
|
2004-02-06 22:47:52 +03:00
|
|
|
if (!(val & VBE_DISPI_NOCLEARMEM)) {
|
2007-09-17 01:08:06 +04:00
|
|
|
memset(s->vram_ptr, 0,
|
2004-02-06 22:47:52 +03:00
|
|
|
s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
|
|
|
|
}
|
2004-02-07 02:58:08 +03:00
|
|
|
} else {
|
2004-04-29 02:26:05 +04:00
|
|
|
s->bank_offset = 0;
|
2004-02-07 02:58:08 +03:00
|
|
|
}
|
2006-09-22 01:46:53 +04:00
|
|
|
s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
|
2004-04-29 23:21:16 +04:00
|
|
|
s->vbe_regs[s->vbe_index] = val;
|
2011-08-22 21:12:12 +04:00
|
|
|
vga_update_memory_access(s);
|
2004-02-07 02:58:08 +03:00
|
|
|
break;
|
2004-02-06 22:47:52 +03:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2003-08-05 03:30:47 +04:00
|
|
|
/* called for accesses between 0xa0000 and 0xc0000 */
|
2012-10-23 14:30:10 +04:00
|
|
|
uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
|
|
|
int memory_map_mode, plane;
|
|
|
|
uint32_t ret;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2003-08-05 03:30:47 +04:00
|
|
|
/* convert to VGA memory offset */
|
2012-01-29 21:02:07 +04:00
|
|
|
memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
|
2004-04-29 02:26:05 +04:00
|
|
|
addr &= 0x1ffff;
|
2003-08-05 03:30:47 +04:00
|
|
|
switch(memory_map_mode) {
|
|
|
|
case 0:
|
|
|
|
break;
|
|
|
|
case 1:
|
2004-04-29 02:26:05 +04:00
|
|
|
if (addr >= 0x10000)
|
2003-08-05 03:30:47 +04:00
|
|
|
return 0xff;
|
2004-02-07 02:58:08 +03:00
|
|
|
addr += s->bank_offset;
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
|
|
|
case 2:
|
2004-04-29 02:26:05 +04:00
|
|
|
addr -= 0x10000;
|
2003-08-05 03:30:47 +04:00
|
|
|
if (addr >= 0x8000)
|
|
|
|
return 0xff;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 3:
|
2004-04-29 02:26:05 +04:00
|
|
|
addr -= 0x18000;
|
2004-01-27 03:14:11 +03:00
|
|
|
if (addr >= 0x8000)
|
|
|
|
return 0xff;
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
|
|
|
}
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2016-05-17 11:54:54 +03:00
|
|
|
if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
|
2003-08-05 03:30:47 +04:00
|
|
|
/* chain 4 mode : simplest access */
|
2016-04-26 09:49:10 +03:00
|
|
|
assert(addr < s->vram_size);
|
2003-08-05 03:30:47 +04:00
|
|
|
ret = s->vram_ptr[addr];
|
2012-01-29 21:02:07 +04:00
|
|
|
} else if (s->gr[VGA_GFX_MODE] & 0x10) {
|
2003-08-05 03:30:47 +04:00
|
|
|
/* odd/even mode (aka text mode mapping) */
|
2012-01-29 21:02:07 +04:00
|
|
|
plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
|
2016-04-26 09:49:10 +03:00
|
|
|
addr = ((addr & ~1) << 1) | plane;
|
|
|
|
if (addr >= s->vram_size) {
|
|
|
|
return 0xff;
|
|
|
|
}
|
|
|
|
ret = s->vram_ptr[addr];
|
2003-08-05 03:30:47 +04:00
|
|
|
} else {
|
|
|
|
/* standard VGA latched access */
|
2016-04-26 09:49:10 +03:00
|
|
|
if (addr * sizeof(uint32_t) >= s->vram_size) {
|
|
|
|
return 0xff;
|
|
|
|
}
|
2003-08-05 03:30:47 +04:00
|
|
|
s->latch = ((uint32_t *)s->vram_ptr)[addr];
|
|
|
|
|
2012-01-29 21:02:07 +04:00
|
|
|
if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
|
2003-08-05 03:30:47 +04:00
|
|
|
/* read mode 0 */
|
2012-01-29 21:02:07 +04:00
|
|
|
plane = s->gr[VGA_GFX_PLANE_READ];
|
2003-10-31 01:10:22 +03:00
|
|
|
ret = GET_PLANE(s->latch, plane);
|
2003-08-05 03:30:47 +04:00
|
|
|
} else {
|
|
|
|
/* read mode 1 */
|
2012-01-29 21:02:07 +04:00
|
|
|
ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
|
|
|
|
mask16[s->gr[VGA_GFX_COMPARE_MASK]];
|
2003-08-05 03:30:47 +04:00
|
|
|
ret |= ret >> 16;
|
|
|
|
ret |= ret >> 8;
|
|
|
|
ret = (~ret) & 0xff;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* called for accesses between 0xa0000 and 0xc0000 */
|
2012-10-23 14:30:10 +04:00
|
|
|
void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
2004-11-14 20:52:01 +03:00
|
|
|
int memory_map_mode, plane, write_mode, b, func_select, mask;
|
2003-08-05 03:30:47 +04:00
|
|
|
uint32_t write_mask, bit_mask, set_mask;
|
|
|
|
|
2003-08-09 03:50:57 +04:00
|
|
|
#ifdef DEBUG_VGA_MEM
|
2009-07-20 21:19:25 +04:00
|
|
|
printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
|
2003-08-05 03:30:47 +04:00
|
|
|
#endif
|
|
|
|
/* convert to VGA memory offset */
|
2012-01-29 21:02:07 +04:00
|
|
|
memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
|
2004-04-29 02:26:05 +04:00
|
|
|
addr &= 0x1ffff;
|
2003-08-05 03:30:47 +04:00
|
|
|
switch(memory_map_mode) {
|
|
|
|
case 0:
|
|
|
|
break;
|
|
|
|
case 1:
|
2004-04-29 02:26:05 +04:00
|
|
|
if (addr >= 0x10000)
|
2003-08-05 03:30:47 +04:00
|
|
|
return;
|
2004-02-07 02:58:08 +03:00
|
|
|
addr += s->bank_offset;
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
|
|
|
case 2:
|
2004-04-29 02:26:05 +04:00
|
|
|
addr -= 0x10000;
|
2003-08-05 03:30:47 +04:00
|
|
|
if (addr >= 0x8000)
|
|
|
|
return;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case 3:
|
2004-04-29 02:26:05 +04:00
|
|
|
addr -= 0x18000;
|
2004-01-27 03:14:11 +03:00
|
|
|
if (addr >= 0x8000)
|
|
|
|
return;
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
|
|
|
}
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2016-05-17 11:54:54 +03:00
|
|
|
if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
|
2003-08-05 03:30:47 +04:00
|
|
|
/* chain 4 mode : simplest access */
|
|
|
|
plane = addr & 3;
|
2004-11-14 20:52:01 +03:00
|
|
|
mask = (1 << plane);
|
2016-05-17 11:54:54 +03:00
|
|
|
if (sr(s, VGA_SEQ_PLANE_WRITE) & mask) {
|
2016-04-26 09:49:10 +03:00
|
|
|
assert(addr < s->vram_size);
|
2003-08-05 03:30:47 +04:00
|
|
|
s->vram_ptr[addr] = val;
|
2003-08-09 03:50:57 +04:00
|
|
|
#ifdef DEBUG_VGA_MEM
|
2009-07-20 21:19:25 +04:00
|
|
|
printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
|
2003-08-05 03:30:47 +04:00
|
|
|
#endif
|
2004-11-14 20:52:01 +03:00
|
|
|
s->plane_updated |= mask; /* only used to detect font change */
|
2011-10-16 20:04:59 +04:00
|
|
|
memory_region_set_dirty(&s->vram, addr, 1);
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
2012-01-29 21:02:07 +04:00
|
|
|
} else if (s->gr[VGA_GFX_MODE] & 0x10) {
|
2003-08-05 03:30:47 +04:00
|
|
|
/* odd/even mode (aka text mode mapping) */
|
2012-01-29 21:02:07 +04:00
|
|
|
plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
|
2004-11-14 20:52:01 +03:00
|
|
|
mask = (1 << plane);
|
2016-05-17 11:54:54 +03:00
|
|
|
if (sr(s, VGA_SEQ_PLANE_WRITE) & mask) {
|
2003-08-05 03:30:47 +04:00
|
|
|
addr = ((addr & ~1) << 1) | plane;
|
2016-04-26 09:49:10 +03:00
|
|
|
if (addr >= s->vram_size) {
|
|
|
|
return;
|
|
|
|
}
|
2003-08-05 03:30:47 +04:00
|
|
|
s->vram_ptr[addr] = val;
|
2003-08-09 03:50:57 +04:00
|
|
|
#ifdef DEBUG_VGA_MEM
|
2009-07-20 21:19:25 +04:00
|
|
|
printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
|
2003-08-05 03:30:47 +04:00
|
|
|
#endif
|
2004-11-14 20:52:01 +03:00
|
|
|
s->plane_updated |= mask; /* only used to detect font change */
|
2011-10-16 20:04:59 +04:00
|
|
|
memory_region_set_dirty(&s->vram, addr, 1);
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* standard VGA latched access */
|
2012-01-29 21:02:07 +04:00
|
|
|
write_mode = s->gr[VGA_GFX_MODE] & 3;
|
2003-08-05 03:30:47 +04:00
|
|
|
switch(write_mode) {
|
|
|
|
default:
|
|
|
|
case 0:
|
|
|
|
/* rotate */
|
2012-01-29 21:02:07 +04:00
|
|
|
b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
|
2003-08-05 03:30:47 +04:00
|
|
|
val = ((val >> b) | (val << (8 - b))) & 0xff;
|
|
|
|
val |= val << 8;
|
|
|
|
val |= val << 16;
|
|
|
|
|
|
|
|
/* apply set/reset mask */
|
2012-01-29 21:02:07 +04:00
|
|
|
set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
|
|
|
|
val = (val & ~set_mask) |
|
|
|
|
(mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
|
|
|
|
bit_mask = s->gr[VGA_GFX_BIT_MASK];
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
val = s->latch;
|
|
|
|
goto do_write;
|
|
|
|
case 2:
|
|
|
|
val = mask16[val & 0x0f];
|
2012-01-29 21:02:07 +04:00
|
|
|
bit_mask = s->gr[VGA_GFX_BIT_MASK];
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
/* rotate */
|
2012-01-29 21:02:07 +04:00
|
|
|
b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
|
2004-01-04 18:55:00 +03:00
|
|
|
val = (val >> b) | (val << (8 - b));
|
2003-08-05 03:30:47 +04:00
|
|
|
|
2012-01-29 21:02:07 +04:00
|
|
|
bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
|
|
|
|
val = mask16[s->gr[VGA_GFX_SR_VALUE]];
|
2003-08-05 03:30:47 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* apply logical operation */
|
2012-01-29 21:02:07 +04:00
|
|
|
func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
|
2003-08-05 03:30:47 +04:00
|
|
|
switch(func_select) {
|
|
|
|
case 0:
|
|
|
|
default:
|
|
|
|
/* nothing to do */
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
/* and */
|
|
|
|
val &= s->latch;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
/* or */
|
|
|
|
val |= s->latch;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
/* xor */
|
|
|
|
val ^= s->latch;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* apply bit mask */
|
|
|
|
bit_mask |= bit_mask << 8;
|
|
|
|
bit_mask |= bit_mask << 16;
|
|
|
|
val = (val & bit_mask) | (s->latch & ~bit_mask);
|
|
|
|
|
|
|
|
do_write:
|
|
|
|
/* mask data according to sr[2] */
|
2016-05-17 11:54:54 +03:00
|
|
|
mask = sr(s, VGA_SEQ_PLANE_WRITE);
|
2004-11-14 20:52:01 +03:00
|
|
|
s->plane_updated |= mask; /* only used to detect font change */
|
|
|
|
write_mask = mask16[mask];
|
2016-04-26 09:49:10 +03:00
|
|
|
if (addr * sizeof(uint32_t) >= s->vram_size) {
|
|
|
|
return;
|
|
|
|
}
|
2007-09-17 01:08:06 +04:00
|
|
|
((uint32_t *)s->vram_ptr)[addr] =
|
|
|
|
(((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
|
2003-08-05 03:30:47 +04:00
|
|
|
(val & write_mask);
|
2003-08-09 03:50:57 +04:00
|
|
|
#ifdef DEBUG_VGA_MEM
|
2009-07-20 21:19:25 +04:00
|
|
|
printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
|
|
|
|
addr * 4, write_mask, val);
|
2003-08-05 03:30:47 +04:00
|
|
|
#endif
|
2011-10-16 20:04:59 +04:00
|
|
|
memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
|
2003-08-05 03:30:47 +04:00
|
|
|
const uint8_t *s, int width);
|
|
|
|
|
2014-06-23 05:46:06 +04:00
|
|
|
#include "vga-helpers.h"
|
2003-08-05 03:30:47 +04:00
|
|
|
|
|
|
|
/* return true if the palette was modified */
|
2009-08-31 18:07:24 +04:00
|
|
|
static int update_palette16(VGACommonState *s)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
2003-08-09 03:50:57 +04:00
|
|
|
int full_update, i;
|
2003-08-05 03:30:47 +04:00
|
|
|
uint32_t v, col, *palette;
|
|
|
|
|
|
|
|
full_update = 0;
|
|
|
|
palette = s->last_palette;
|
|
|
|
for(i = 0; i < 16; i++) {
|
|
|
|
v = s->ar[i];
|
2012-01-29 21:02:07 +04:00
|
|
|
if (s->ar[VGA_ATC_MODE] & 0x80) {
|
|
|
|
v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
|
|
|
|
} else {
|
|
|
|
v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
|
|
|
|
}
|
2003-08-05 03:30:47 +04:00
|
|
|
v = v * 3;
|
2014-06-22 05:00:50 +04:00
|
|
|
col = rgb_to_pixel32(c6_to_8(s->palette[v]),
|
|
|
|
c6_to_8(s->palette[v + 1]),
|
|
|
|
c6_to_8(s->palette[v + 2]));
|
2003-08-09 03:50:57 +04:00
|
|
|
if (col != palette[i]) {
|
|
|
|
full_update = 1;
|
|
|
|
palette[i] = col;
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
2003-08-09 03:50:57 +04:00
|
|
|
}
|
|
|
|
return full_update;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* return true if the palette was modified */
|
2009-08-31 18:07:24 +04:00
|
|
|
static int update_palette256(VGACommonState *s)
|
2003-08-09 03:50:57 +04:00
|
|
|
{
|
|
|
|
int full_update, i;
|
|
|
|
uint32_t v, col, *palette;
|
|
|
|
|
|
|
|
full_update = 0;
|
|
|
|
palette = s->last_palette;
|
|
|
|
v = 0;
|
|
|
|
for(i = 0; i < 256; i++) {
|
2006-09-22 01:46:53 +04:00
|
|
|
if (s->dac_8bit) {
|
2014-06-22 05:00:50 +04:00
|
|
|
col = rgb_to_pixel32(s->palette[v],
|
|
|
|
s->palette[v + 1],
|
|
|
|
s->palette[v + 2]);
|
2006-09-22 01:46:53 +04:00
|
|
|
} else {
|
2014-06-22 05:00:50 +04:00
|
|
|
col = rgb_to_pixel32(c6_to_8(s->palette[v]),
|
|
|
|
c6_to_8(s->palette[v + 1]),
|
|
|
|
c6_to_8(s->palette[v + 2]));
|
2006-09-22 01:46:53 +04:00
|
|
|
}
|
2003-08-05 03:30:47 +04:00
|
|
|
if (col != palette[i]) {
|
|
|
|
full_update = 1;
|
|
|
|
palette[i] = col;
|
|
|
|
}
|
2003-08-09 03:50:57 +04:00
|
|
|
v += 3;
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
|
|
|
return full_update;
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
static void vga_get_offsets(VGACommonState *s,
|
2007-09-17 01:08:06 +04:00
|
|
|
uint32_t *pline_offset,
|
2006-08-18 13:32:04 +04:00
|
|
|
uint32_t *pstart_addr,
|
|
|
|
uint32_t *pline_compare)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
2006-08-18 13:32:04 +04:00
|
|
|
uint32_t start_addr, line_offset, line_compare;
|
2012-10-15 10:02:57 +04:00
|
|
|
|
2016-04-26 15:11:34 +03:00
|
|
|
if (vbe_enabled(s)) {
|
2004-02-06 22:47:52 +03:00
|
|
|
line_offset = s->vbe_line_offset;
|
|
|
|
start_addr = s->vbe_start_addr;
|
2006-08-18 13:32:04 +04:00
|
|
|
line_compare = 65535;
|
2012-10-15 10:02:57 +04:00
|
|
|
} else {
|
2004-02-06 22:47:52 +03:00
|
|
|
/* compute line_offset in bytes */
|
2012-01-29 21:02:07 +04:00
|
|
|
line_offset = s->cr[VGA_CRTC_OFFSET];
|
2004-02-06 22:47:52 +03:00
|
|
|
line_offset <<= 3;
|
2005-04-23 22:43:45 +04:00
|
|
|
|
2004-02-06 22:47:52 +03:00
|
|
|
/* starting address */
|
2012-01-29 21:02:07 +04:00
|
|
|
start_addr = s->cr[VGA_CRTC_START_LO] |
|
|
|
|
(s->cr[VGA_CRTC_START_HI] << 8);
|
2006-08-18 13:32:04 +04:00
|
|
|
|
|
|
|
/* line compare */
|
2012-01-29 21:02:07 +04:00
|
|
|
line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
|
|
|
|
((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
|
|
|
|
((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
|
2004-02-06 22:47:52 +03:00
|
|
|
}
|
2004-06-05 14:30:49 +04:00
|
|
|
*pline_offset = line_offset;
|
|
|
|
*pstart_addr = start_addr;
|
2006-08-18 13:32:04 +04:00
|
|
|
*pline_compare = line_compare;
|
2004-06-05 14:30:49 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* update start_addr and line_offset. Return TRUE if modified */
|
2009-08-31 18:07:24 +04:00
|
|
|
static int update_basic_params(VGACommonState *s)
|
2004-06-05 14:30:49 +04:00
|
|
|
{
|
|
|
|
int full_update;
|
|
|
|
uint32_t start_addr, line_offset, line_compare;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2004-06-05 14:30:49 +04:00
|
|
|
full_update = 0;
|
|
|
|
|
2006-08-18 13:32:04 +04:00
|
|
|
s->get_offsets(s, &line_offset, &start_addr, &line_compare);
|
2003-08-05 03:30:47 +04:00
|
|
|
|
|
|
|
if (line_offset != s->line_offset ||
|
|
|
|
start_addr != s->start_addr ||
|
|
|
|
line_compare != s->line_compare) {
|
|
|
|
s->line_offset = line_offset;
|
|
|
|
s->start_addr = start_addr;
|
|
|
|
s->line_compare = line_compare;
|
|
|
|
full_update = 1;
|
|
|
|
}
|
|
|
|
return full_update;
|
|
|
|
}
|
|
|
|
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2003-08-05 03:30:47 +04:00
|
|
|
static const uint8_t cursor_glyph[32 * 4] = {
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
|
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
2007-09-17 12:09:54 +04:00
|
|
|
};
|
2003-08-05 03:30:47 +04:00
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
|
2009-01-04 13:56:46 +03:00
|
|
|
int *pcwidth, int *pcheight)
|
|
|
|
{
|
|
|
|
int width, cwidth, height, cheight;
|
|
|
|
|
|
|
|
/* total width & height */
|
2012-01-29 21:02:07 +04:00
|
|
|
cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
|
2009-01-04 13:56:46 +03:00
|
|
|
cwidth = 8;
|
2016-05-17 11:54:54 +03:00
|
|
|
if (!(sr(s, VGA_SEQ_CLOCK_MODE) & VGA_SR01_CHAR_CLK_8DOTS)) {
|
2009-01-04 13:56:46 +03:00
|
|
|
cwidth = 9;
|
2012-01-29 21:02:07 +04:00
|
|
|
}
|
2016-05-17 11:54:54 +03:00
|
|
|
if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) {
|
2009-01-04 13:56:46 +03:00
|
|
|
cwidth = 16; /* NOTE: no 18 pixel wide */
|
2012-01-29 21:02:07 +04:00
|
|
|
}
|
|
|
|
width = (s->cr[VGA_CRTC_H_DISP] + 1);
|
|
|
|
if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
|
2009-01-04 13:56:46 +03:00
|
|
|
/* ugly hack for CGA 160x100x16 - explain me the logic */
|
|
|
|
height = 100;
|
|
|
|
} else {
|
2012-01-29 21:02:07 +04:00
|
|
|
height = s->cr[VGA_CRTC_V_DISP_END] |
|
|
|
|
((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
|
|
|
|
((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
|
2009-01-04 13:56:46 +03:00
|
|
|
height = (height + 1) / cheight;
|
|
|
|
}
|
|
|
|
|
|
|
|
*pwidth = width;
|
|
|
|
*pheight = height;
|
|
|
|
*pcwidth = cwidth;
|
|
|
|
*pcheight = cheight;
|
|
|
|
}
|
|
|
|
|
2007-09-17 01:08:06 +04:00
|
|
|
/*
|
|
|
|
* Text mode update
|
2003-08-05 03:30:47 +04:00
|
|
|
* Missing:
|
|
|
|
* - double scan
|
2007-09-17 01:08:06 +04:00
|
|
|
* - double width
|
2003-08-05 03:30:47 +04:00
|
|
|
* - underline
|
|
|
|
* - flashing
|
|
|
|
*/
|
2009-08-31 18:07:24 +04:00
|
|
|
static void vga_draw_text(VGACommonState *s, int full_update)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
2013-03-05 18:24:14 +04:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s->con);
|
2003-08-05 03:30:47 +04:00
|
|
|
int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
|
2009-11-06 16:08:26 +03:00
|
|
|
int cx_min, cx_max, linesize, x_incr, line, line1;
|
2003-08-05 03:30:47 +04:00
|
|
|
uint32_t offset, fgcol, bgcol, v, cursor_offset;
|
2009-11-06 03:46:12 +03:00
|
|
|
uint8_t *d1, *d, *src, *dest, *cursor_ptr;
|
2003-08-05 03:30:47 +04:00
|
|
|
const uint8_t *font_ptr, *font_base[2];
|
2014-06-21 09:39:31 +04:00
|
|
|
int dup9, line_offset;
|
2003-08-05 03:30:47 +04:00
|
|
|
uint32_t *palette;
|
|
|
|
uint32_t *ch_attr_ptr;
|
2013-08-21 19:03:08 +04:00
|
|
|
int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
|
2003-08-05 03:30:47 +04:00
|
|
|
|
|
|
|
/* compute font data address (in plane 2) */
|
2016-05-17 11:54:54 +03:00
|
|
|
v = sr(s, VGA_SEQ_CHARACTER_MAP);
|
2004-05-20 16:46:38 +04:00
|
|
|
offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
|
2003-08-05 03:30:47 +04:00
|
|
|
if (offset != s->font_offsets[0]) {
|
|
|
|
s->font_offsets[0] = offset;
|
|
|
|
full_update = 1;
|
|
|
|
}
|
|
|
|
font_base[0] = s->vram_ptr + offset;
|
|
|
|
|
2004-05-20 16:46:38 +04:00
|
|
|
offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
|
2003-08-05 03:30:47 +04:00
|
|
|
font_base[1] = s->vram_ptr + offset;
|
|
|
|
if (offset != s->font_offsets[1]) {
|
|
|
|
s->font_offsets[1] = offset;
|
|
|
|
full_update = 1;
|
|
|
|
}
|
2014-06-11 14:19:25 +04:00
|
|
|
if (s->plane_updated & (1 << 2) || s->has_chain4_alias) {
|
2004-11-14 20:52:01 +03:00
|
|
|
/* if the plane 2 was modified since the last display, it
|
|
|
|
indicates the font may have been modified */
|
|
|
|
s->plane_updated = 0;
|
|
|
|
full_update = 1;
|
|
|
|
}
|
2009-04-08 00:55:29 +04:00
|
|
|
full_update |= update_basic_params(s);
|
2003-08-05 03:30:47 +04:00
|
|
|
|
|
|
|
line_offset = s->line_offset;
|
|
|
|
|
2009-01-04 13:56:46 +03:00
|
|
|
vga_get_text_resolution(s, &width, &height, &cw, &cheight);
|
2012-04-28 23:16:21 +04:00
|
|
|
if ((height * width) <= 1) {
|
|
|
|
/* better than nothing: exit if transient size is too small */
|
|
|
|
return;
|
|
|
|
}
|
2004-04-16 02:35:16 +04:00
|
|
|
if ((height * width) > CH_ATTR_SIZE) {
|
|
|
|
/* better than nothing: exit if transient size is too big */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-04-08 00:55:29 +04:00
|
|
|
if (width != s->last_width || height != s->last_height ||
|
|
|
|
cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
|
|
|
|
s->last_scr_width = width * cw;
|
|
|
|
s->last_scr_height = height * cheight;
|
2013-03-05 18:24:14 +04:00
|
|
|
qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
|
|
|
|
surface = qemu_console_surface(s->con);
|
|
|
|
dpy_text_resize(s->con, width, height);
|
2009-04-08 00:55:29 +04:00
|
|
|
s->last_depth = 0;
|
|
|
|
s->last_width = width;
|
|
|
|
s->last_height = height;
|
|
|
|
s->last_ch = cheight;
|
|
|
|
s->last_cw = cw;
|
|
|
|
full_update = 1;
|
|
|
|
}
|
2009-01-16 01:14:11 +03:00
|
|
|
full_update |= update_palette16(s);
|
|
|
|
palette = s->last_palette;
|
2013-03-05 18:24:14 +04:00
|
|
|
x_incr = cw * surface_bytes_per_pixel(surface);
|
2009-01-16 01:14:11 +03:00
|
|
|
|
2012-10-09 19:10:13 +04:00
|
|
|
if (full_update) {
|
|
|
|
s->full_update_text = 1;
|
|
|
|
}
|
|
|
|
if (s->full_update_gfx) {
|
|
|
|
s->full_update_gfx = 0;
|
|
|
|
full_update |= 1;
|
|
|
|
}
|
|
|
|
|
2012-01-29 21:02:07 +04:00
|
|
|
cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
|
|
|
|
s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
|
2003-08-05 03:30:47 +04:00
|
|
|
if (cursor_offset != s->cursor_offset ||
|
2012-01-29 21:02:07 +04:00
|
|
|
s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
|
|
|
|
s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
|
2003-08-05 03:30:47 +04:00
|
|
|
/* if the cursor position changed, we update the old and new
|
|
|
|
chars */
|
|
|
|
if (s->cursor_offset < CH_ATTR_SIZE)
|
|
|
|
s->last_ch_attr[s->cursor_offset] = -1;
|
|
|
|
if (cursor_offset < CH_ATTR_SIZE)
|
|
|
|
s->last_ch_attr[cursor_offset] = -1;
|
|
|
|
s->cursor_offset = cursor_offset;
|
2012-01-29 21:02:07 +04:00
|
|
|
s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
|
|
|
|
s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
2003-08-06 03:06:22 +04:00
|
|
|
cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
|
2012-07-04 21:49:54 +04:00
|
|
|
if (now >= s->cursor_blink_time) {
|
|
|
|
s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
|
|
|
|
s->cursor_visible_phase = !s->cursor_visible_phase;
|
|
|
|
}
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2013-03-05 18:24:14 +04:00
|
|
|
dest = surface_data(surface);
|
|
|
|
linesize = surface_stride(surface);
|
2003-08-05 03:30:47 +04:00
|
|
|
ch_attr_ptr = s->last_ch_attr;
|
2009-11-06 03:46:12 +03:00
|
|
|
line = 0;
|
|
|
|
offset = s->start_addr * 4;
|
2003-08-05 03:30:47 +04:00
|
|
|
for(cy = 0; cy < height; cy++) {
|
|
|
|
d1 = dest;
|
2009-11-06 03:46:12 +03:00
|
|
|
src = s->vram_ptr + offset;
|
2003-08-05 03:30:47 +04:00
|
|
|
cx_min = width;
|
|
|
|
cx_max = -1;
|
|
|
|
for(cx = 0; cx < width; cx++) {
|
|
|
|
ch_attr = *(uint16_t *)src;
|
2012-07-04 21:49:54 +04:00
|
|
|
if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
|
2003-08-05 03:30:47 +04:00
|
|
|
if (cx < cx_min)
|
|
|
|
cx_min = cx;
|
|
|
|
if (cx > cx_max)
|
|
|
|
cx_max = cx;
|
|
|
|
*ch_attr_ptr = ch_attr;
|
2009-07-27 18:13:06 +04:00
|
|
|
#ifdef HOST_WORDS_BIGENDIAN
|
2003-08-05 03:30:47 +04:00
|
|
|
ch = ch_attr >> 8;
|
|
|
|
cattr = ch_attr & 0xff;
|
|
|
|
#else
|
|
|
|
ch = ch_attr & 0xff;
|
|
|
|
cattr = ch_attr >> 8;
|
|
|
|
#endif
|
|
|
|
font_ptr = font_base[(cattr >> 3) & 1];
|
|
|
|
font_ptr += 32 * 4 * ch;
|
|
|
|
bgcol = palette[cattr >> 4];
|
|
|
|
fgcol = palette[cattr & 0x0f];
|
2014-06-21 09:39:31 +04:00
|
|
|
if (cw == 16) {
|
2014-06-21 09:51:52 +04:00
|
|
|
vga_draw_glyph16(d1, linesize,
|
|
|
|
font_ptr, cheight, fgcol, bgcol);
|
2014-06-21 09:39:31 +04:00
|
|
|
} else if (cw != 9) {
|
2014-06-21 09:51:52 +04:00
|
|
|
vga_draw_glyph8(d1, linesize,
|
|
|
|
font_ptr, cheight, fgcol, bgcol);
|
2003-08-05 03:30:47 +04:00
|
|
|
} else {
|
|
|
|
dup9 = 0;
|
2012-01-29 21:02:07 +04:00
|
|
|
if (ch >= 0xb0 && ch <= 0xdf &&
|
|
|
|
(s->ar[VGA_ATC_MODE] & 0x04)) {
|
2003-08-05 03:30:47 +04:00
|
|
|
dup9 = 1;
|
2012-01-29 21:02:07 +04:00
|
|
|
}
|
2014-06-21 09:51:52 +04:00
|
|
|
vga_draw_glyph9(d1, linesize,
|
|
|
|
font_ptr, cheight, fgcol, bgcol, dup9);
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
|
|
|
if (src == cursor_ptr &&
|
2012-07-04 21:49:54 +04:00
|
|
|
!(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
|
|
|
|
s->cursor_visible_phase) {
|
2003-08-05 03:30:47 +04:00
|
|
|
int line_start, line_last, h;
|
|
|
|
/* draw the cursor */
|
2012-01-29 21:02:07 +04:00
|
|
|
line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
|
|
|
|
line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
|
2003-08-05 03:30:47 +04:00
|
|
|
/* XXX: check that */
|
|
|
|
if (line_last > cheight - 1)
|
|
|
|
line_last = cheight - 1;
|
|
|
|
if (line_last >= line_start && line_start < cheight) {
|
|
|
|
h = line_last - line_start + 1;
|
|
|
|
d = d1 + linesize * line_start;
|
2014-06-21 09:39:31 +04:00
|
|
|
if (cw == 16) {
|
2014-06-21 09:51:52 +04:00
|
|
|
vga_draw_glyph16(d, linesize,
|
|
|
|
cursor_glyph, h, fgcol, bgcol);
|
2014-06-21 09:39:31 +04:00
|
|
|
} else if (cw != 9) {
|
2014-06-21 09:51:52 +04:00
|
|
|
vga_draw_glyph8(d, linesize,
|
|
|
|
cursor_glyph, h, fgcol, bgcol);
|
2003-08-05 03:30:47 +04:00
|
|
|
} else {
|
2014-06-21 09:51:52 +04:00
|
|
|
vga_draw_glyph9(d, linesize,
|
|
|
|
cursor_glyph, h, fgcol, bgcol, 1);
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
d1 += x_incr;
|
|
|
|
src += 4;
|
|
|
|
ch_attr_ptr++;
|
|
|
|
}
|
|
|
|
if (cx_max != -1) {
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_gfx_update(s->con, cx_min * cw, cy * cheight,
|
2012-09-28 17:02:08 +04:00
|
|
|
(cx_max - cx_min + 1) * cw, cheight);
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
|
|
|
dest += linesize * cheight;
|
2009-11-06 16:08:26 +03:00
|
|
|
line1 = line + cheight;
|
|
|
|
offset += line_offset;
|
|
|
|
if (line < s->line_compare && line1 >= s->line_compare) {
|
2009-11-06 03:46:12 +03:00
|
|
|
offset = 0;
|
|
|
|
}
|
2009-11-06 16:08:26 +03:00
|
|
|
line = line1;
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2003-08-09 03:50:57 +04:00
|
|
|
enum {
|
|
|
|
VGA_DRAW_LINE2,
|
|
|
|
VGA_DRAW_LINE2D2,
|
|
|
|
VGA_DRAW_LINE4,
|
|
|
|
VGA_DRAW_LINE4D2,
|
|
|
|
VGA_DRAW_LINE8D2,
|
|
|
|
VGA_DRAW_LINE8,
|
2014-07-07 03:48:28 +04:00
|
|
|
VGA_DRAW_LINE15_LE,
|
|
|
|
VGA_DRAW_LINE16_LE,
|
|
|
|
VGA_DRAW_LINE24_LE,
|
|
|
|
VGA_DRAW_LINE32_LE,
|
|
|
|
VGA_DRAW_LINE15_BE,
|
|
|
|
VGA_DRAW_LINE16_BE,
|
|
|
|
VGA_DRAW_LINE24_BE,
|
|
|
|
VGA_DRAW_LINE32_BE,
|
2003-08-09 03:50:57 +04:00
|
|
|
VGA_DRAW_LINE_NB,
|
|
|
|
};
|
|
|
|
|
2014-06-21 09:39:31 +04:00
|
|
|
static vga_draw_line_func * const vga_draw_line_table[VGA_DRAW_LINE_NB] = {
|
2014-06-21 09:51:52 +04:00
|
|
|
vga_draw_line2,
|
|
|
|
vga_draw_line2d2,
|
|
|
|
vga_draw_line4,
|
|
|
|
vga_draw_line4d2,
|
|
|
|
vga_draw_line8d2,
|
|
|
|
vga_draw_line8,
|
2014-07-07 03:48:28 +04:00
|
|
|
vga_draw_line15_le,
|
|
|
|
vga_draw_line16_le,
|
|
|
|
vga_draw_line24_le,
|
|
|
|
vga_draw_line32_le,
|
|
|
|
vga_draw_line15_be,
|
|
|
|
vga_draw_line16_be,
|
|
|
|
vga_draw_line24_be,
|
|
|
|
vga_draw_line32_be,
|
2006-05-11 02:17:36 +04:00
|
|
|
};
|
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
static int vga_get_bpp(VGACommonState *s)
|
2004-06-05 14:30:49 +04:00
|
|
|
{
|
|
|
|
int ret;
|
2012-10-15 10:02:57 +04:00
|
|
|
|
2016-04-26 15:11:34 +03:00
|
|
|
if (vbe_enabled(s)) {
|
2004-06-05 14:30:49 +04:00
|
|
|
ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
|
2012-10-15 10:02:57 +04:00
|
|
|
} else {
|
2004-06-05 14:30:49 +04:00
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
|
2004-06-08 04:59:19 +04:00
|
|
|
{
|
|
|
|
int width, height;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2016-04-26 15:11:34 +03:00
|
|
|
if (vbe_enabled(s)) {
|
2006-06-13 20:37:40 +04:00
|
|
|
width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
|
|
|
|
height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
|
2012-10-15 10:02:57 +04:00
|
|
|
} else {
|
2012-01-29 21:02:07 +04:00
|
|
|
width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
|
|
|
|
height = s->cr[VGA_CRTC_V_DISP_END] |
|
|
|
|
((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
|
|
|
|
((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
|
2006-06-13 20:37:40 +04:00
|
|
|
height = (height + 1);
|
|
|
|
}
|
2004-06-08 04:59:19 +04:00
|
|
|
*pwidth = width;
|
|
|
|
*pheight = height;
|
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
|
2004-06-06 19:17:19 +04:00
|
|
|
{
|
|
|
|
int y;
|
|
|
|
if (y1 >= VGA_MAX_HEIGHT)
|
|
|
|
return;
|
|
|
|
if (y2 >= VGA_MAX_HEIGHT)
|
|
|
|
y2 = VGA_MAX_HEIGHT;
|
|
|
|
for(y = y1; y < y2; y++) {
|
|
|
|
s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-04-21 12:16:26 +03:00
|
|
|
static bool vga_scanline_invalidated(VGACommonState *s, int y)
|
|
|
|
{
|
|
|
|
if (y >= VGA_MAX_HEIGHT) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return s->invalidated_y_table[y >> 5] & (1 << (y & 0x1f));
|
|
|
|
}
|
|
|
|
|
2012-11-03 15:47:08 +04:00
|
|
|
void vga_sync_dirty_bitmap(VGACommonState *s)
|
2008-11-24 23:21:41 +03:00
|
|
|
{
|
2011-08-08 17:08:57 +04:00
|
|
|
memory_region_sync_dirty_bitmap(&s->vram);
|
2008-11-24 23:21:41 +03:00
|
|
|
}
|
|
|
|
|
2009-09-21 16:35:18 +04:00
|
|
|
void vga_dirty_log_start(VGACommonState *s)
|
|
|
|
{
|
2011-08-08 17:08:57 +04:00
|
|
|
memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
|
2009-12-18 01:08:10 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void vga_dirty_log_stop(VGACommonState *s)
|
|
|
|
{
|
2011-08-08 17:08:57 +04:00
|
|
|
memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
|
2009-12-18 01:08:10 +03:00
|
|
|
}
|
|
|
|
|
2009-04-08 00:55:29 +04:00
|
|
|
/*
|
|
|
|
* graphic modes
|
|
|
|
*/
|
2009-08-31 18:07:24 +04:00
|
|
|
static void vga_draw_graphic(VGACommonState *s, int full_update)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
2013-03-05 18:24:14 +04:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s->con);
|
2009-04-27 21:57:12 +04:00
|
|
|
int y1, y, update, linesize, y_start, double_scan, mask, depth;
|
|
|
|
int width, height, shift_control, line_offset, bwidth, bits;
|
2017-04-21 12:16:27 +03:00
|
|
|
ram_addr_t page0, page1;
|
|
|
|
DirtyBitmapSnapshot *snap = NULL;
|
2003-10-01 01:29:03 +04:00
|
|
|
int disp_width, multi_scan, multi_run;
|
2009-04-08 00:55:29 +04:00
|
|
|
uint8_t *d;
|
|
|
|
uint32_t v, addr1, addr;
|
2014-07-07 03:50:12 +04:00
|
|
|
vga_draw_line_func *vga_draw_line = NULL;
|
2014-07-07 04:17:44 +04:00
|
|
|
bool share_surface;
|
2014-07-07 10:39:05 +04:00
|
|
|
pixman_format_code_t format;
|
2014-07-07 03:50:12 +04:00
|
|
|
#ifdef HOST_WORDS_BIGENDIAN
|
|
|
|
bool byteswap = !s->big_endian_fb;
|
2014-07-07 03:48:28 +04:00
|
|
|
#else
|
2014-07-07 03:50:12 +04:00
|
|
|
bool byteswap = s->big_endian_fb;
|
2013-02-20 12:37:12 +04:00
|
|
|
#endif
|
2009-04-08 00:55:29 +04:00
|
|
|
|
|
|
|
full_update |= update_basic_params(s);
|
|
|
|
|
2004-06-08 04:59:19 +04:00
|
|
|
s->get_resolution(s, &width, &height);
|
2003-08-09 03:50:57 +04:00
|
|
|
disp_width = width;
|
2004-05-27 02:58:01 +04:00
|
|
|
|
2012-01-29 21:02:07 +04:00
|
|
|
shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
|
|
|
|
double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
|
2009-04-08 00:55:29 +04:00
|
|
|
if (shift_control != 1) {
|
2012-01-29 21:02:07 +04:00
|
|
|
multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
|
|
|
|
- 1;
|
2009-04-08 00:55:29 +04:00
|
|
|
} else {
|
|
|
|
/* in CGA modes, multi_scan is ignored */
|
|
|
|
/* XXX: is it correct ? */
|
|
|
|
multi_scan = double_scan;
|
|
|
|
}
|
|
|
|
multi_run = multi_scan;
|
2003-08-09 03:50:57 +04:00
|
|
|
if (shift_control != s->shift_control ||
|
|
|
|
double_scan != s->double_scan) {
|
2009-04-08 00:55:29 +04:00
|
|
|
full_update = 1;
|
2003-08-05 03:30:47 +04:00
|
|
|
s->shift_control = shift_control;
|
2003-08-09 03:50:57 +04:00
|
|
|
s->double_scan = double_scan;
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2009-03-17 19:05:50 +03:00
|
|
|
if (shift_control == 0) {
|
2016-05-17 11:54:54 +03:00
|
|
|
if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
|
2009-03-17 19:05:50 +03:00
|
|
|
disp_width <<= 1;
|
|
|
|
}
|
|
|
|
} else if (shift_control == 1) {
|
2016-05-17 11:54:54 +03:00
|
|
|
if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
|
2009-03-17 19:05:50 +03:00
|
|
|
disp_width <<= 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-04-08 00:55:29 +04:00
|
|
|
depth = s->get_bpp(s);
|
2014-07-07 04:17:44 +04:00
|
|
|
|
2014-07-07 10:39:05 +04:00
|
|
|
/*
|
|
|
|
* Check whether we can share the surface with the backend
|
|
|
|
* or whether we need a shadow surface. We share native
|
|
|
|
* endian surfaces for 15bpp and above and byteswapped
|
|
|
|
* surfaces for 24bpp and above.
|
|
|
|
*/
|
|
|
|
format = qemu_default_pixman_format(depth, !byteswap);
|
|
|
|
if (format) {
|
|
|
|
share_surface = dpy_gfx_check_format(s->con, format)
|
|
|
|
&& !s->force_shadow;
|
|
|
|
} else {
|
|
|
|
share_surface = false;
|
|
|
|
}
|
2009-01-16 22:45:28 +03:00
|
|
|
if (s->line_offset != s->last_line_offset ||
|
|
|
|
disp_width != s->last_width ||
|
|
|
|
height != s->last_height ||
|
2014-06-23 07:57:41 +04:00
|
|
|
s->last_depth != depth ||
|
2014-07-07 04:17:44 +04:00
|
|
|
s->last_byteswap != byteswap ||
|
|
|
|
share_surface != is_buffer_shared(surface)) {
|
|
|
|
if (share_surface) {
|
2013-02-28 13:48:02 +04:00
|
|
|
surface = qemu_create_displaysurface_from(disp_width,
|
2014-06-18 13:03:15 +04:00
|
|
|
height, format, s->line_offset,
|
|
|
|
s->vram_ptr + (s->start_addr * 4));
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_gfx_replace_surface(s->con, surface);
|
2009-01-16 22:45:28 +03:00
|
|
|
} else {
|
2013-03-05 18:24:14 +04:00
|
|
|
qemu_console_resize(s->con, disp_width, height);
|
|
|
|
surface = qemu_console_surface(s->con);
|
2009-01-16 22:45:28 +03:00
|
|
|
}
|
|
|
|
s->last_scr_width = disp_width;
|
|
|
|
s->last_scr_height = height;
|
|
|
|
s->last_width = disp_width;
|
|
|
|
s->last_height = height;
|
|
|
|
s->last_line_offset = s->line_offset;
|
|
|
|
s->last_depth = depth;
|
2014-06-23 07:57:41 +04:00
|
|
|
s->last_byteswap = byteswap;
|
2009-04-08 00:55:29 +04:00
|
|
|
full_update = 1;
|
2013-03-05 18:24:14 +04:00
|
|
|
} else if (is_buffer_shared(surface) &&
|
|
|
|
(full_update || surface_data(surface) != s->vram_ptr
|
2012-10-10 15:05:05 +04:00
|
|
|
+ (s->start_addr * 4))) {
|
2014-06-18 13:03:15 +04:00
|
|
|
pixman_format_code_t format =
|
|
|
|
qemu_default_pixman_format(depth, !byteswap);
|
2013-02-28 13:48:02 +04:00
|
|
|
surface = qemu_create_displaysurface_from(disp_width,
|
2014-06-18 13:03:15 +04:00
|
|
|
height, format, s->line_offset,
|
|
|
|
s->vram_ptr + (s->start_addr * 4));
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_gfx_replace_surface(s->con, surface);
|
2009-01-16 22:45:28 +03:00
|
|
|
}
|
|
|
|
|
2009-04-08 00:55:29 +04:00
|
|
|
if (shift_control == 0) {
|
2003-08-09 03:50:57 +04:00
|
|
|
full_update |= update_palette16(s);
|
2016-05-17 11:54:54 +03:00
|
|
|
if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
|
2003-08-09 03:50:57 +04:00
|
|
|
v = VGA_DRAW_LINE4D2;
|
|
|
|
} else {
|
|
|
|
v = VGA_DRAW_LINE4;
|
|
|
|
}
|
2008-05-04 17:11:53 +04:00
|
|
|
bits = 4;
|
2009-04-08 00:55:29 +04:00
|
|
|
} else if (shift_control == 1) {
|
2003-08-09 03:50:57 +04:00
|
|
|
full_update |= update_palette16(s);
|
2016-05-17 11:54:54 +03:00
|
|
|
if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) {
|
2003-08-09 03:50:57 +04:00
|
|
|
v = VGA_DRAW_LINE2D2;
|
|
|
|
} else {
|
|
|
|
v = VGA_DRAW_LINE2;
|
|
|
|
}
|
2008-05-04 17:11:53 +04:00
|
|
|
bits = 4;
|
2003-08-09 03:50:57 +04:00
|
|
|
} else {
|
2004-06-05 14:30:49 +04:00
|
|
|
switch(s->get_bpp(s)) {
|
|
|
|
default:
|
|
|
|
case 0:
|
2004-02-06 22:47:52 +03:00
|
|
|
full_update |= update_palette256(s);
|
|
|
|
v = VGA_DRAW_LINE8D2;
|
2008-05-04 17:11:53 +04:00
|
|
|
bits = 4;
|
2004-06-05 14:30:49 +04:00
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
full_update |= update_palette256(s);
|
|
|
|
v = VGA_DRAW_LINE8;
|
2008-05-04 17:11:53 +04:00
|
|
|
bits = 8;
|
2004-06-05 14:30:49 +04:00
|
|
|
break;
|
|
|
|
case 15:
|
2014-07-07 03:50:12 +04:00
|
|
|
v = s->big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_LE;
|
2008-05-04 17:11:53 +04:00
|
|
|
bits = 16;
|
2004-06-05 14:30:49 +04:00
|
|
|
break;
|
|
|
|
case 16:
|
2014-07-07 03:50:12 +04:00
|
|
|
v = s->big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_LE;
|
2008-05-04 17:11:53 +04:00
|
|
|
bits = 16;
|
2004-06-05 14:30:49 +04:00
|
|
|
break;
|
|
|
|
case 24:
|
2014-07-07 03:50:12 +04:00
|
|
|
v = s->big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_LE;
|
2008-05-04 17:11:53 +04:00
|
|
|
bits = 24;
|
2004-06-05 14:30:49 +04:00
|
|
|
break;
|
|
|
|
case 32:
|
2014-07-07 03:50:12 +04:00
|
|
|
v = s->big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_LE;
|
2008-05-04 17:11:53 +04:00
|
|
|
bits = 32;
|
2004-06-05 14:30:49 +04:00
|
|
|
break;
|
2004-02-06 22:47:52 +03:00
|
|
|
}
|
2003-08-09 03:50:57 +04:00
|
|
|
}
|
2014-06-21 09:39:31 +04:00
|
|
|
vga_draw_line = vga_draw_line_table[v];
|
2003-08-09 03:50:57 +04:00
|
|
|
|
2013-03-05 18:24:14 +04:00
|
|
|
if (!is_buffer_shared(surface) && s->cursor_invalidate) {
|
2004-06-06 19:17:19 +04:00
|
|
|
s->cursor_invalidate(s);
|
2013-03-05 18:24:14 +04:00
|
|
|
}
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2003-08-05 03:30:47 +04:00
|
|
|
line_offset = s->line_offset;
|
2003-08-09 03:50:57 +04:00
|
|
|
#if 0
|
2004-11-08 01:57:20 +03:00
|
|
|
printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
|
2012-01-29 21:02:07 +04:00
|
|
|
width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
|
2016-05-17 11:54:54 +03:00
|
|
|
s->line_compare, sr(s, VGA_SEQ_CLOCK_MODE));
|
2003-08-09 03:50:57 +04:00
|
|
|
#endif
|
2003-08-05 03:30:47 +04:00
|
|
|
addr1 = (s->start_addr * 4);
|
2008-05-04 17:11:53 +04:00
|
|
|
bwidth = (width * bits + 7) / 8;
|
2003-08-06 03:06:22 +04:00
|
|
|
y_start = -1;
|
2013-03-05 18:24:14 +04:00
|
|
|
d = surface_data(surface);
|
|
|
|
linesize = surface_stride(surface);
|
2003-08-09 03:50:57 +04:00
|
|
|
y1 = 0;
|
2017-04-21 12:16:27 +03:00
|
|
|
|
|
|
|
if (!full_update) {
|
|
|
|
vga_sync_dirty_bitmap(s);
|
|
|
|
snap = memory_region_snapshot_and_clear_dirty(&s->vram, addr1,
|
2017-05-09 13:48:39 +03:00
|
|
|
line_offset * height,
|
2017-04-21 12:16:27 +03:00
|
|
|
DIRTY_MEMORY_VGA);
|
|
|
|
}
|
|
|
|
|
2003-08-05 03:30:47 +04:00
|
|
|
for(y = 0; y < height; y++) {
|
|
|
|
addr = addr1;
|
2012-01-29 21:02:07 +04:00
|
|
|
if (!(s->cr[VGA_CRTC_MODE] & 1)) {
|
2003-08-09 03:50:57 +04:00
|
|
|
int shift;
|
2003-08-05 03:30:47 +04:00
|
|
|
/* CGA compatibility handling */
|
2012-01-29 21:02:07 +04:00
|
|
|
shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
|
2003-08-09 03:50:57 +04:00
|
|
|
addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
2012-01-29 21:02:07 +04:00
|
|
|
if (!(s->cr[VGA_CRTC_MODE] & 2)) {
|
2003-08-09 03:50:57 +04:00
|
|
|
addr = (addr & ~0x8000) | ((y1 & 2) << 14);
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
2012-02-07 19:03:24 +04:00
|
|
|
update = full_update;
|
2012-01-22 20:38:21 +04:00
|
|
|
page0 = addr;
|
|
|
|
page1 = addr + bwidth - 1;
|
2017-04-21 12:16:27 +03:00
|
|
|
if (full_update) {
|
|
|
|
update = 1;
|
|
|
|
} else {
|
|
|
|
update = memory_region_snapshot_get_dirty(&s->vram, snap,
|
|
|
|
page0, page1 - page0);
|
|
|
|
}
|
2017-04-21 12:16:26 +03:00
|
|
|
/* explicit invalidation for the hardware cursor (cirrus only) */
|
|
|
|
update |= vga_scanline_invalidated(s, y);
|
2003-08-05 03:30:47 +04:00
|
|
|
if (update) {
|
2003-08-06 03:06:22 +04:00
|
|
|
if (y_start < 0)
|
|
|
|
y_start = y;
|
2013-03-05 18:24:14 +04:00
|
|
|
if (!(is_buffer_shared(surface))) {
|
2009-01-16 01:14:11 +03:00
|
|
|
vga_draw_line(s, d, s->vram_ptr + addr, width);
|
|
|
|
if (s->cursor_draw_line)
|
|
|
|
s->cursor_draw_line(s, d, y);
|
|
|
|
}
|
2003-08-06 03:06:22 +04:00
|
|
|
} else {
|
|
|
|
if (y_start >= 0) {
|
|
|
|
/* flush to display */
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_gfx_update(s->con, 0, y_start,
|
2012-09-28 17:02:08 +04:00
|
|
|
disp_width, y - y_start);
|
2003-08-06 03:06:22 +04:00
|
|
|
y_start = -1;
|
|
|
|
}
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
2003-10-01 01:29:03 +04:00
|
|
|
if (!multi_run) {
|
2012-01-29 21:02:07 +04:00
|
|
|
mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
|
2004-11-08 01:57:20 +03:00
|
|
|
if ((y1 & mask) == mask)
|
|
|
|
addr1 += line_offset;
|
|
|
|
y1++;
|
2009-04-08 00:55:29 +04:00
|
|
|
multi_run = multi_scan;
|
2003-10-01 01:29:03 +04:00
|
|
|
} else {
|
|
|
|
multi_run--;
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
2004-11-08 01:57:20 +03:00
|
|
|
/* line compare acts on the displayed lines */
|
|
|
|
if (y == s->line_compare)
|
|
|
|
addr1 = 0;
|
2003-08-05 03:30:47 +04:00
|
|
|
d += linesize;
|
|
|
|
}
|
2003-08-06 03:06:22 +04:00
|
|
|
if (y_start >= 0) {
|
|
|
|
/* flush to display */
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_gfx_update(s->con, 0, y_start,
|
2012-09-28 17:02:08 +04:00
|
|
|
disp_width, y - y_start);
|
2003-08-06 03:06:22 +04:00
|
|
|
}
|
2017-04-21 12:16:27 +03:00
|
|
|
g_free(snap);
|
2017-04-21 12:16:26 +03:00
|
|
|
memset(s->invalidated_y_table, 0, sizeof(s->invalidated_y_table));
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
|
|
|
|
2009-08-31 18:07:24 +04:00
|
|
|
static void vga_draw_blank(VGACommonState *s, int full_update)
|
2004-04-16 02:28:04 +04:00
|
|
|
{
|
2013-03-05 18:24:14 +04:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s->con);
|
2014-06-22 05:03:49 +04:00
|
|
|
int i, w;
|
2004-04-16 02:28:04 +04:00
|
|
|
uint8_t *d;
|
|
|
|
|
|
|
|
if (!full_update)
|
|
|
|
return;
|
|
|
|
if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
|
|
|
|
return;
|
2008-11-24 23:21:41 +03:00
|
|
|
|
2013-03-05 18:24:14 +04:00
|
|
|
w = s->last_scr_width * surface_bytes_per_pixel(surface);
|
|
|
|
d = surface_data(surface);
|
2004-04-16 02:28:04 +04:00
|
|
|
for(i = 0; i < s->last_scr_height; i++) {
|
2014-06-22 05:03:49 +04:00
|
|
|
memset(d, 0, w);
|
2013-03-05 18:24:14 +04:00
|
|
|
d += surface_stride(surface);
|
2004-04-16 02:28:04 +04:00
|
|
|
}
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_gfx_update(s->con, 0, 0,
|
2012-09-28 17:02:08 +04:00
|
|
|
s->last_scr_width, s->last_scr_height);
|
2004-04-16 02:28:04 +04:00
|
|
|
}
|
|
|
|
|
2009-04-08 00:55:29 +04:00
|
|
|
#define GMODE_TEXT 0
|
|
|
|
#define GMODE_GRAPH 1
|
|
|
|
#define GMODE_BLANK 2
|
|
|
|
|
2006-04-09 05:06:34 +04:00
|
|
|
static void vga_update_display(void *opaque)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
2009-08-31 18:07:24 +04:00
|
|
|
VGACommonState *s = opaque;
|
2013-03-05 18:24:14 +04:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s->con);
|
2009-04-08 00:55:29 +04:00
|
|
|
int full_update, graphic_mode;
|
2003-08-05 03:30:47 +04:00
|
|
|
|
2011-09-30 14:31:14 +04:00
|
|
|
qemu_flush_coalesced_mmio_buffer();
|
|
|
|
|
2013-03-05 18:24:14 +04:00
|
|
|
if (surface_bits_per_pixel(surface) == 0) {
|
2004-03-15 00:42:10 +03:00
|
|
|
/* nothing to do */
|
2004-03-18 02:17:16 +03:00
|
|
|
} else {
|
2009-11-27 20:42:26 +03:00
|
|
|
full_update = 0;
|
2012-08-27 18:33:20 +04:00
|
|
|
if (!(s->ar_index & 0x20)) {
|
2009-04-08 00:55:29 +04:00
|
|
|
graphic_mode = GMODE_BLANK;
|
|
|
|
} else {
|
2012-01-29 21:02:07 +04:00
|
|
|
graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
|
2009-04-08 00:55:29 +04:00
|
|
|
}
|
|
|
|
if (graphic_mode != s->graphic_mode) {
|
|
|
|
s->graphic_mode = graphic_mode;
|
2013-08-21 19:03:08 +04:00
|
|
|
s->cursor_blink_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
|
2009-04-08 00:55:29 +04:00
|
|
|
full_update = 1;
|
|
|
|
}
|
|
|
|
switch(graphic_mode) {
|
2004-04-16 02:28:04 +04:00
|
|
|
case GMODE_TEXT:
|
2003-08-05 03:30:47 +04:00
|
|
|
vga_draw_text(s, full_update);
|
2004-04-16 02:28:04 +04:00
|
|
|
break;
|
|
|
|
case GMODE_GRAPH:
|
|
|
|
vga_draw_graphic(s, full_update);
|
|
|
|
break;
|
|
|
|
case GMODE_BLANK:
|
|
|
|
default:
|
|
|
|
vga_draw_blank(s, full_update);
|
|
|
|
break;
|
|
|
|
}
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-06-08 04:59:19 +04:00
|
|
|
/* force a full display refresh */
|
2006-04-09 05:06:34 +04:00
|
|
|
static void vga_invalidate_display(void *opaque)
|
2004-06-08 04:59:19 +04:00
|
|
|
{
|
2009-08-31 18:07:24 +04:00
|
|
|
VGACommonState *s = opaque;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2009-11-27 20:42:26 +03:00
|
|
|
s->last_width = -1;
|
|
|
|
s->last_height = -1;
|
2004-06-08 04:59:19 +04:00
|
|
|
}
|
|
|
|
|
2009-08-24 20:42:45 +04:00
|
|
|
void vga_common_reset(VGACommonState *s)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
2008-12-28 21:27:10 +03:00
|
|
|
s->sr_index = 0;
|
|
|
|
memset(s->sr, '\0', sizeof(s->sr));
|
2016-05-17 11:54:54 +03:00
|
|
|
memset(s->sr_vbe, '\0', sizeof(s->sr_vbe));
|
2008-12-28 21:27:10 +03:00
|
|
|
s->gr_index = 0;
|
|
|
|
memset(s->gr, '\0', sizeof(s->gr));
|
|
|
|
s->ar_index = 0;
|
|
|
|
memset(s->ar, '\0', sizeof(s->ar));
|
|
|
|
s->ar_flip_flop = 0;
|
|
|
|
s->cr_index = 0;
|
|
|
|
memset(s->cr, '\0', sizeof(s->cr));
|
|
|
|
s->msr = 0;
|
|
|
|
s->fcr = 0;
|
|
|
|
s->st00 = 0;
|
|
|
|
s->st01 = 0;
|
|
|
|
s->dac_state = 0;
|
|
|
|
s->dac_sub_index = 0;
|
|
|
|
s->dac_read_index = 0;
|
|
|
|
s->dac_write_index = 0;
|
|
|
|
memset(s->dac_cache, '\0', sizeof(s->dac_cache));
|
|
|
|
s->dac_8bit = 0;
|
|
|
|
memset(s->palette, '\0', sizeof(s->palette));
|
|
|
|
s->bank_offset = 0;
|
|
|
|
s->vbe_index = 0;
|
|
|
|
memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
|
2010-03-25 13:38:52 +03:00
|
|
|
s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
|
2008-12-28 21:27:10 +03:00
|
|
|
s->vbe_start_addr = 0;
|
|
|
|
s->vbe_line_offset = 0;
|
|
|
|
s->vbe_bank_mask = (s->vram_size >> 16) - 1;
|
|
|
|
memset(s->font_offsets, '\0', sizeof(s->font_offsets));
|
2009-04-08 00:55:29 +04:00
|
|
|
s->graphic_mode = -1; /* force full update */
|
2008-12-28 21:27:10 +03:00
|
|
|
s->shift_control = 0;
|
|
|
|
s->double_scan = 0;
|
|
|
|
s->line_offset = 0;
|
|
|
|
s->line_compare = 0;
|
|
|
|
s->start_addr = 0;
|
|
|
|
s->plane_updated = 0;
|
|
|
|
s->last_cw = 0;
|
|
|
|
s->last_ch = 0;
|
|
|
|
s->last_width = 0;
|
|
|
|
s->last_height = 0;
|
|
|
|
s->last_scr_width = 0;
|
|
|
|
s->last_scr_height = 0;
|
|
|
|
s->cursor_start = 0;
|
|
|
|
s->cursor_end = 0;
|
|
|
|
s->cursor_offset = 0;
|
2014-06-23 07:57:41 +04:00
|
|
|
s->big_endian_fb = s->default_endian_fb;
|
2008-12-28 21:27:10 +03:00
|
|
|
memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
|
|
|
|
memset(s->last_palette, '\0', sizeof(s->last_palette));
|
|
|
|
memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
|
|
|
|
switch (vga_retrace_method) {
|
|
|
|
case VGA_RETRACE_DUMB:
|
|
|
|
break;
|
|
|
|
case VGA_RETRACE_PRECISE:
|
|
|
|
memset(&s->retrace_info, 0, sizeof (s->retrace_info));
|
|
|
|
break;
|
|
|
|
}
|
2011-08-22 21:12:12 +04:00
|
|
|
vga_update_memory_access(s);
|
2003-08-05 03:30:47 +04:00
|
|
|
}
|
|
|
|
|
2009-08-24 20:42:45 +04:00
|
|
|
static void vga_reset(void *opaque)
|
|
|
|
{
|
2009-08-31 18:07:24 +04:00
|
|
|
VGACommonState *s = opaque;
|
2009-08-24 20:42:45 +04:00
|
|
|
vga_common_reset(s);
|
|
|
|
}
|
|
|
|
|
2008-02-10 19:33:14 +03:00
|
|
|
#define TEXTMODE_X(x) ((x) % width)
|
|
|
|
#define TEXTMODE_Y(x) ((x) / width)
|
|
|
|
#define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
|
|
|
|
((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
|
|
|
|
/* relay text rendering to the display driver
|
|
|
|
* instead of doing a full vga_update_display() */
|
2009-10-02 01:12:16 +04:00
|
|
|
static void vga_update_text(void *opaque, console_ch_t *chardata)
|
2008-02-10 19:33:14 +03:00
|
|
|
{
|
2009-08-31 18:07:24 +04:00
|
|
|
VGACommonState *s = opaque;
|
2009-04-08 00:55:29 +04:00
|
|
|
int graphic_mode, i, cursor_offset, cursor_visible;
|
2008-02-10 19:33:14 +03:00
|
|
|
int cw, cheight, width, height, size, c_min, c_max;
|
|
|
|
uint32_t *src;
|
2009-10-02 01:12:16 +04:00
|
|
|
console_ch_t *dst, val;
|
2008-02-10 19:33:14 +03:00
|
|
|
char msg_buffer[80];
|
2009-04-08 00:55:29 +04:00
|
|
|
int full_update = 0;
|
|
|
|
|
2011-09-30 14:31:14 +04:00
|
|
|
qemu_flush_coalesced_mmio_buffer();
|
|
|
|
|
2009-04-08 00:55:29 +04:00
|
|
|
if (!(s->ar_index & 0x20)) {
|
|
|
|
graphic_mode = GMODE_BLANK;
|
|
|
|
} else {
|
2012-01-29 21:02:07 +04:00
|
|
|
graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
|
2009-04-08 00:55:29 +04:00
|
|
|
}
|
|
|
|
if (graphic_mode != s->graphic_mode) {
|
|
|
|
s->graphic_mode = graphic_mode;
|
|
|
|
full_update = 1;
|
|
|
|
}
|
|
|
|
if (s->last_width == -1) {
|
|
|
|
s->last_width = 0;
|
|
|
|
full_update = 1;
|
|
|
|
}
|
2008-02-10 19:33:14 +03:00
|
|
|
|
2009-04-08 00:55:29 +04:00
|
|
|
switch (graphic_mode) {
|
2008-02-10 19:33:14 +03:00
|
|
|
case GMODE_TEXT:
|
|
|
|
/* TODO: update palette */
|
2009-04-08 00:55:29 +04:00
|
|
|
full_update |= update_basic_params(s);
|
2008-02-10 19:33:14 +03:00
|
|
|
|
2009-04-08 00:55:29 +04:00
|
|
|
/* total width & height */
|
2012-01-29 21:02:07 +04:00
|
|
|
cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
|
2009-04-08 00:55:29 +04:00
|
|
|
cw = 8;
|
2016-05-17 11:54:54 +03:00
|
|
|
if (!(sr(s, VGA_SEQ_CLOCK_MODE) & VGA_SR01_CHAR_CLK_8DOTS)) {
|
2009-04-08 00:55:29 +04:00
|
|
|
cw = 9;
|
2012-01-29 21:02:07 +04:00
|
|
|
}
|
2016-05-17 11:54:54 +03:00
|
|
|
if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) {
|
2009-04-08 00:55:29 +04:00
|
|
|
cw = 16; /* NOTE: no 18 pixel wide */
|
2012-01-29 21:02:07 +04:00
|
|
|
}
|
|
|
|
width = (s->cr[VGA_CRTC_H_DISP] + 1);
|
|
|
|
if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
|
2009-04-08 00:55:29 +04:00
|
|
|
/* ugly hack for CGA 160x100x16 - explain me the logic */
|
|
|
|
height = 100;
|
|
|
|
} else {
|
2012-01-29 21:02:07 +04:00
|
|
|
height = s->cr[VGA_CRTC_V_DISP_END] |
|
|
|
|
((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
|
|
|
|
((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
|
2009-04-08 00:55:29 +04:00
|
|
|
height = (height + 1) / cheight;
|
2008-02-10 19:33:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
size = (height * width);
|
|
|
|
if (size > CH_ATTR_SIZE) {
|
|
|
|
if (!full_update)
|
|
|
|
return;
|
|
|
|
|
2008-08-21 21:58:08 +04:00
|
|
|
snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
|
|
|
|
width, height);
|
2008-02-10 19:33:14 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2009-04-08 00:55:29 +04:00
|
|
|
if (width != s->last_width || height != s->last_height ||
|
|
|
|
cw != s->last_cw || cheight != s->last_ch) {
|
|
|
|
s->last_scr_width = width * cw;
|
|
|
|
s->last_scr_height = height * cheight;
|
2013-03-05 18:24:14 +04:00
|
|
|
qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
|
|
|
|
dpy_text_resize(s->con, width, height);
|
2012-10-09 19:10:13 +04:00
|
|
|
s->last_depth = 0;
|
2009-04-08 00:55:29 +04:00
|
|
|
s->last_width = width;
|
|
|
|
s->last_height = height;
|
|
|
|
s->last_ch = cheight;
|
|
|
|
s->last_cw = cw;
|
|
|
|
full_update = 1;
|
|
|
|
}
|
|
|
|
|
2012-10-09 19:10:13 +04:00
|
|
|
if (full_update) {
|
|
|
|
s->full_update_gfx = 1;
|
|
|
|
}
|
|
|
|
if (s->full_update_text) {
|
|
|
|
s->full_update_text = 0;
|
|
|
|
full_update |= 1;
|
|
|
|
}
|
|
|
|
|
2008-02-10 19:33:14 +03:00
|
|
|
/* Update "hardware" cursor */
|
2012-01-29 21:02:07 +04:00
|
|
|
cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
|
|
|
|
s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
|
2008-02-10 19:33:14 +03:00
|
|
|
if (cursor_offset != s->cursor_offset ||
|
2012-01-29 21:02:07 +04:00
|
|
|
s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
|
|
|
|
s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
|
|
|
|
cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
|
2008-02-10 19:33:14 +03:00
|
|
|
if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_text_cursor(s->con,
|
2012-09-12 09:56:45 +04:00
|
|
|
TEXTMODE_X(cursor_offset),
|
|
|
|
TEXTMODE_Y(cursor_offset));
|
2008-02-10 19:33:14 +03:00
|
|
|
else
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_text_cursor(s->con, -1, -1);
|
2008-02-10 19:33:14 +03:00
|
|
|
s->cursor_offset = cursor_offset;
|
2012-01-29 21:02:07 +04:00
|
|
|
s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
|
|
|
|
s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
|
2008-02-10 19:33:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
src = (uint32_t *) s->vram_ptr + s->start_addr;
|
|
|
|
dst = chardata;
|
|
|
|
|
|
|
|
if (full_update) {
|
|
|
|
for (i = 0; i < size; src ++, dst ++, i ++)
|
2011-01-04 23:58:24 +03:00
|
|
|
console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
|
2008-02-10 19:33:14 +03:00
|
|
|
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_text_update(s->con, 0, 0, width, height);
|
2008-02-10 19:33:14 +03:00
|
|
|
} else {
|
|
|
|
c_max = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < size; src ++, dst ++, i ++) {
|
2011-01-04 23:58:24 +03:00
|
|
|
console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
|
2008-02-10 19:33:14 +03:00
|
|
|
if (*dst != val) {
|
|
|
|
*dst = val;
|
|
|
|
c_max = i;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
c_min = i;
|
|
|
|
for (; i < size; src ++, dst ++, i ++) {
|
2011-01-04 23:58:24 +03:00
|
|
|
console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
|
2008-02-10 19:33:14 +03:00
|
|
|
if (*dst != val) {
|
|
|
|
*dst = val;
|
|
|
|
c_max = i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (c_min <= c_max) {
|
|
|
|
i = TEXTMODE_Y(c_min);
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
|
2008-02-10 19:33:14 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
case GMODE_GRAPH:
|
|
|
|
if (!full_update)
|
|
|
|
return;
|
|
|
|
|
|
|
|
s->get_resolution(s, &width, &height);
|
2008-08-21 21:58:08 +04:00
|
|
|
snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
|
|
|
|
width, height);
|
2008-02-10 19:33:14 +03:00
|
|
|
break;
|
|
|
|
case GMODE_BLANK:
|
|
|
|
default:
|
|
|
|
if (!full_update)
|
|
|
|
return;
|
|
|
|
|
2008-08-21 21:58:08 +04:00
|
|
|
snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
|
2008-02-10 19:33:14 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Display a message */
|
2008-02-11 03:09:42 +03:00
|
|
|
s->last_width = 60;
|
|
|
|
s->last_height = height = 3;
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_text_cursor(s->con, -1, -1);
|
|
|
|
dpy_text_resize(s->con, s->last_width, height);
|
2008-02-10 19:33:14 +03:00
|
|
|
|
2008-02-11 03:09:42 +03:00
|
|
|
for (dst = chardata, i = 0; i < s->last_width * height; i ++)
|
2008-02-10 19:33:14 +03:00
|
|
|
console_write_ch(dst ++, ' ');
|
|
|
|
|
|
|
|
size = strlen(msg_buffer);
|
2008-02-11 03:09:42 +03:00
|
|
|
width = (s->last_width - size) / 2;
|
|
|
|
dst = chardata + s->last_width + width;
|
2008-02-10 19:33:14 +03:00
|
|
|
for (i = 0; i < size; i ++)
|
2015-11-29 16:28:24 +03:00
|
|
|
console_write_ch(dst ++, ATTR2CHTYPE(msg_buffer[i], QEMU_COLOR_BLUE,
|
|
|
|
QEMU_COLOR_BLACK, 1));
|
2008-02-10 19:33:14 +03:00
|
|
|
|
2013-03-05 18:24:14 +04:00
|
|
|
dpy_text_update(s->con, 0, 0, s->last_width, height);
|
2008-02-10 19:33:14 +03:00
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint64_t vga_mem_read(void *opaque, hwaddr addr,
|
2011-08-08 17:08:57 +04:00
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
VGACommonState *s = opaque;
|
|
|
|
|
2011-08-08 17:09:01 +04:00
|
|
|
return vga_mem_readb(s, addr);
|
2011-08-08 17:08:57 +04:00
|
|
|
}
|
2003-08-05 03:30:47 +04:00
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static void vga_mem_write(void *opaque, hwaddr addr,
|
2011-08-08 17:08:57 +04:00
|
|
|
uint64_t data, unsigned size)
|
|
|
|
{
|
|
|
|
VGACommonState *s = opaque;
|
|
|
|
|
2015-03-08 21:30:01 +03:00
|
|
|
vga_mem_writeb(s, addr, data);
|
2011-08-08 17:08:57 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
const MemoryRegionOps vga_mem_ops = {
|
|
|
|
.read = vga_mem_read,
|
|
|
|
.write = vga_mem_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
2011-08-08 17:09:01 +04:00
|
|
|
.impl = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 1,
|
|
|
|
},
|
2003-08-05 03:30:47 +04:00
|
|
|
};
|
|
|
|
|
2009-10-14 17:25:25 +04:00
|
|
|
static int vga_common_post_load(void *opaque, int version_id)
|
2004-03-31 22:58:38 +04:00
|
|
|
{
|
2009-08-31 18:07:14 +04:00
|
|
|
VGACommonState *s = opaque;
|
2009-10-14 17:25:25 +04:00
|
|
|
|
|
|
|
/* force refresh */
|
|
|
|
s->graphic_mode = -1;
|
2016-05-17 11:54:54 +03:00
|
|
|
vbe_update_vgaregs(s);
|
2009-10-14 17:25:25 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-06-23 07:57:41 +04:00
|
|
|
static bool vga_endian_state_needed(void *opaque)
|
|
|
|
{
|
|
|
|
VGACommonState *s = opaque;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only send the endian state if it's different from the
|
|
|
|
* default one, thus ensuring backward compatibility for
|
|
|
|
* migration of the common case
|
|
|
|
*/
|
|
|
|
return s->default_endian_fb != s->big_endian_fb;
|
|
|
|
}
|
|
|
|
|
2015-02-07 00:43:16 +03:00
|
|
|
static const VMStateDescription vmstate_vga_endian = {
|
2014-06-23 07:57:41 +04:00
|
|
|
.name = "vga.endian",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-09-23 16:09:54 +04:00
|
|
|
.needed = vga_endian_state_needed,
|
2014-06-23 07:57:41 +04:00
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_BOOL(big_endian_fb, VGACommonState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2009-10-14 17:25:25 +04:00
|
|
|
const VMStateDescription vmstate_vga_common = {
|
|
|
|
.name = "vga",
|
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 2,
|
|
|
|
.post_load = vga_common_post_load,
|
2014-04-16 17:32:32 +04:00
|
|
|
.fields = (VMStateField[]) {
|
2009-10-14 17:25:25 +04:00
|
|
|
VMSTATE_UINT32(latch, VGACommonState),
|
|
|
|
VMSTATE_UINT8(sr_index, VGACommonState),
|
|
|
|
VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
|
|
|
|
VMSTATE_UINT8(gr_index, VGACommonState),
|
|
|
|
VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
|
|
|
|
VMSTATE_UINT8(ar_index, VGACommonState),
|
|
|
|
VMSTATE_BUFFER(ar, VGACommonState),
|
|
|
|
VMSTATE_INT32(ar_flip_flop, VGACommonState),
|
|
|
|
VMSTATE_UINT8(cr_index, VGACommonState),
|
|
|
|
VMSTATE_BUFFER(cr, VGACommonState),
|
|
|
|
VMSTATE_UINT8(msr, VGACommonState),
|
|
|
|
VMSTATE_UINT8(fcr, VGACommonState),
|
|
|
|
VMSTATE_UINT8(st00, VGACommonState),
|
|
|
|
VMSTATE_UINT8(st01, VGACommonState),
|
|
|
|
|
|
|
|
VMSTATE_UINT8(dac_state, VGACommonState),
|
|
|
|
VMSTATE_UINT8(dac_sub_index, VGACommonState),
|
|
|
|
VMSTATE_UINT8(dac_read_index, VGACommonState),
|
|
|
|
VMSTATE_UINT8(dac_write_index, VGACommonState),
|
|
|
|
VMSTATE_BUFFER(dac_cache, VGACommonState),
|
|
|
|
VMSTATE_BUFFER(palette, VGACommonState),
|
|
|
|
|
|
|
|
VMSTATE_INT32(bank_offset, VGACommonState),
|
2017-06-23 17:48:23 +03:00
|
|
|
VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState, NULL),
|
2009-10-14 17:25:25 +04:00
|
|
|
VMSTATE_UINT16(vbe_index, VGACommonState),
|
|
|
|
VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
|
|
|
|
VMSTATE_UINT32(vbe_start_addr, VGACommonState),
|
|
|
|
VMSTATE_UINT32(vbe_line_offset, VGACommonState),
|
|
|
|
VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
2014-06-23 07:57:41 +04:00
|
|
|
},
|
2014-09-23 16:09:54 +04:00
|
|
|
.subsections = (const VMStateDescription*[]) {
|
|
|
|
&vmstate_vga_endian,
|
|
|
|
NULL
|
2009-10-14 17:25:25 +04:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2013-03-13 17:04:18 +04:00
|
|
|
static const GraphicHwOps vga_ops = {
|
|
|
|
.invalidate = vga_invalidate_display,
|
|
|
|
.gfx_update = vga_update_display,
|
|
|
|
.text_update = vga_update_text,
|
|
|
|
};
|
|
|
|
|
2015-02-17 19:30:53 +03:00
|
|
|
static inline uint32_t uint_clamp(uint32_t val, uint32_t vmin, uint32_t vmax)
|
|
|
|
{
|
|
|
|
if (val < vmin) {
|
|
|
|
return vmin;
|
|
|
|
}
|
|
|
|
if (val > vmax) {
|
|
|
|
return vmax;
|
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2013-10-11 21:56:59 +04:00
|
|
|
void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate)
|
2003-08-05 03:30:47 +04:00
|
|
|
{
|
2003-08-09 03:50:57 +04:00
|
|
|
int i, j, v, b;
|
2003-08-05 03:30:47 +04:00
|
|
|
|
|
|
|
for(i = 0;i < 256; i++) {
|
|
|
|
v = 0;
|
|
|
|
for(j = 0; j < 8; j++) {
|
|
|
|
v |= ((i >> j) & 1) << (j * 4);
|
|
|
|
}
|
|
|
|
expand4[i] = v;
|
|
|
|
|
|
|
|
v = 0;
|
|
|
|
for(j = 0; j < 4; j++) {
|
|
|
|
v |= ((i >> (2 * j)) & 3) << (j * 4);
|
|
|
|
}
|
|
|
|
expand2[i] = v;
|
|
|
|
}
|
2003-08-09 03:50:57 +04:00
|
|
|
for(i = 0; i < 16; i++) {
|
|
|
|
v = 0;
|
|
|
|
for(j = 0; j < 4; j++) {
|
|
|
|
b = ((i >> j) & 1);
|
|
|
|
v |= b << (2 * j);
|
|
|
|
v |= b << (2 * j + 1);
|
|
|
|
}
|
|
|
|
expand4to8[i] = v;
|
|
|
|
}
|
2003-08-05 03:30:47 +04:00
|
|
|
|
2015-02-17 19:30:53 +03:00
|
|
|
s->vram_size_mb = uint_clamp(s->vram_size_mb, 1, 512);
|
|
|
|
s->vram_size_mb = pow2ceil(s->vram_size_mb);
|
|
|
|
s->vram_size = s->vram_size_mb << 20;
|
|
|
|
|
2014-08-26 16:16:30 +04:00
|
|
|
if (!s->vbe_size) {
|
|
|
|
s->vbe_size = s->vram_size;
|
|
|
|
}
|
2012-05-24 11:59:44 +04:00
|
|
|
|
2009-10-14 16:10:11 +04:00
|
|
|
s->is_vbe_vmstate = 1;
|
2014-09-09 09:27:55 +04:00
|
|
|
memory_region_init_ram(&s->vram, obj, "vga.vram", s->vram_size,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 17:51:43 +03:00
|
|
|
&error_fatal);
|
2013-10-11 21:56:59 +04:00
|
|
|
vmstate_register_ram(&s->vram, global_vmstate ? NULL : DEVICE(obj));
|
2011-12-18 18:40:50 +04:00
|
|
|
xen_register_framebuffer(&s->vram);
|
2011-08-08 17:08:57 +04:00
|
|
|
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
|
2004-06-05 14:30:49 +04:00
|
|
|
s->get_bpp = vga_get_bpp;
|
|
|
|
s->get_offsets = vga_get_offsets;
|
2004-06-08 04:59:19 +04:00
|
|
|
s->get_resolution = vga_get_resolution;
|
2013-03-13 17:04:18 +04:00
|
|
|
s->hw_ops = &vga_ops;
|
2008-09-28 04:42:12 +04:00
|
|
|
switch (vga_retrace_method) {
|
|
|
|
case VGA_RETRACE_DUMB:
|
|
|
|
s->retrace = vga_dumb_retrace;
|
|
|
|
s->update_retrace_info = vga_dumb_update_retrace_info;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case VGA_RETRACE_PRECISE:
|
|
|
|
s->retrace = vga_precise_retrace;
|
|
|
|
s->update_retrace_info = vga_precise_update_retrace_info;
|
|
|
|
break;
|
|
|
|
}
|
2014-07-07 03:50:12 +04:00
|
|
|
|
|
|
|
/*
|
2014-06-23 07:57:41 +04:00
|
|
|
* Set default fb endian based on target, could probably be turned
|
2014-07-07 03:50:12 +04:00
|
|
|
* into a device attribute set by the machine/platform to remove
|
|
|
|
* all target endian dependencies from this file.
|
|
|
|
*/
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
2014-06-23 07:57:41 +04:00
|
|
|
s->default_endian_fb = true;
|
2014-07-07 03:50:12 +04:00
|
|
|
#else
|
2014-06-23 07:57:41 +04:00
|
|
|
s->default_endian_fb = false;
|
2014-07-07 03:50:12 +04:00
|
|
|
#endif
|
2011-08-08 17:08:57 +04:00
|
|
|
vga_dirty_log_start(s);
|
2004-06-05 14:30:49 +04:00
|
|
|
}
|
|
|
|
|
2011-08-16 19:27:39 +04:00
|
|
|
static const MemoryRegionPortio vga_portio_list[] = {
|
|
|
|
{ 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
|
|
|
|
{ 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
|
|
|
|
{ 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
|
|
|
|
{ 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
|
|
|
|
{ 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
|
|
|
|
PORTIO_END_OF_LIST(),
|
|
|
|
};
|
2003-08-05 03:30:47 +04:00
|
|
|
|
2011-08-16 19:27:39 +04:00
|
|
|
static const MemoryRegionPortio vbe_portio_list[] = {
|
|
|
|
{ 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
|
|
|
|
# ifdef TARGET_I386
|
|
|
|
{ 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
|
|
|
|
# endif
|
2012-11-12 15:40:46 +04:00
|
|
|
{ 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
|
2011-08-16 19:27:39 +04:00
|
|
|
PORTIO_END_OF_LIST(),
|
|
|
|
};
|
2004-02-06 22:47:52 +03:00
|
|
|
|
2011-08-16 19:27:39 +04:00
|
|
|
/* Used by both ISA and PCI */
|
2013-06-07 05:21:13 +04:00
|
|
|
MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
|
2011-08-16 19:27:39 +04:00
|
|
|
const MemoryRegionPortio **vga_ports,
|
|
|
|
const MemoryRegionPortio **vbe_ports)
|
|
|
|
{
|
|
|
|
MemoryRegion *vga_mem;
|
2004-05-27 02:58:01 +04:00
|
|
|
|
2011-08-16 19:27:39 +04:00
|
|
|
*vga_ports = vga_portio_list;
|
|
|
|
*vbe_ports = vbe_portio_list;
|
2004-02-06 22:47:52 +03:00
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
vga_mem = g_malloc(sizeof(*vga_mem));
|
2013-06-07 05:21:13 +04:00
|
|
|
memory_region_init_io(vga_mem, obj, &vga_mem_ops, s,
|
2011-08-08 17:08:57 +04:00
|
|
|
"vga-lowmem", 0x20000);
|
2012-08-23 15:02:33 +04:00
|
|
|
memory_region_set_flush_coalesced(vga_mem);
|
2011-08-08 17:08:57 +04:00
|
|
|
|
|
|
|
return vga_mem;
|
2011-02-13 17:01:05 +03:00
|
|
|
}
|
|
|
|
|
2013-06-07 05:21:13 +04:00
|
|
|
void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
|
2011-08-16 19:27:39 +04:00
|
|
|
MemoryRegion *address_space_io, bool init_vga_ports)
|
2011-02-13 17:01:05 +03:00
|
|
|
{
|
2011-08-08 17:08:57 +04:00
|
|
|
MemoryRegion *vga_io_memory;
|
2011-08-16 19:27:39 +04:00
|
|
|
const MemoryRegionPortio *vga_ports, *vbe_ports;
|
2011-02-13 17:01:05 +03:00
|
|
|
|
|
|
|
qemu_register_reset(vga_reset, s);
|
|
|
|
|
|
|
|
s->bank_offset = 0;
|
|
|
|
|
2011-08-22 21:12:12 +04:00
|
|
|
s->legacy_address_space = address_space;
|
|
|
|
|
2013-06-07 05:21:13 +04:00
|
|
|
vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports);
|
2011-08-15 18:17:37 +04:00
|
|
|
memory_region_add_subregion_overlap(address_space,
|
2015-02-01 11:12:56 +03:00
|
|
|
0x000a0000,
|
2011-08-08 17:08:57 +04:00
|
|
|
vga_io_memory,
|
|
|
|
1);
|
|
|
|
memory_region_set_coalescing(vga_io_memory);
|
2011-08-16 19:27:39 +04:00
|
|
|
if (init_vga_ports) {
|
2014-04-29 17:38:39 +04:00
|
|
|
portio_list_init(&s->vga_port_list, obj, vga_ports, s, "vga");
|
|
|
|
portio_list_set_flush_coalesced(&s->vga_port_list);
|
|
|
|
portio_list_add(&s->vga_port_list, address_space_io, 0x3b0);
|
2011-08-16 19:27:39 +04:00
|
|
|
}
|
|
|
|
if (vbe_ports) {
|
2014-04-29 17:38:39 +04:00
|
|
|
portio_list_init(&s->vbe_port_list, obj, vbe_ports, s, "vbe");
|
|
|
|
portio_list_add(&s->vbe_port_list, address_space_io, 0x1ce);
|
2011-08-16 19:27:39 +04:00
|
|
|
}
|
2006-08-17 14:44:00 +04:00
|
|
|
}
|
|
|
|
|
2013-06-07 05:21:13 +04:00
|
|
|
void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *system_memory)
|
2009-12-18 01:08:07 +03:00
|
|
|
{
|
2012-05-09 19:23:06 +04:00
|
|
|
/* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
|
|
|
|
* so use an alias to avoid double-mapping the same region.
|
|
|
|
*/
|
2013-06-07 05:21:13 +04:00
|
|
|
memory_region_init_alias(&s->vram_vbe, obj, "vram.vbe",
|
2012-05-09 19:23:06 +04:00
|
|
|
&s->vram, 0, memory_region_size(&s->vram));
|
2009-12-18 01:08:07 +03:00
|
|
|
/* XXX: use optimized standard vga accesses */
|
2011-08-15 18:17:37 +04:00
|
|
|
memory_region_add_subregion(system_memory,
|
2011-08-08 17:08:57 +04:00
|
|
|
VBE_DISPI_LFB_PHYSICAL_ADDRESS,
|
2012-05-09 19:23:06 +04:00
|
|
|
&s->vram_vbe);
|
2009-12-18 01:08:07 +03:00
|
|
|
s->vbe_mapped = 1;
|
|
|
|
}
|