2011-03-08 01:32:40 +03:00
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/*
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* QEMU model of the Milkymist texture mapping unit.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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* Copyright (c) 2010 Sebastien Bourdeauducq
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* <sebastien.bourdeauducq@lekernel.net>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* http://www.milkymist.org/socdoc/tmu2.pdf
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*
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "trace.h"
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#include "qemu-error.h"
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#include <X11/Xlib.h>
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#include <GL/gl.h>
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#include <GL/glx.h>
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enum {
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R_CTL = 0,
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R_HMESHLAST,
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R_VMESHLAST,
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R_BRIGHTNESS,
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R_CHROMAKEY,
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R_VERTICESADDR,
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R_TEXFBUF,
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R_TEXHRES,
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R_TEXVRES,
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R_TEXHMASK,
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R_TEXVMASK,
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R_DSTFBUF,
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R_DSTHRES,
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R_DSTVRES,
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R_DSTHOFFSET,
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R_DSTVOFFSET,
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R_DSTSQUAREW,
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R_DSTSQUAREH,
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R_ALPHA,
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R_MAX
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};
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enum {
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CTL_START_BUSY = (1<<0),
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CTL_CHROMAKEY = (1<<1),
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};
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enum {
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MAX_BRIGHTNESS = 63,
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MAX_ALPHA = 63,
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};
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enum {
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MESH_MAXSIZE = 128,
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};
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struct vertex {
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int x;
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int y;
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2011-08-31 14:38:01 +04:00
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} QEMU_PACKED;
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2011-03-08 01:32:40 +03:00
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struct MilkymistTMU2State {
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SysBusDevice busdev;
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2011-08-31 18:48:44 +04:00
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MemoryRegion regs_region;
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2011-03-08 01:32:40 +03:00
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CharDriverState *chr;
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qemu_irq irq;
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uint32_t regs[R_MAX];
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Display *dpy;
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GLXFBConfig glx_fb_config;
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GLXContext glx_context;
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};
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typedef struct MilkymistTMU2State MilkymistTMU2State;
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static const int glx_fbconfig_attr[] = {
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GLX_GREEN_SIZE, 5,
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GLX_GREEN_SIZE, 6,
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GLX_BLUE_SIZE, 5,
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None
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};
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static int tmu2_glx_init(MilkymistTMU2State *s)
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{
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GLXFBConfig *configs;
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int nelements;
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s->dpy = XOpenDisplay(NULL); /* FIXME: call XCloseDisplay() */
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if (s->dpy == NULL) {
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return 1;
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}
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configs = glXChooseFBConfig(s->dpy, 0, glx_fbconfig_attr, &nelements);
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if (configs == NULL) {
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return 1;
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}
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s->glx_fb_config = *configs;
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XFree(configs);
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/* FIXME: call glXDestroyContext() */
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s->glx_context = glXCreateNewContext(s->dpy, s->glx_fb_config,
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GLX_RGBA_TYPE, NULL, 1);
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if (s->glx_context == NULL) {
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return 1;
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}
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return 0;
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}
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static void tmu2_gl_map(struct vertex *mesh, int texhres, int texvres,
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int hmeshlast, int vmeshlast, int ho, int vo, int sw, int sh)
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{
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int x, y;
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int x0, y0, x1, y1;
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int u0, v0, u1, v1, u2, v2, u3, v3;
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double xscale = 1.0 / ((double)(64 * texhres));
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double yscale = 1.0 / ((double)(64 * texvres));
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glLoadIdentity();
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glTranslatef(ho, vo, 0);
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glEnable(GL_TEXTURE_2D);
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glBegin(GL_QUADS);
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for (y = 0; y < vmeshlast; y++) {
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y0 = y * sh;
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y1 = y0 + sh;
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for (x = 0; x < hmeshlast; x++) {
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x0 = x * sw;
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x1 = x0 + sw;
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u0 = be32_to_cpu(mesh[MESH_MAXSIZE * y + x].x);
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v0 = be32_to_cpu(mesh[MESH_MAXSIZE * y + x].y);
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u1 = be32_to_cpu(mesh[MESH_MAXSIZE * y + x + 1].x);
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v1 = be32_to_cpu(mesh[MESH_MAXSIZE * y + x + 1].y);
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u2 = be32_to_cpu(mesh[MESH_MAXSIZE * (y + 1) + x + 1].x);
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v2 = be32_to_cpu(mesh[MESH_MAXSIZE * (y + 1) + x + 1].y);
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u3 = be32_to_cpu(mesh[MESH_MAXSIZE * (y + 1) + x].x);
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v3 = be32_to_cpu(mesh[MESH_MAXSIZE * (y + 1) + x].y);
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glTexCoord2d(((double)u0) * xscale, ((double)v0) * yscale);
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glVertex3i(x0, y0, 0);
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glTexCoord2d(((double)u1) * xscale, ((double)v1) * yscale);
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glVertex3i(x1, y0, 0);
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glTexCoord2d(((double)u2) * xscale, ((double)v2) * yscale);
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glVertex3i(x1, y1, 0);
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glTexCoord2d(((double)u3) * xscale, ((double)v3) * yscale);
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glVertex3i(x0, y1, 0);
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}
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}
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glEnd();
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}
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static void tmu2_start(MilkymistTMU2State *s)
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{
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int pbuffer_attrib[6] = {
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GLX_PBUFFER_WIDTH,
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0,
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GLX_PBUFFER_HEIGHT,
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0,
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GLX_PRESERVED_CONTENTS,
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True
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};
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GLXPbuffer pbuffer;
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GLuint texture;
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void *fb;
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target_phys_addr_t fb_len;
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void *mesh;
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target_phys_addr_t mesh_len;
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float m;
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trace_milkymist_tmu2_start();
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/* Create and set up a suitable OpenGL context */
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pbuffer_attrib[1] = s->regs[R_DSTHRES];
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pbuffer_attrib[3] = s->regs[R_DSTVRES];
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pbuffer = glXCreatePbuffer(s->dpy, s->glx_fb_config, pbuffer_attrib);
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glXMakeContextCurrent(s->dpy, pbuffer, pbuffer, s->glx_context);
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/* Fixup endianness. TODO: would it work on BE hosts? */
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glPixelStorei(GL_UNPACK_SWAP_BYTES, 1);
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glPixelStorei(GL_PACK_SWAP_BYTES, 1);
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/* Row alignment */
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glPixelStorei(GL_UNPACK_ALIGNMENT, 2);
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glPixelStorei(GL_PACK_ALIGNMENT, 2);
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/* Read the QEMU source framebuffer into an OpenGL texture */
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glGenTextures(1, &texture);
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glBindTexture(GL_TEXTURE_2D, texture);
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fb_len = 2*s->regs[R_TEXHRES]*s->regs[R_TEXVRES];
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fb = cpu_physical_memory_map(s->regs[R_TEXFBUF], &fb_len, 0);
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if (fb == NULL) {
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glDeleteTextures(1, &texture);
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glXMakeContextCurrent(s->dpy, None, None, NULL);
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glXDestroyPbuffer(s->dpy, pbuffer);
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return;
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}
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glTexImage2D(GL_TEXTURE_2D, 0, 3, s->regs[R_TEXHRES], s->regs[R_TEXVRES],
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0, GL_RGB, GL_UNSIGNED_SHORT_5_6_5, fb);
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cpu_physical_memory_unmap(fb, fb_len, 0, fb_len);
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/* Set up texturing options */
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/* WARNING:
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* Many cases of TMU2 masking are not supported by OpenGL.
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* We only implement the most common ones:
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* - full bilinear filtering vs. nearest texel
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* - texture clamping vs. texture wrapping
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*/
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if ((s->regs[R_TEXHMASK] & 0x3f) > 0x20) {
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glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR);
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glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_LINEAR);
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} else {
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glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST);
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glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_NEAREST);
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}
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if ((s->regs[R_TEXHMASK] >> 6) & s->regs[R_TEXHRES]) {
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glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_CLAMP);
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} else {
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glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_REPEAT);
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}
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if ((s->regs[R_TEXVMASK] >> 6) & s->regs[R_TEXVRES]) {
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glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_T, GL_CLAMP);
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} else {
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glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_T, GL_REPEAT);
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}
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/* Translucency and decay */
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glEnable(GL_BLEND);
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glBlendFunc(GL_SRC_ALPHA, GL_ONE_MINUS_SRC_ALPHA);
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m = (float)(s->regs[R_BRIGHTNESS] + 1) / 64.0f;
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glColor4f(m, m, m, (float)(s->regs[R_ALPHA] + 1) / 64.0f);
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/* Read the QEMU dest. framebuffer into the OpenGL framebuffer */
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fb_len = 2 * s->regs[R_DSTHRES] * s->regs[R_DSTVRES];
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fb = cpu_physical_memory_map(s->regs[R_DSTFBUF], &fb_len, 0);
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if (fb == NULL) {
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glDeleteTextures(1, &texture);
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glXMakeContextCurrent(s->dpy, None, None, NULL);
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glXDestroyPbuffer(s->dpy, pbuffer);
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return;
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}
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glDrawPixels(s->regs[R_DSTHRES], s->regs[R_DSTVRES], GL_RGB,
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GL_UNSIGNED_SHORT_5_6_5, fb);
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cpu_physical_memory_unmap(fb, fb_len, 0, fb_len);
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glViewport(0, 0, s->regs[R_DSTHRES], s->regs[R_DSTVRES]);
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glMatrixMode(GL_PROJECTION);
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glLoadIdentity();
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glOrtho(0.0, s->regs[R_DSTHRES], 0.0, s->regs[R_DSTVRES], -1.0, 1.0);
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glMatrixMode(GL_MODELVIEW);
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/* Map the texture */
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mesh_len = MESH_MAXSIZE*MESH_MAXSIZE*sizeof(struct vertex);
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mesh = cpu_physical_memory_map(s->regs[R_VERTICESADDR], &mesh_len, 0);
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if (mesh == NULL) {
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glDeleteTextures(1, &texture);
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glXMakeContextCurrent(s->dpy, None, None, NULL);
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glXDestroyPbuffer(s->dpy, pbuffer);
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return;
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}
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tmu2_gl_map((struct vertex *)mesh,
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s->regs[R_TEXHRES], s->regs[R_TEXVRES],
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s->regs[R_HMESHLAST], s->regs[R_VMESHLAST],
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s->regs[R_DSTHOFFSET], s->regs[R_DSTVOFFSET],
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s->regs[R_DSTSQUAREW], s->regs[R_DSTSQUAREH]);
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cpu_physical_memory_unmap(mesh, mesh_len, 0, mesh_len);
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/* Write back the OpenGL framebuffer to the QEMU framebuffer */
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fb_len = 2 * s->regs[R_DSTHRES] * s->regs[R_DSTVRES];
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fb = cpu_physical_memory_map(s->regs[R_DSTFBUF], &fb_len, 1);
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if (fb == NULL) {
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glDeleteTextures(1, &texture);
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glXMakeContextCurrent(s->dpy, None, None, NULL);
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glXDestroyPbuffer(s->dpy, pbuffer);
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return;
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}
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glReadPixels(0, 0, s->regs[R_DSTHRES], s->regs[R_DSTVRES], GL_RGB,
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GL_UNSIGNED_SHORT_5_6_5, fb);
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cpu_physical_memory_unmap(fb, fb_len, 1, fb_len);
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/* Free OpenGL allocs */
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glDeleteTextures(1, &texture);
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glXMakeContextCurrent(s->dpy, None, None, NULL);
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glXDestroyPbuffer(s->dpy, pbuffer);
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s->regs[R_CTL] &= ~CTL_START_BUSY;
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trace_milkymist_tmu2_pulse_irq();
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qemu_irq_pulse(s->irq);
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}
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2011-08-31 18:48:44 +04:00
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static uint64_t tmu2_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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2011-03-08 01:32:40 +03:00
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{
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MilkymistTMU2State *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_CTL:
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case R_HMESHLAST:
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case R_VMESHLAST:
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case R_BRIGHTNESS:
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case R_CHROMAKEY:
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case R_VERTICESADDR:
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case R_TEXFBUF:
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case R_TEXHRES:
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case R_TEXVRES:
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case R_TEXHMASK:
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case R_TEXVMASK:
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case R_DSTFBUF:
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case R_DSTHRES:
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case R_DSTVRES:
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case R_DSTHOFFSET:
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case R_DSTVOFFSET:
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case R_DSTSQUAREW:
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case R_DSTSQUAREH:
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case R_ALPHA:
|
|
|
|
r = s->regs[addr];
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
error_report("milkymist_tmu2: read access to unknown register 0x"
|
|
|
|
TARGET_FMT_plx, addr << 2);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
trace_milkymist_tmu2_memory_read(addr << 2, r);
|
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tmu2_check_registers(MilkymistTMU2State *s)
|
|
|
|
{
|
|
|
|
if (s->regs[R_BRIGHTNESS] > MAX_BRIGHTNESS) {
|
2011-06-22 16:03:54 +04:00
|
|
|
error_report("milkymist_tmu2: max brightness is %d", MAX_BRIGHTNESS);
|
2011-03-08 01:32:40 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
if (s->regs[R_ALPHA] > MAX_ALPHA) {
|
2011-06-22 16:03:54 +04:00
|
|
|
error_report("milkymist_tmu2: max alpha is %d", MAX_ALPHA);
|
2011-03-08 01:32:40 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
if (s->regs[R_VERTICESADDR] & 0x07) {
|
|
|
|
error_report("milkymist_tmu2: vertex mesh address has to be 64-bit "
|
2011-06-22 16:03:54 +04:00
|
|
|
"aligned");
|
2011-03-08 01:32:40 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
if (s->regs[R_TEXFBUF] & 0x01) {
|
|
|
|
error_report("milkymist_tmu2: texture buffer address has to be "
|
2011-06-22 16:03:54 +04:00
|
|
|
"16-bit aligned");
|
2011-03-08 01:32:40 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-31 18:48:44 +04:00
|
|
|
static void tmu2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
|
|
|
|
unsigned size)
|
2011-03-08 01:32:40 +03:00
|
|
|
{
|
|
|
|
MilkymistTMU2State *s = opaque;
|
|
|
|
|
|
|
|
trace_milkymist_tmu2_memory_write(addr, value);
|
|
|
|
|
|
|
|
addr >>= 2;
|
|
|
|
switch (addr) {
|
|
|
|
case R_CTL:
|
|
|
|
s->regs[addr] = value;
|
|
|
|
if (value & CTL_START_BUSY) {
|
|
|
|
tmu2_start(s);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case R_BRIGHTNESS:
|
|
|
|
case R_HMESHLAST:
|
|
|
|
case R_VMESHLAST:
|
|
|
|
case R_CHROMAKEY:
|
|
|
|
case R_VERTICESADDR:
|
|
|
|
case R_TEXFBUF:
|
|
|
|
case R_TEXHRES:
|
|
|
|
case R_TEXVRES:
|
|
|
|
case R_TEXHMASK:
|
|
|
|
case R_TEXVMASK:
|
|
|
|
case R_DSTFBUF:
|
|
|
|
case R_DSTHRES:
|
|
|
|
case R_DSTVRES:
|
|
|
|
case R_DSTHOFFSET:
|
|
|
|
case R_DSTVOFFSET:
|
|
|
|
case R_DSTSQUAREW:
|
|
|
|
case R_DSTSQUAREH:
|
|
|
|
case R_ALPHA:
|
|
|
|
s->regs[addr] = value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
error_report("milkymist_tmu2: write access to unknown register 0x"
|
|
|
|
TARGET_FMT_plx, addr << 2);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
tmu2_check_registers(s);
|
|
|
|
}
|
|
|
|
|
2011-08-31 18:48:44 +04:00
|
|
|
static const MemoryRegionOps tmu2_mmio_ops = {
|
|
|
|
.read = tmu2_read,
|
|
|
|
.write = tmu2_write,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2011-03-08 01:32:40 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
static void milkymist_tmu2_reset(DeviceState *d)
|
|
|
|
{
|
|
|
|
MilkymistTMU2State *s = container_of(d, MilkymistTMU2State, busdev.qdev);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < R_MAX; i++) {
|
|
|
|
s->regs[i] = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int milkymist_tmu2_init(SysBusDevice *dev)
|
|
|
|
{
|
|
|
|
MilkymistTMU2State *s = FROM_SYSBUS(typeof(*s), dev);
|
|
|
|
|
|
|
|
if (tmu2_glx_init(s)) {
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
sysbus_init_irq(dev, &s->irq);
|
|
|
|
|
2011-08-31 18:48:44 +04:00
|
|
|
memory_region_init_io(&s->regs_region, &tmu2_mmio_ops, s,
|
|
|
|
"milkymist-tmu2", R_MAX * 4);
|
2011-11-27 13:38:10 +04:00
|
|
|
sysbus_init_mmio(dev, &s->regs_region);
|
2011-03-08 01:32:40 +03:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_milkymist_tmu2 = {
|
|
|
|
.name = "milkymist-tmu2",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.minimum_version_id_old = 1,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32_ARRAY(regs, MilkymistTMU2State, R_MAX),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2012-01-24 23:12:29 +04:00
|
|
|
static void milkymist_tmu2_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 23:12:29 +04:00
|
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->init = milkymist_tmu2_init;
|
2011-12-08 07:34:16 +04:00
|
|
|
dc->reset = milkymist_tmu2_reset;
|
|
|
|
dc->vmsd = &vmstate_milkymist_tmu2;
|
2012-01-24 23:12:29 +04:00
|
|
|
}
|
|
|
|
|
2011-12-08 07:34:16 +04:00
|
|
|
static TypeInfo milkymist_tmu2_info = {
|
|
|
|
.name = "milkymist-tmu2",
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(MilkymistTMU2State),
|
|
|
|
.class_init = milkymist_tmu2_class_init,
|
2011-03-08 01:32:40 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
static void milkymist_tmu2_register(void)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&milkymist_tmu2_info);
|
2011-03-08 01:32:40 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
device_init(milkymist_tmu2_register)
|