64 lines
1.5 KiB
Python
64 lines
1.5 KiB
Python
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# OpenSBI boot test for RISC-V machines
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#
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# Copyright (c) 2022, Ventana Micro
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#
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# This work is licensed under the terms of the GNU GPL, version 2 or
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# later. See the COPYING file in the top-level directory.
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from avocado_qemu import QemuSystemTest
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from avocado_qemu import wait_for_console_pattern
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class RiscvOpenSBI(QemuSystemTest):
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"""
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:avocado: tags=accel:tcg
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"""
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timeout = 5
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def boot_opensbi(self):
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self.vm.set_console()
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self.vm.launch()
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wait_for_console_pattern(self, 'Platform Name')
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wait_for_console_pattern(self, 'Boot HART MEDELEG')
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def test_riscv32_spike(self):
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"""
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:avocado: tags=arch:riscv32
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:avocado: tags=machine:spike
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"""
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self.boot_opensbi()
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def test_riscv64_spike(self):
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"""
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:avocado: tags=arch:riscv64
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:avocado: tags=machine:spike
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"""
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self.boot_opensbi()
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def test_riscv32_sifive_u(self):
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"""
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:avocado: tags=arch:riscv32
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:avocado: tags=machine:sifive_u
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"""
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self.boot_opensbi()
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def test_riscv64_sifive_u(self):
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"""
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:avocado: tags=arch:riscv64
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:avocado: tags=machine:sifive_u
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"""
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self.boot_opensbi()
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def test_riscv32_virt(self):
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"""
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:avocado: tags=arch:riscv32
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:avocado: tags=machine:virt
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"""
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self.boot_opensbi()
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def test_riscv64_virt(self):
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"""
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:avocado: tags=arch:riscv64
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:avocado: tags=machine:virt
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"""
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self.boot_opensbi()
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