2007-09-17 01:08:06 +04:00
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/*
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2007-05-23 04:03:59 +04:00
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* QEMU SMBus device emulation.
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*
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2018-11-14 03:31:27 +03:00
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* This code is a helper for SMBus device emulation. It implements an
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2023-08-23 09:53:26 +03:00
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* I2C device interface and runs the SMBus protocol from the device
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2018-11-14 03:31:27 +03:00
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* point of view and maps those to simple calls to emulate.
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*
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2007-05-23 04:03:59 +04:00
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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2011-06-26 06:21:35 +04:00
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* This code is licensed under the LGPL.
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2007-05-23 04:03:59 +04:00
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*/
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/* TODO: Implement PEC. */
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2016-01-26 21:17:30 +03:00
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#include "qemu/osdep.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/i2c/i2c.h"
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2018-11-14 03:31:27 +03:00
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#include "hw/i2c/smbus_slave.h"
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2019-08-12 08:23:45 +03:00
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#include "migration/vmstate.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2007-05-23 04:03:59 +04:00
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//#define DEBUG_SMBUS 1
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#ifdef DEBUG_SMBUS
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2009-05-13 21:53:17 +04:00
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#define DPRINTF(fmt, ...) \
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do { printf("smbus(%02x): " fmt , dev->i2c.address, ## __VA_ARGS__); } while (0)
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#define BADF(fmt, ...) \
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2024-02-02 23:48:46 +03:00
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do { g_autofree char *qom_path = object_get_canonical_path(OBJECT(dev)); \
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fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
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exit(1); } while (0)
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2007-05-23 04:03:59 +04:00
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#else
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2009-05-13 21:53:17 +04:00
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#define DPRINTF(fmt, ...) do {} while(0)
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#define BADF(fmt, ...) \
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2024-02-02 23:48:46 +03:00
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do { g_autofree char *qom_path = object_get_canonical_path(OBJECT(dev)); \
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fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
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} while (0)
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2007-05-23 04:03:59 +04:00
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#endif
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enum {
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SMBUS_IDLE,
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SMBUS_WRITE_DATA,
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SMBUS_READ_DATA,
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SMBUS_DONE,
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SMBUS_CONFUSED = -1
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};
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static void smbus_do_quick_cmd(SMBusDevice *dev, int recv)
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{
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2011-12-05 06:39:20 +04:00
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SMBusDeviceClass *sc = SMBUS_DEVICE_GET_CLASS(dev);
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2009-05-15 01:35:08 +04:00
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2007-05-23 04:03:59 +04:00
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DPRINTF("Quick Command %d\n", recv);
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2011-12-05 06:39:20 +04:00
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if (sc->quick_cmd) {
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sc->quick_cmd(dev, recv);
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}
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2007-05-23 04:03:59 +04:00
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}
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static void smbus_do_write(SMBusDevice *dev)
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{
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2011-12-05 06:39:20 +04:00
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SMBusDeviceClass *sc = SMBUS_DEVICE_GET_CLASS(dev);
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2009-05-15 01:35:08 +04:00
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2018-11-30 22:38:21 +03:00
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DPRINTF("Command %d len %d\n", dev->data_buf[0], dev->data_len);
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if (sc->write_data) {
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sc->write_data(dev, dev->data_buf, dev->data_len);
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2007-05-23 04:03:59 +04:00
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}
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}
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2017-01-09 14:40:20 +03:00
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static int smbus_i2c_event(I2CSlave *s, enum i2c_event event)
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2007-05-23 04:03:59 +04:00
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{
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2011-12-05 06:39:20 +04:00
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SMBusDevice *dev = SMBUS_DEVICE(s);
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2009-05-15 01:35:08 +04:00
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2007-05-23 04:03:59 +04:00
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switch (event) {
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case I2C_START_SEND:
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switch (dev->mode) {
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case SMBUS_IDLE:
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DPRINTF("Incoming data\n");
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dev->mode = SMBUS_WRITE_DATA;
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break;
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2018-11-30 23:04:19 +03:00
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2007-05-23 04:03:59 +04:00
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default:
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BADF("Unexpected send start condition in state %d\n", dev->mode);
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dev->mode = SMBUS_CONFUSED;
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break;
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}
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break;
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case I2C_START_RECV:
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switch (dev->mode) {
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case SMBUS_IDLE:
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DPRINTF("Read mode\n");
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2018-11-30 22:49:31 +03:00
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dev->mode = SMBUS_READ_DATA;
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2007-05-23 04:03:59 +04:00
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break;
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2018-11-30 23:04:19 +03:00
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2007-05-23 04:03:59 +04:00
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case SMBUS_WRITE_DATA:
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if (dev->data_len == 0) {
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BADF("Read after write with no data\n");
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dev->mode = SMBUS_CONFUSED;
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} else {
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2018-11-30 22:38:21 +03:00
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smbus_do_write(dev);
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2007-05-23 04:03:59 +04:00
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DPRINTF("Read mode\n");
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dev->mode = SMBUS_READ_DATA;
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}
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break;
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2018-11-30 23:04:19 +03:00
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2007-05-23 04:03:59 +04:00
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default:
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BADF("Unexpected recv start condition in state %d\n", dev->mode);
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dev->mode = SMBUS_CONFUSED;
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break;
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}
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break;
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case I2C_FINISH:
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2018-11-30 22:20:12 +03:00
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if (dev->data_len == 0) {
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if (dev->mode == SMBUS_WRITE_DATA || dev->mode == SMBUS_READ_DATA) {
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smbus_do_quick_cmd(dev, dev->mode == SMBUS_READ_DATA);
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}
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} else {
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switch (dev->mode) {
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case SMBUS_WRITE_DATA:
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smbus_do_write(dev);
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break;
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case SMBUS_READ_DATA:
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BADF("Unexpected stop during receive\n");
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break;
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default:
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/* Nothing to do. */
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break;
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}
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2007-05-23 04:03:59 +04:00
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}
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dev->mode = SMBUS_IDLE;
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dev->data_len = 0;
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break;
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case I2C_NACK:
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switch (dev->mode) {
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case SMBUS_DONE:
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/* Nothing to do. */
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break;
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2018-11-30 23:04:19 +03:00
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2007-05-23 04:03:59 +04:00
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case SMBUS_READ_DATA:
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dev->mode = SMBUS_DONE;
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break;
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2018-11-30 23:04:19 +03:00
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2007-05-23 04:03:59 +04:00
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default:
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BADF("Unexpected NACK in state %d\n", dev->mode);
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dev->mode = SMBUS_CONFUSED;
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break;
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}
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2022-06-30 10:21:14 +03:00
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break;
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default:
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return -1;
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2007-05-23 04:03:59 +04:00
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}
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2017-01-09 14:40:20 +03:00
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return 0;
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2007-05-23 04:03:59 +04:00
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}
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2018-11-14 20:50:50 +03:00
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static uint8_t smbus_i2c_recv(I2CSlave *s)
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2007-05-23 04:03:59 +04:00
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{
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2011-12-05 06:39:20 +04:00
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SMBusDevice *dev = SMBUS_DEVICE(s);
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SMBusDeviceClass *sc = SMBUS_DEVICE_GET_CLASS(dev);
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2018-11-30 22:49:31 +03:00
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uint8_t ret = 0xff;
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2007-05-23 04:03:59 +04:00
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switch (dev->mode) {
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2018-11-30 22:49:31 +03:00
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case SMBUS_READ_DATA:
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2011-12-05 06:39:20 +04:00
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if (sc->receive_byte) {
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ret = sc->receive_byte(dev);
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2007-05-23 04:03:59 +04:00
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}
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DPRINTF("Read data %02x\n", ret);
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break;
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2018-11-30 23:04:19 +03:00
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2007-05-23 04:03:59 +04:00
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default:
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BADF("Unexpected read in state %d\n", dev->mode);
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dev->mode = SMBUS_CONFUSED;
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break;
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}
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2018-11-30 23:04:19 +03:00
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2007-05-23 04:03:59 +04:00
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return ret;
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}
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2011-12-05 06:28:27 +04:00
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static int smbus_i2c_send(I2CSlave *s, uint8_t data)
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2007-05-23 04:03:59 +04:00
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{
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2011-12-05 06:39:20 +04:00
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SMBusDevice *dev = SMBUS_DEVICE(s);
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2009-05-15 01:35:08 +04:00
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2007-05-23 04:03:59 +04:00
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switch (dev->mode) {
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case SMBUS_WRITE_DATA:
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DPRINTF("Write data %02x\n", data);
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2018-12-03 15:52:50 +03:00
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if (dev->data_len >= sizeof(dev->data_buf)) {
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BADF("Too many bytes sent\n");
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} else {
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dev->data_buf[dev->data_len++] = data;
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}
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2007-05-23 04:03:59 +04:00
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break;
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2018-11-30 23:04:19 +03:00
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2007-05-23 04:03:59 +04:00
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default:
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BADF("Unexpected write in state %d\n", dev->mode);
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break;
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}
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2018-11-30 23:04:19 +03:00
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2007-05-23 04:03:59 +04:00
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return 0;
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}
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2011-12-05 06:39:20 +04:00
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static void smbus_device_class_init(ObjectClass *klass, void *data)
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{
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I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
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sc->event = smbus_i2c_event;
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sc->recv = smbus_i2c_recv;
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sc->send = smbus_i2c_send;
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}
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2017-12-07 18:34:59 +03:00
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bool smbus_vmstate_needed(SMBusDevice *dev)
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{
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return dev->mode != SMBUS_IDLE;
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}
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const VMStateDescription vmstate_smbus_device = {
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.name = TYPE_SMBUS_DEVICE,
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.version_id = 1,
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.minimum_version_id = 1,
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2023-12-21 06:16:11 +03:00
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.fields = (const VMStateField[]) {
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2017-12-07 18:34:59 +03:00
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VMSTATE_I2C_SLAVE(i2c, SMBusDevice),
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VMSTATE_INT32(mode, SMBusDevice),
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VMSTATE_INT32(data_len, SMBusDevice),
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VMSTATE_UINT8_ARRAY(data_buf, SMBusDevice, SMBUS_DATA_MAX_LEN),
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VMSTATE_END_OF_LIST()
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}
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};
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2013-01-10 19:19:07 +04:00
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static const TypeInfo smbus_device_type_info = {
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2011-12-05 06:39:20 +04:00
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.name = TYPE_SMBUS_DEVICE,
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.parent = TYPE_I2C_SLAVE,
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.instance_size = sizeof(SMBusDevice),
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.abstract = true,
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.class_size = sizeof(SMBusDeviceClass),
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.class_init = smbus_device_class_init,
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};
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2012-02-09 18:20:55 +04:00
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static void smbus_device_register_types(void)
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2011-12-05 06:39:20 +04:00
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{
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type_register_static(&smbus_device_type_info);
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}
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2012-02-09 18:20:55 +04:00
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type_init(smbus_device_register_types)
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