2017-10-01 23:11:45 +03:00
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/*
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* QEMU HPPA hardware system emulator.
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2023-10-14 08:06:04 +03:00
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* (C) Copyright 2018-2023 Helge Deller <deller@gmx.de>
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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2017-10-01 23:11:45 +03:00
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*/
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#include "qemu/osdep.h"
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2020-10-28 14:36:57 +03:00
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#include "qemu/datadir.h"
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2017-10-01 23:11:45 +03:00
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#include "cpu.h"
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#include "elf.h"
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#include "hw/loader.h"
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#include "qemu/error-report.h"
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2019-08-12 08:23:38 +03:00
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#include "sysemu/reset.h"
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2017-10-01 23:11:45 +03:00
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#include "sysemu/sysemu.h"
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2020-08-26 18:45:43 +03:00
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#include "sysemu/runstate.h"
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2019-10-04 02:03:53 +03:00
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#include "hw/rtc/mc146818rtc.h"
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2017-10-01 23:11:45 +03:00
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#include "hw/timer/i8254.h"
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#include "hw/char/serial.h"
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2022-05-04 12:25:44 +03:00
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#include "hw/char/parallel.h"
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2022-05-04 12:25:51 +03:00
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#include "hw/intc/i8259.h"
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2022-05-04 12:25:46 +03:00
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#include "hw/input/lasips2.h"
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2019-12-21 00:15:08 +03:00
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#include "hw/net/lasi_82596.h"
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2022-01-06 01:09:04 +03:00
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#include "hw/nmi.h"
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2023-10-14 08:47:05 +03:00
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#include "hw/usb.h"
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2022-05-04 12:25:51 +03:00
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#include "hw/pci/pci.h"
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2023-10-14 08:41:18 +03:00
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#include "hw/pci/pci_device.h"
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2023-10-14 08:47:05 +03:00
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#include "hw/pci-host/astro.h"
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2022-05-04 12:25:32 +03:00
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#include "hw/pci-host/dino.h"
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2022-05-04 12:25:52 +03:00
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#include "hw/misc/lasi.h"
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2022-05-04 12:25:57 +03:00
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#include "hppa_hardware.h"
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2018-06-25 15:42:11 +03:00
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#include "qemu/units.h"
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2017-10-01 23:11:45 +03:00
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#include "qapi/error.h"
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2019-12-12 19:15:43 +03:00
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#include "net/net.h"
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2018-02-04 09:41:41 +03:00
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#include "qemu/log.h"
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2017-10-01 23:11:45 +03:00
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2023-11-11 22:31:37 +03:00
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#define MIN_SEABIOS_HPPA_VERSION 12 /* require at least this fw version */
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2020-07-27 23:43:44 +03:00
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2024-01-03 22:10:01 +03:00
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#define HPA_POWER_BUTTON (FIRMWARE_END - 0x10)
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static hwaddr soft_power_reg;
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2020-08-26 18:45:43 +03:00
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2022-05-04 12:25:56 +03:00
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#define enable_lasi_lan() 0
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2023-10-14 08:41:18 +03:00
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static DeviceState *lasi_dev;
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2022-05-04 12:25:56 +03:00
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2020-08-26 18:45:43 +03:00
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static void hppa_powerdown_req(Notifier *n, void *opaque)
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{
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uint32_t val;
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val = ldl_be_phys(&address_space_memory, soft_power_reg);
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if ((val >> 8) == 0) {
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/* immediately shut down when under hardware control */
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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return;
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}
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/* clear bit 31 to indicate that the power switch was pressed. */
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val &= ~1;
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stl_be_phys(&address_space_memory, soft_power_reg, val);
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}
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static Notifier hppa_system_powerdown_notifier = {
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.notify = hppa_powerdown_req
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};
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2022-05-04 12:25:53 +03:00
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/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */
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static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size)
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{
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return 0;
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}
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static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size)
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{
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}
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static const MemoryRegionOps hppa_pci_ignore_ops = {
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.read = ignore_read,
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.write = ignore_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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2020-08-26 18:45:43 +03:00
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2023-09-18 04:17:31 +03:00
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static ISABus *hppa_isa_bus(hwaddr addr)
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2017-10-08 23:47:27 +03:00
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{
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ISABus *isa_bus;
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qemu_irq *isa_irqs;
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MemoryRegion *isa_region;
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isa_region = g_new(MemoryRegion, 1);
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memory_region_init_io(isa_region, NULL, &hppa_pci_ignore_ops,
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NULL, "isa-io", 0x800);
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2023-09-18 04:17:31 +03:00
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memory_region_add_subregion(get_system_memory(), addr, isa_region);
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2017-10-08 23:47:27 +03:00
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isa_bus = isa_bus_new(NULL, get_system_memory(), isa_region,
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&error_abort);
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2023-10-14 08:06:04 +03:00
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isa_irqs = i8259_init(isa_bus, NULL);
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2023-02-09 15:32:18 +03:00
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isa_bus_register_input_irqs(isa_bus, isa_irqs);
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2017-10-08 23:47:27 +03:00
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return isa_bus;
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}
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2023-10-14 08:25:02 +03:00
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/*
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* Helper functions to emulate RTC clock and DebugOutputPort
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*/
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static time_t rtc_ref;
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static uint64_t io_cpu_read(void *opaque, hwaddr addr, unsigned size)
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{
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uint64_t val = 0;
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switch (addr) {
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case 0: /* RTC clock */
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val = time(NULL);
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val += rtc_ref;
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break;
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case 8: /* DebugOutputPort */
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return 0xe9; /* readback */
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}
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return val;
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}
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static void io_cpu_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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unsigned char ch;
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Chardev *debugout;
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switch (addr) {
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case 0: /* RTC clock */
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rtc_ref = val - time(NULL);
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break;
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case 8: /* DebugOutputPort */
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ch = val;
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debugout = serial_hd(0);
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if (debugout) {
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qemu_chr_fe_write_all(debugout->be, &ch, 1);
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} else {
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fprintf(stderr, "%c", ch);
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}
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break;
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}
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}
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static const MemoryRegionOps hppa_io_helper_ops = {
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.read = io_cpu_read,
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.write = io_cpu_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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2023-09-18 04:17:31 +03:00
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typedef uint64_t TranslateFn(void *opaque, uint64_t addr);
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2023-10-14 08:25:02 +03:00
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2023-09-18 04:17:31 +03:00
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static uint64_t linux_kernel_virt_to_phys(void *opaque, uint64_t addr)
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2017-10-08 23:47:27 +03:00
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{
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addr &= (0x10000000 - 1);
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return addr;
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}
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2023-09-18 04:17:31 +03:00
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static uint64_t translate_pa10(void *dummy, uint64_t addr)
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{
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return (uint32_t)addr;
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}
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static uint64_t translate_pa20(void *dummy, uint64_t addr)
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{
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return hppa_abs_to_phys_pa2_w0(addr);
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}
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2017-10-08 23:47:27 +03:00
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static HPPACPU *cpu[HPPA_MAX_CPUS];
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static uint64_t firmware_entry;
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2017-10-01 23:11:45 +03:00
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2020-08-09 18:06:50 +03:00
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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{
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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2023-09-18 04:17:31 +03:00
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static FWCfgState *create_fw_cfg(MachineState *ms, PCIBus *pci_bus,
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hwaddr addr)
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2020-07-27 23:43:44 +03:00
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{
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FWCfgState *fw_cfg;
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uint64_t val;
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2023-06-24 01:28:44 +03:00
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const char qemu_version[] = QEMU_VERSION;
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2023-10-14 08:15:10 +03:00
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MachineClass *mc = MACHINE_GET_CLASS(ms);
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2023-10-13 03:46:55 +03:00
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int btlb_entries = HPPA_BTLB_ENTRIES(&cpu[0]->env);
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2023-10-14 08:15:10 +03:00
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int len;
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2020-07-27 23:43:44 +03:00
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2023-09-18 04:17:31 +03:00
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fw_cfg = fw_cfg_init_mem(addr, addr + 4);
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2020-07-27 23:43:44 +03:00
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fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS);
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2020-10-28 13:19:23 +03:00
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size);
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2020-07-27 23:43:44 +03:00
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val = cpu_to_le64(MIN_SEABIOS_HPPA_VERSION);
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fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version",
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g_memdup(&val, sizeof(val)), sizeof(val));
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2023-10-13 03:46:55 +03:00
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val = cpu_to_le64(HPPA_TLB_ENTRIES - btlb_entries);
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2020-08-27 14:10:32 +03:00
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fw_cfg_add_file(fw_cfg, "/etc/cpu/tlb_entries",
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g_memdup(&val, sizeof(val)), sizeof(val));
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2023-10-13 03:46:55 +03:00
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val = cpu_to_le64(btlb_entries);
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2023-10-14 08:15:10 +03:00
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fw_cfg_add_file(fw_cfg, "/etc/cpu/btlb_entries",
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g_memdup(&val, sizeof(val)), sizeof(val));
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len = strlen(mc->name) + 1;
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fw_cfg_add_file(fw_cfg, "/etc/hppa/machine",
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g_memdup(mc->name, len), len);
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2024-01-03 22:10:01 +03:00
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val = cpu_to_le64(soft_power_reg);
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2023-10-14 08:15:10 +03:00
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fw_cfg_add_file(fw_cfg, "/etc/hppa/power-button-addr",
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g_memdup(&val, sizeof(val)), sizeof(val));
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2023-10-14 08:25:02 +03:00
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val = cpu_to_le64(CPU_HPA + 16);
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fw_cfg_add_file(fw_cfg, "/etc/hppa/rtc-addr",
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g_memdup(&val, sizeof(val)), sizeof(val));
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2023-10-14 08:15:10 +03:00
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val = cpu_to_le64(CPU_HPA + 24);
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fw_cfg_add_file(fw_cfg, "/etc/hppa/DebugOutputPort",
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2020-08-26 18:45:43 +03:00
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g_memdup(&val, sizeof(val)), sizeof(val));
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2022-04-14 19:52:56 +03:00
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fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ms->boot_config.order[0]);
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2020-08-09 18:06:50 +03:00
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qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
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2023-06-24 01:28:44 +03:00
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fw_cfg_add_file(fw_cfg, "/etc/qemu-version",
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g_memdup(qemu_version, sizeof(qemu_version)),
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sizeof(qemu_version));
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2023-10-14 08:15:10 +03:00
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fw_cfg_add_extra_pci_roots(pci_bus, fw_cfg);
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2020-07-27 23:43:44 +03:00
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return fw_cfg;
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}
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2022-05-04 12:25:48 +03:00
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static LasiState *lasi_init(void)
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{
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DeviceState *dev;
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dev = qdev_new(TYPE_LASI_CHIP);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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return LASI_CHIP(dev);
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}
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2022-05-04 12:25:29 +03:00
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static DinoState *dino_init(MemoryRegion *addr_space)
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{
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DeviceState *dev;
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dev = qdev_new(TYPE_DINO_PCI_HOST_BRIDGE);
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object_property_set_link(OBJECT(dev), "memory-as", OBJECT(addr_space),
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&error_fatal);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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return DINO_PCI_HOST_BRIDGE(dev);
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}
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2023-10-14 08:41:18 +03:00
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/*
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* Step 1: Create CPUs and Memory
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*/
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2023-09-18 04:17:31 +03:00
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static TranslateFn *machine_HP_common_init_cpus(MachineState *machine)
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2017-10-01 23:11:45 +03:00
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{
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2017-10-08 23:47:27 +03:00
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MemoryRegion *addr_space = get_system_memory();
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2019-05-18 23:54:27 +03:00
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unsigned int smp_cpus = machine->smp.cpus;
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2023-09-18 04:17:31 +03:00
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TranslateFn *translate;
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MemoryRegion *cpu_region;
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2023-12-31 11:36:58 +03:00
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uint64_t ram_max;
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2017-10-08 23:47:27 +03:00
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/* Create CPUs. */
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2023-09-18 04:17:31 +03:00
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for (unsigned int i = 0; i < smp_cpus; i++) {
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2017-10-08 23:47:27 +03:00
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cpu[i] = HPPA_CPU(cpu_create(machine->cpu_type));
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2023-09-18 04:17:31 +03:00
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}
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/*
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* For now, treat address layout as if PSW_W is clear.
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* TODO: create a proper hppa64 board model and load elf64 firmware.
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*/
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if (hppa_is_pa20(&cpu[0]->env)) {
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translate = translate_pa20;
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2023-12-31 11:36:58 +03:00
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ram_max = 0xf0000000; /* 3.75 GB (limited by 32-bit firmware) */
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2023-09-18 04:17:31 +03:00
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} else {
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translate = translate_pa10;
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2023-12-31 11:36:58 +03:00
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|
|
ram_max = 0xf0000000; /* 3.75 GB (32-bit CPU) */
|
2023-09-18 04:17:31 +03:00
|
|
|
}
|
|
|
|
|
2024-01-03 22:10:01 +03:00
|
|
|
soft_power_reg = translate(NULL, HPA_POWER_BUTTON);
|
|
|
|
|
2023-09-18 04:17:31 +03:00
|
|
|
for (unsigned int i = 0; i < smp_cpus; i++) {
|
|
|
|
g_autofree char *name = g_strdup_printf("cpu%u-io-eir", i);
|
2017-10-08 23:47:27 +03:00
|
|
|
|
|
|
|
cpu_region = g_new(MemoryRegion, 1);
|
|
|
|
memory_region_init_io(cpu_region, OBJECT(cpu[i]), &hppa_io_eir_ops,
|
2019-10-01 16:36:24 +03:00
|
|
|
cpu[i], name, 4);
|
2023-09-18 04:17:31 +03:00
|
|
|
memory_region_add_subregion(addr_space,
|
|
|
|
translate(NULL, CPU_HPA + i * 0x1000),
|
2017-10-08 23:47:27 +03:00
|
|
|
cpu_region);
|
|
|
|
}
|
|
|
|
|
2023-10-14 08:25:02 +03:00
|
|
|
/* RTC and DebugOutputPort on CPU #0 */
|
|
|
|
cpu_region = g_new(MemoryRegion, 1);
|
|
|
|
memory_region_init_io(cpu_region, OBJECT(cpu[0]), &hppa_io_helper_ops,
|
|
|
|
cpu[0], "cpu0-io-rtc", 2 * sizeof(uint64_t));
|
2023-09-18 04:17:31 +03:00
|
|
|
memory_region_add_subregion(addr_space, translate(NULL, CPU_HPA + 16),
|
|
|
|
cpu_region);
|
2023-10-14 08:25:02 +03:00
|
|
|
|
2017-10-08 23:47:27 +03:00
|
|
|
/* Main memory region. */
|
2023-12-31 11:36:58 +03:00
|
|
|
if (machine->ram_size > ram_max) {
|
|
|
|
info_report("Max RAM size limited to %" PRIu64 " MB", ram_max / MiB);
|
|
|
|
machine->ram_size = ram_max;
|
2020-01-09 03:05:24 +03:00
|
|
|
}
|
2020-02-19 19:09:15 +03:00
|
|
|
memory_region_add_subregion_overlap(addr_space, 0, machine->ram, -1);
|
2023-09-18 04:17:31 +03:00
|
|
|
|
|
|
|
return translate;
|
2023-10-14 08:41:18 +03:00
|
|
|
}
|
2020-02-19 19:09:15 +03:00
|
|
|
|
2023-10-14 08:41:18 +03:00
|
|
|
/*
|
|
|
|
* Last creation step: Add SCSI discs, NICs, graphics & load firmware
|
|
|
|
*/
|
2023-09-18 04:17:31 +03:00
|
|
|
static void machine_HP_common_init_tail(MachineState *machine, PCIBus *pci_bus,
|
|
|
|
TranslateFn *translate)
|
2023-10-14 08:41:18 +03:00
|
|
|
{
|
|
|
|
const char *kernel_filename = machine->kernel_filename;
|
|
|
|
const char *kernel_cmdline = machine->kernel_cmdline;
|
|
|
|
const char *initrd_filename = machine->initrd_filename;
|
|
|
|
MachineClass *mc = MACHINE_GET_CLASS(machine);
|
|
|
|
DeviceState *dev;
|
2023-10-14 08:47:05 +03:00
|
|
|
PCIDevice *pci_dev;
|
2023-10-14 08:41:18 +03:00
|
|
|
char *firmware_filename;
|
|
|
|
uint64_t firmware_low, firmware_high;
|
|
|
|
long size;
|
|
|
|
uint64_t kernel_entry = 0, kernel_low, kernel_high;
|
|
|
|
MemoryRegion *addr_space = get_system_memory();
|
|
|
|
MemoryRegion *rom_region;
|
|
|
|
long i;
|
|
|
|
unsigned int smp_cpus = machine->smp.cpus;
|
|
|
|
SysBusDevice *s;
|
2020-07-27 23:43:44 +03:00
|
|
|
|
2017-10-08 23:47:27 +03:00
|
|
|
/* SCSI disk setup. */
|
2024-01-01 23:47:30 +03:00
|
|
|
if (drive_get_max_bus(IF_SCSI) >= 0) {
|
|
|
|
dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a"));
|
|
|
|
lsi53c8xx_handle_legacy_cmdline(dev);
|
|
|
|
}
|
2017-10-08 23:47:27 +03:00
|
|
|
|
2019-12-21 00:15:11 +03:00
|
|
|
/* Graphics setup. */
|
|
|
|
if (machine->enable_graphics && vga_interface_type != VGA_NONE) {
|
2022-05-01 15:25:05 +03:00
|
|
|
vga_interface_created = true;
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:31:58 +03:00
|
|
|
dev = qdev_new("artist");
|
2019-12-21 00:15:11 +03:00
|
|
|
s = SYS_BUS_DEVICE(dev);
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:32:34 +03:00
|
|
|
sysbus_realize_and_unref(s, &error_fatal);
|
2023-09-18 04:17:31 +03:00
|
|
|
sysbus_mmio_map(s, 0, translate(NULL, LASI_GFX_HPA));
|
|
|
|
sysbus_mmio_map(s, 1, translate(NULL, ARTIST_FB_ADDR));
|
2019-12-21 00:15:11 +03:00
|
|
|
}
|
|
|
|
|
2019-12-22 01:25:30 +03:00
|
|
|
/* Network setup. */
|
2024-01-01 23:47:30 +03:00
|
|
|
if (nd_table[0].used && enable_lasi_lan()) {
|
2023-09-18 04:17:31 +03:00
|
|
|
lasi_82596_init(addr_space, translate(NULL, LASI_LAN_HPA),
|
2022-05-04 12:25:43 +03:00
|
|
|
qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA));
|
|
|
|
}
|
|
|
|
|
2017-10-08 23:47:27 +03:00
|
|
|
for (i = 0; i < nb_nics; i++) {
|
2019-12-21 00:15:08 +03:00
|
|
|
if (!enable_lasi_lan()) {
|
2023-05-23 14:04:31 +03:00
|
|
|
pci_nic_init_nofail(&nd_table[i], pci_bus, mc->default_nic, NULL);
|
2019-12-21 00:15:08 +03:00
|
|
|
}
|
2017-10-08 23:47:27 +03:00
|
|
|
}
|
|
|
|
|
2023-10-14 08:47:05 +03:00
|
|
|
/* BMC board: HP Powerbar SP2 Diva (with console only) */
|
|
|
|
pci_dev = pci_new(-1, "pci-serial");
|
|
|
|
if (!lasi_dev) {
|
|
|
|
/* bind default keyboard/serial to Diva card */
|
|
|
|
qdev_prop_set_chr(DEVICE(pci_dev), "chardev", serial_hd(0));
|
|
|
|
}
|
|
|
|
qdev_prop_set_uint8(DEVICE(pci_dev), "prog_if", 0);
|
|
|
|
pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
|
|
|
|
pci_config_set_vendor_id(pci_dev->config, PCI_VENDOR_ID_HP);
|
|
|
|
pci_config_set_device_id(pci_dev->config, 0x1048);
|
|
|
|
pci_set_word(&pci_dev->config[PCI_SUBSYSTEM_VENDOR_ID], PCI_VENDOR_ID_HP);
|
|
|
|
pci_set_word(&pci_dev->config[PCI_SUBSYSTEM_ID], 0x1227); /* Powerbar */
|
|
|
|
|
|
|
|
/* create a second serial PCI card when running Astro */
|
2024-01-01 23:47:30 +03:00
|
|
|
if (serial_hd(1) && !lasi_dev) {
|
2023-10-14 08:47:05 +03:00
|
|
|
pci_dev = pci_new(-1, "pci-serial-4x");
|
|
|
|
qdev_prop_set_chr(DEVICE(pci_dev), "chardev1", serial_hd(1));
|
|
|
|
qdev_prop_set_chr(DEVICE(pci_dev), "chardev2", serial_hd(2));
|
|
|
|
qdev_prop_set_chr(DEVICE(pci_dev), "chardev3", serial_hd(3));
|
|
|
|
qdev_prop_set_chr(DEVICE(pci_dev), "chardev4", serial_hd(4));
|
|
|
|
pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* create USB OHCI controller for USB keyboard & mouse on Astro machines */
|
|
|
|
if (!lasi_dev && machine->enable_graphics) {
|
|
|
|
pci_create_simple(pci_bus, -1, "pci-ohci");
|
|
|
|
usb_create_simple(usb_bus_find(-1), "usb-kbd");
|
|
|
|
usb_create_simple(usb_bus_find(-1), "usb-mouse");
|
|
|
|
}
|
|
|
|
|
2020-08-26 18:45:43 +03:00
|
|
|
/* register power switch emulation */
|
|
|
|
qemu_register_powerdown_notifier(&hppa_system_powerdown_notifier);
|
|
|
|
|
2023-10-14 08:41:18 +03:00
|
|
|
/* fw_cfg configuration interface */
|
2023-09-18 04:17:31 +03:00
|
|
|
create_fw_cfg(machine, pci_bus, translate(NULL, FW_CFG_IO_BASE));
|
2023-10-14 08:41:18 +03:00
|
|
|
|
2017-10-08 23:47:27 +03:00
|
|
|
/* Load firmware. Given that this is not "real" firmware,
|
|
|
|
but one explicitly written for the emulation, we might as
|
|
|
|
well load it directly from an ELF image. */
|
|
|
|
firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
|
2020-10-26 17:30:17 +03:00
|
|
|
machine->firmware ?: "hppa-firmware.img");
|
2017-10-08 23:47:27 +03:00
|
|
|
if (firmware_filename == NULL) {
|
|
|
|
error_report("no firmware provided");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2023-09-18 04:17:31 +03:00
|
|
|
size = load_elf(firmware_filename, NULL, translate, NULL,
|
2020-01-27 01:55:04 +03:00
|
|
|
&firmware_entry, &firmware_low, &firmware_high, NULL,
|
2017-10-08 23:47:27 +03:00
|
|
|
true, EM_PARISC, 0, 0);
|
|
|
|
|
|
|
|
if (size < 0) {
|
|
|
|
error_report("could not load firmware '%s'", firmware_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
2018-02-04 09:41:41 +03:00
|
|
|
qemu_log_mask(CPU_LOG_PAGE, "Firmware loaded at 0x%08" PRIx64
|
|
|
|
"-0x%08" PRIx64 ", entry at 0x%08" PRIx64 ".\n",
|
|
|
|
firmware_low, firmware_high, firmware_entry);
|
2023-09-18 04:17:31 +03:00
|
|
|
if (firmware_low < translate(NULL, FIRMWARE_START) ||
|
|
|
|
firmware_high >= translate(NULL, FIRMWARE_END)) {
|
2017-10-08 23:47:27 +03:00
|
|
|
error_report("Firmware overlaps with memory or IO space");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
g_free(firmware_filename);
|
|
|
|
|
|
|
|
rom_region = g_new(MemoryRegion, 1);
|
2019-10-08 14:33:18 +03:00
|
|
|
memory_region_init_ram(rom_region, NULL, "firmware",
|
|
|
|
(FIRMWARE_END - FIRMWARE_START), &error_fatal);
|
2023-09-18 04:17:31 +03:00
|
|
|
memory_region_add_subregion(addr_space,
|
|
|
|
translate(NULL, FIRMWARE_START), rom_region);
|
2017-10-08 23:47:27 +03:00
|
|
|
|
|
|
|
/* Load kernel */
|
|
|
|
if (kernel_filename) {
|
2023-09-18 04:17:31 +03:00
|
|
|
size = load_elf(kernel_filename, NULL, linux_kernel_virt_to_phys,
|
2020-01-27 01:55:04 +03:00
|
|
|
NULL, &kernel_entry, &kernel_low, &kernel_high, NULL,
|
2017-10-08 23:47:27 +03:00
|
|
|
true, EM_PARISC, 0, 0);
|
|
|
|
|
2023-09-18 04:17:31 +03:00
|
|
|
kernel_entry = linux_kernel_virt_to_phys(NULL, kernel_entry);
|
2017-10-08 23:47:27 +03:00
|
|
|
|
|
|
|
if (size < 0) {
|
|
|
|
error_report("could not load kernel '%s'", kernel_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
2018-02-04 09:41:41 +03:00
|
|
|
qemu_log_mask(CPU_LOG_PAGE, "Kernel loaded at 0x%08" PRIx64
|
|
|
|
"-0x%08" PRIx64 ", entry at 0x%08" PRIx64
|
2018-06-25 15:42:11 +03:00
|
|
|
", size %" PRIu64 " kB\n",
|
|
|
|
kernel_low, kernel_high, kernel_entry, size / KiB);
|
2017-10-08 23:47:27 +03:00
|
|
|
|
|
|
|
if (kernel_cmdline) {
|
|
|
|
cpu[0]->env.gr[24] = 0x4000;
|
|
|
|
pstrcpy_targphys("cmdline", cpu[0]->env.gr[24],
|
|
|
|
TARGET_PAGE_SIZE, kernel_cmdline);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (initrd_filename) {
|
|
|
|
ram_addr_t initrd_base;
|
2018-09-13 13:07:13 +03:00
|
|
|
int64_t initrd_size;
|
2017-10-08 23:47:27 +03:00
|
|
|
|
|
|
|
initrd_size = get_image_size(initrd_filename);
|
|
|
|
if (initrd_size < 0) {
|
|
|
|
error_report("could not load initial ram disk '%s'",
|
|
|
|
initrd_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Load the initrd image high in memory.
|
|
|
|
Mirror the algorithm used by palo:
|
|
|
|
(1) Due to sign-extension problems and PDC,
|
|
|
|
put the initrd no higher than 1G.
|
|
|
|
(2) Reserve 64k for stack. */
|
2020-10-28 13:19:23 +03:00
|
|
|
initrd_base = MIN(machine->ram_size, 1 * GiB);
|
2018-06-25 15:42:11 +03:00
|
|
|
initrd_base = initrd_base - 64 * KiB;
|
2017-10-08 23:47:27 +03:00
|
|
|
initrd_base = (initrd_base - initrd_size) & TARGET_PAGE_MASK;
|
|
|
|
|
|
|
|
if (initrd_base < kernel_high) {
|
|
|
|
error_report("kernel and initial ram disk too large!");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
load_image_targphys(initrd_filename, initrd_base, initrd_size);
|
|
|
|
cpu[0]->env.gr[23] = initrd_base;
|
|
|
|
cpu[0]->env.gr[22] = initrd_base + initrd_size;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!kernel_entry) {
|
|
|
|
/* When booting via firmware, tell firmware if we want interactive
|
|
|
|
* mode (kernel_entry=1), and to boot from CD (gr[24]='d')
|
|
|
|
* or hard disc * (gr[24]='c').
|
|
|
|
*/
|
2022-04-14 19:52:56 +03:00
|
|
|
kernel_entry = machine->boot_config.has_menu ? machine->boot_config.menu : 0;
|
|
|
|
cpu[0]->env.gr[24] = machine->boot_config.order[0];
|
2017-10-08 23:47:27 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* We jump to the firmware entry routine and pass the
|
|
|
|
* various parameters in registers. After firmware initialization,
|
|
|
|
* firmware will start the Linux kernel with ramdisk and cmdline.
|
|
|
|
*/
|
2020-10-28 13:19:23 +03:00
|
|
|
cpu[0]->env.gr[26] = machine->ram_size;
|
2017-10-08 23:47:27 +03:00
|
|
|
cpu[0]->env.gr[25] = kernel_entry;
|
|
|
|
|
|
|
|
/* tell firmware how many SMP CPUs to present in inventory table */
|
|
|
|
cpu[0]->env.gr[21] = smp_cpus;
|
2020-09-02 22:21:01 +03:00
|
|
|
|
|
|
|
/* tell firmware fw_cfg port */
|
|
|
|
cpu[0]->env.gr[19] = FW_CFG_IO_BASE;
|
2017-10-01 23:11:45 +03:00
|
|
|
}
|
|
|
|
|
2023-10-14 08:41:18 +03:00
|
|
|
/*
|
|
|
|
* Create HP B160L workstation
|
|
|
|
*/
|
|
|
|
static void machine_HP_B160L_init(MachineState *machine)
|
|
|
|
{
|
|
|
|
DeviceState *dev, *dino_dev;
|
|
|
|
MemoryRegion *addr_space = get_system_memory();
|
2023-09-18 04:17:31 +03:00
|
|
|
TranslateFn *translate;
|
2023-10-14 08:41:18 +03:00
|
|
|
ISABus *isa_bus;
|
|
|
|
PCIBus *pci_bus;
|
|
|
|
|
|
|
|
/* Create CPUs and RAM. */
|
2023-09-18 04:17:31 +03:00
|
|
|
translate = machine_HP_common_init_cpus(machine);
|
2023-10-14 08:41:18 +03:00
|
|
|
|
2023-10-25 21:10:21 +03:00
|
|
|
if (hppa_is_pa20(&cpu[0]->env)) {
|
|
|
|
error_report("The HP B160L workstation requires a 32-bit "
|
|
|
|
"CPU. Use '-machine C3700' instead.");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2023-10-14 08:41:18 +03:00
|
|
|
/* Init Lasi chip */
|
|
|
|
lasi_dev = DEVICE(lasi_init());
|
2023-09-18 04:17:31 +03:00
|
|
|
memory_region_add_subregion(addr_space, translate(NULL, LASI_HPA),
|
2023-10-14 08:41:18 +03:00
|
|
|
sysbus_mmio_get_region(
|
|
|
|
SYS_BUS_DEVICE(lasi_dev), 0));
|
|
|
|
|
|
|
|
/* Init Dino (PCI host bus chip). */
|
|
|
|
dino_dev = DEVICE(dino_init(addr_space));
|
2023-09-18 04:17:31 +03:00
|
|
|
memory_region_add_subregion(addr_space, translate(NULL, DINO_HPA),
|
2023-10-14 08:41:18 +03:00
|
|
|
sysbus_mmio_get_region(
|
|
|
|
SYS_BUS_DEVICE(dino_dev), 0));
|
|
|
|
pci_bus = PCI_BUS(qdev_get_child_bus(dino_dev, "pci"));
|
|
|
|
assert(pci_bus);
|
|
|
|
|
|
|
|
/* Create ISA bus, needed for PS/2 kbd/mouse port emulation */
|
2023-09-18 04:17:31 +03:00
|
|
|
isa_bus = hppa_isa_bus(translate(NULL, IDE_HPA));
|
2023-10-14 08:41:18 +03:00
|
|
|
assert(isa_bus);
|
|
|
|
|
|
|
|
/* Serial ports: Lasi and Dino use a 7.272727 MHz clock. */
|
2023-09-18 04:17:31 +03:00
|
|
|
serial_mm_init(addr_space, translate(NULL, LASI_UART_HPA + 0x800), 0,
|
2023-10-14 08:41:18 +03:00
|
|
|
qdev_get_gpio_in(lasi_dev, LASI_IRQ_UART_HPA), 7272727 / 16,
|
|
|
|
serial_hd(0), DEVICE_BIG_ENDIAN);
|
|
|
|
|
2023-09-18 04:17:31 +03:00
|
|
|
serial_mm_init(addr_space, translate(NULL, DINO_UART_HPA + 0x800), 0,
|
2023-10-14 08:41:18 +03:00
|
|
|
qdev_get_gpio_in(dino_dev, DINO_IRQ_RS232INT), 7272727 / 16,
|
|
|
|
serial_hd(1), DEVICE_BIG_ENDIAN);
|
|
|
|
|
|
|
|
/* Parallel port */
|
2023-09-18 04:17:31 +03:00
|
|
|
parallel_mm_init(addr_space, translate(NULL, LASI_LPT_HPA + 0x800), 0,
|
2023-10-14 08:41:18 +03:00
|
|
|
qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA),
|
|
|
|
parallel_hds[0]);
|
|
|
|
|
|
|
|
/* PS/2 Keyboard/Mouse */
|
|
|
|
dev = qdev_new(TYPE_LASIPS2);
|
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
|
|
|
|
qdev_get_gpio_in(lasi_dev, LASI_IRQ_PS2KBD_HPA));
|
2023-09-18 04:17:31 +03:00
|
|
|
memory_region_add_subregion(addr_space,
|
|
|
|
translate(NULL, LASI_PS2KBD_HPA),
|
2023-10-14 08:41:18 +03:00
|
|
|
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
|
|
|
|
0));
|
2023-09-18 04:17:31 +03:00
|
|
|
memory_region_add_subregion(addr_space,
|
|
|
|
translate(NULL, LASI_PS2KBD_HPA + 0x100),
|
2023-10-14 08:41:18 +03:00
|
|
|
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
|
|
|
|
1));
|
|
|
|
|
|
|
|
/* Add SCSI discs, NICs, graphics & load firmware */
|
2023-09-18 04:17:31 +03:00
|
|
|
machine_HP_common_init_tail(machine, pci_bus, translate);
|
2023-10-14 08:41:18 +03:00
|
|
|
}
|
|
|
|
|
2023-10-14 08:47:05 +03:00
|
|
|
static AstroState *astro_init(void)
|
|
|
|
{
|
|
|
|
DeviceState *dev;
|
|
|
|
|
|
|
|
dev = qdev_new(TYPE_ASTRO_CHIP);
|
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
|
|
|
|
|
|
return ASTRO_CHIP(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Create HP C3700 workstation
|
|
|
|
*/
|
|
|
|
static void machine_HP_C3700_init(MachineState *machine)
|
|
|
|
{
|
|
|
|
PCIBus *pci_bus;
|
|
|
|
AstroState *astro;
|
|
|
|
DeviceState *astro_dev;
|
|
|
|
MemoryRegion *addr_space = get_system_memory();
|
2023-09-18 04:17:31 +03:00
|
|
|
TranslateFn *translate;
|
2023-10-14 08:47:05 +03:00
|
|
|
|
|
|
|
/* Create CPUs and RAM. */
|
2023-09-18 04:17:31 +03:00
|
|
|
translate = machine_HP_common_init_cpus(machine);
|
2023-10-14 08:47:05 +03:00
|
|
|
|
2023-10-25 21:10:21 +03:00
|
|
|
if (!hppa_is_pa20(&cpu[0]->env)) {
|
|
|
|
error_report("The HP C3000 workstation requires a 64-bit CPU. "
|
|
|
|
"Use '-machine B160L' instead.");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2023-10-14 08:47:05 +03:00
|
|
|
/* Init Astro and the Elroys (PCI host bus chips). */
|
|
|
|
astro = astro_init();
|
|
|
|
astro_dev = DEVICE(astro);
|
2023-09-18 04:17:31 +03:00
|
|
|
memory_region_add_subregion(addr_space, translate(NULL, ASTRO_HPA),
|
2023-10-14 08:47:05 +03:00
|
|
|
sysbus_mmio_get_region(
|
|
|
|
SYS_BUS_DEVICE(astro_dev), 0));
|
|
|
|
pci_bus = PCI_BUS(qdev_get_child_bus(DEVICE(astro->elroy[0]), "pci"));
|
|
|
|
assert(pci_bus);
|
|
|
|
|
|
|
|
/* Add SCSI discs, NICs, graphics & load firmware */
|
2023-09-18 04:17:31 +03:00
|
|
|
machine_HP_common_init_tail(machine, pci_bus, translate);
|
2023-10-14 08:47:05 +03:00
|
|
|
}
|
|
|
|
|
2022-10-25 03:43:17 +03:00
|
|
|
static void hppa_machine_reset(MachineState *ms, ShutdownCause reason)
|
2017-10-08 23:47:27 +03:00
|
|
|
{
|
2019-05-18 23:54:27 +03:00
|
|
|
unsigned int smp_cpus = ms->smp.cpus;
|
2017-10-08 23:47:27 +03:00
|
|
|
int i;
|
|
|
|
|
2022-10-25 03:43:17 +03:00
|
|
|
qemu_devices_reset(reason);
|
2017-10-08 23:47:27 +03:00
|
|
|
|
|
|
|
/* Start all CPUs at the firmware entry point.
|
|
|
|
* Monarch CPU will initialize firmware, secondary CPUs
|
2023-06-23 09:24:30 +03:00
|
|
|
* will enter a small idle loop and wait for rendevouz. */
|
2017-10-08 23:47:27 +03:00
|
|
|
for (i = 0; i < smp_cpus; i++) {
|
2023-06-23 09:24:30 +03:00
|
|
|
CPUState *cs = CPU(cpu[i]);
|
|
|
|
|
|
|
|
cpu_set_pc(cs, firmware_entry);
|
|
|
|
cpu[i]->env.psw = PSW_Q;
|
2017-10-08 23:47:27 +03:00
|
|
|
cpu[i]->env.gr[5] = CPU_HPA + i * 0x1000;
|
2023-06-23 09:24:30 +03:00
|
|
|
|
|
|
|
cs->exception_index = -1;
|
|
|
|
cs->halted = 0;
|
2017-10-08 23:47:27 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* already initialized by machine_hppa_init()? */
|
2020-10-28 13:19:23 +03:00
|
|
|
if (cpu[0]->env.gr[26] == ms->ram_size) {
|
2017-10-08 23:47:27 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-10-28 13:19:23 +03:00
|
|
|
cpu[0]->env.gr[26] = ms->ram_size;
|
2017-10-08 23:47:27 +03:00
|
|
|
cpu[0]->env.gr[25] = 0; /* no firmware boot menu */
|
|
|
|
cpu[0]->env.gr[24] = 'c';
|
|
|
|
/* gr22/gr23 unused, no initrd while reboot. */
|
|
|
|
cpu[0]->env.gr[21] = smp_cpus;
|
2020-09-02 22:21:01 +03:00
|
|
|
/* tell firmware fw_cfg port */
|
|
|
|
cpu[0]->env.gr[19] = FW_CFG_IO_BASE;
|
2017-10-08 23:47:27 +03:00
|
|
|
}
|
|
|
|
|
2022-01-06 01:09:04 +03:00
|
|
|
static void hppa_nmi(NMIState *n, int cpu_index, Error **errp)
|
|
|
|
{
|
|
|
|
CPUState *cs;
|
|
|
|
|
|
|
|
CPU_FOREACH(cs) {
|
|
|
|
cpu_interrupt(cs, CPU_INTERRUPT_NMI);
|
|
|
|
}
|
|
|
|
}
|
2017-10-08 23:47:27 +03:00
|
|
|
|
2023-10-14 08:41:18 +03:00
|
|
|
static void HP_B160L_machine_init_class_init(ObjectClass *oc, void *data)
|
2017-10-01 23:11:45 +03:00
|
|
|
{
|
2023-11-17 10:17:01 +03:00
|
|
|
static const char * const valid_cpu_types[] = {
|
|
|
|
TYPE_HPPA_CPU,
|
|
|
|
NULL
|
|
|
|
};
|
2022-05-04 12:25:59 +03:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
NMIClass *nc = NMI_CLASS(oc);
|
|
|
|
|
2023-10-14 08:41:18 +03:00
|
|
|
mc->desc = "HP B160L workstation";
|
2017-10-08 23:47:27 +03:00
|
|
|
mc->default_cpu_type = TYPE_HPPA_CPU;
|
2023-11-17 10:17:01 +03:00
|
|
|
mc->valid_cpu_types = valid_cpu_types;
|
2023-10-14 08:41:18 +03:00
|
|
|
mc->init = machine_HP_B160L_init;
|
2017-10-08 23:47:27 +03:00
|
|
|
mc->reset = hppa_machine_reset;
|
2017-10-01 23:11:45 +03:00
|
|
|
mc->block_default_type = IF_SCSI;
|
2017-10-08 23:47:27 +03:00
|
|
|
mc->max_cpus = HPPA_MAX_CPUS;
|
|
|
|
mc->default_cpus = 1;
|
2020-02-07 19:19:47 +03:00
|
|
|
mc->is_default = true;
|
2018-06-25 15:41:57 +03:00
|
|
|
mc->default_ram_size = 512 * MiB;
|
2017-10-01 23:11:45 +03:00
|
|
|
mc->default_boot_order = "cd";
|
2020-02-19 19:09:15 +03:00
|
|
|
mc->default_ram_id = "ram";
|
2023-05-23 14:04:31 +03:00
|
|
|
mc->default_nic = "tulip";
|
2017-10-01 23:11:45 +03:00
|
|
|
|
2022-01-06 01:09:04 +03:00
|
|
|
nc->nmi_monitor_handler = hppa_nmi;
|
|
|
|
}
|
|
|
|
|
2023-10-14 08:41:18 +03:00
|
|
|
static const TypeInfo HP_B160L_machine_init_typeinfo = {
|
|
|
|
.name = MACHINE_TYPE_NAME("B160L"),
|
2022-05-04 12:25:58 +03:00
|
|
|
.parent = TYPE_MACHINE,
|
2023-10-14 08:41:18 +03:00
|
|
|
.class_init = HP_B160L_machine_init_class_init,
|
2022-01-06 01:09:04 +03:00
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ TYPE_NMI },
|
|
|
|
{ }
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2023-10-14 08:47:05 +03:00
|
|
|
static void HP_C3700_machine_init_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
2023-11-17 10:17:01 +03:00
|
|
|
static const char * const valid_cpu_types[] = {
|
|
|
|
TYPE_HPPA64_CPU,
|
|
|
|
NULL
|
|
|
|
};
|
2023-10-14 08:47:05 +03:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
NMIClass *nc = NMI_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "HP C3700 workstation";
|
2023-10-21 14:40:55 +03:00
|
|
|
mc->default_cpu_type = TYPE_HPPA64_CPU;
|
2023-11-17 10:17:01 +03:00
|
|
|
mc->valid_cpu_types = valid_cpu_types;
|
2023-10-14 08:47:05 +03:00
|
|
|
mc->init = machine_HP_C3700_init;
|
|
|
|
mc->reset = hppa_machine_reset;
|
|
|
|
mc->block_default_type = IF_SCSI;
|
|
|
|
mc->max_cpus = HPPA_MAX_CPUS;
|
|
|
|
mc->default_cpus = 1;
|
|
|
|
mc->is_default = false;
|
|
|
|
mc->default_ram_size = 1024 * MiB;
|
|
|
|
mc->default_boot_order = "cd";
|
|
|
|
mc->default_ram_id = "ram";
|
|
|
|
mc->default_nic = "tulip";
|
|
|
|
|
|
|
|
nc->nmi_monitor_handler = hppa_nmi;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo HP_C3700_machine_init_typeinfo = {
|
|
|
|
.name = MACHINE_TYPE_NAME("C3700"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = HP_C3700_machine_init_class_init,
|
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ TYPE_NMI },
|
|
|
|
{ }
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2022-05-04 12:26:00 +03:00
|
|
|
static void hppa_machine_init_register_types(void)
|
2022-01-06 01:09:04 +03:00
|
|
|
{
|
2023-10-14 08:41:18 +03:00
|
|
|
type_register_static(&HP_B160L_machine_init_typeinfo);
|
2023-10-14 08:47:05 +03:00
|
|
|
type_register_static(&HP_C3700_machine_init_typeinfo);
|
2022-01-06 01:09:04 +03:00
|
|
|
}
|
|
|
|
|
2022-05-04 12:26:00 +03:00
|
|
|
type_init(hppa_machine_init_register_types)
|