2009-03-02 19:42:04 +03:00
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#if !defined(__OPENPIC_H__)
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#define __OPENPIC_H__
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/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
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enum {
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OPENPIC_OUTPUT_INT = 0, /* IRQ */
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OPENPIC_OUTPUT_CINT, /* critical IRQ */
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OPENPIC_OUTPUT_MCK, /* Machine check event */
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OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
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OPENPIC_OUTPUT_RESET, /* Core reset event */
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OPENPIC_OUTPUT_NB,
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};
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2012-12-08 08:17:14 +04:00
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#define OPENPIC_MODEL_RAVEN 0
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#define OPENPIC_MODEL_FSL_MPIC_20 1
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2013-01-21 19:53:53 +04:00
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#define OPENPIC_MODEL_FSL_MPIC_42 2
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2012-12-08 02:51:09 +04:00
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2009-03-02 19:42:04 +03:00
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#endif /* __OPENPIC_H__ */
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