2020-04-04 00:05:01 +03:00
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/*
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* RISC-V translation routines for the RVXI Base Integer Instruction Set.
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*
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* Copyright (c) 2020 Western Digital
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2020-11-04 07:43:31 +03:00
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#ifndef CONFIG_USER_ONLY
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2021-08-23 22:55:28 +03:00
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static bool check_access(DisasContext *ctx)
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{
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2020-11-04 07:43:31 +03:00
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if (!ctx->hlsx) {
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if (ctx->virt_enabled) {
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generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
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} else {
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generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
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}
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2021-08-23 22:55:28 +03:00
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return false;
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2020-11-04 07:43:31 +03:00
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}
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2021-08-23 22:55:28 +03:00
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return true;
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2020-11-04 07:43:31 +03:00
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}
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#endif
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2021-08-23 22:55:28 +03:00
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static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop)
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2020-08-12 22:13:19 +03:00
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{
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2021-08-23 22:55:28 +03:00
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#ifdef CONFIG_USER_ONLY
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2020-08-12 22:13:19 +03:00
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return false;
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2021-08-23 22:55:28 +03:00
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#else
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if (check_access(ctx)) {
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
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int mem_idx = ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
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tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop);
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gen_set_gpr(ctx, a->rd, dest);
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}
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return true;
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2020-08-12 22:13:19 +03:00
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#endif
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}
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2021-08-23 22:55:28 +03:00
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static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
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2020-08-12 22:13:19 +03:00
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{
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REQUIRE_EXT(ctx, RVH);
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2021-08-23 22:55:28 +03:00
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return do_hlv(ctx, a, MO_SB);
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}
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2020-08-12 22:13:19 +03:00
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2021-08-23 22:55:28 +03:00
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static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
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{
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REQUIRE_EXT(ctx, RVH);
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return do_hlv(ctx, a, MO_TESW);
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2020-08-12 22:13:19 +03:00
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}
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static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
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{
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REQUIRE_EXT(ctx, RVH);
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2021-08-23 22:55:28 +03:00
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return do_hlv(ctx, a, MO_TESL);
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2020-08-12 22:13:19 +03:00
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}
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static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
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{
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REQUIRE_EXT(ctx, RVH);
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2021-08-23 22:55:28 +03:00
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return do_hlv(ctx, a, MO_UB);
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2020-08-12 22:13:19 +03:00
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}
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static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
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{
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REQUIRE_EXT(ctx, RVH);
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2021-08-23 22:55:28 +03:00
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return do_hlv(ctx, a, MO_TEUW);
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}
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2020-08-12 22:13:19 +03:00
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2021-08-23 22:55:28 +03:00
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static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop)
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{
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#ifdef CONFIG_USER_ONLY
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2020-08-12 22:13:19 +03:00
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return false;
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2021-08-23 22:55:28 +03:00
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#else
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if (check_access(ctx)) {
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TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
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TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
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int mem_idx = ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
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tcg_gen_qemu_st_tl(data, addr, mem_idx, mop);
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}
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return true;
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2020-08-12 22:13:19 +03:00
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#endif
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}
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static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
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{
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REQUIRE_EXT(ctx, RVH);
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2021-08-23 22:55:28 +03:00
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return do_hsv(ctx, a, MO_SB);
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2020-08-12 22:13:19 +03:00
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}
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static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
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{
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REQUIRE_EXT(ctx, RVH);
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2021-08-23 22:55:28 +03:00
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return do_hsv(ctx, a, MO_TESW);
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2020-08-12 22:13:19 +03:00
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}
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static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
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{
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REQUIRE_EXT(ctx, RVH);
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2021-08-23 22:55:28 +03:00
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return do_hsv(ctx, a, MO_TESL);
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2020-08-12 22:13:19 +03:00
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}
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static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
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{
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2021-04-24 06:34:12 +03:00
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REQUIRE_64BIT(ctx);
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2020-08-12 22:13:19 +03:00
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REQUIRE_EXT(ctx, RVH);
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2021-08-23 22:55:28 +03:00
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return do_hlv(ctx, a, MO_TEUL);
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2020-08-12 22:13:19 +03:00
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}
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static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
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{
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2021-04-24 06:34:12 +03:00
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REQUIRE_64BIT(ctx);
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2020-08-12 22:13:19 +03:00
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REQUIRE_EXT(ctx, RVH);
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2021-08-23 22:55:28 +03:00
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return do_hlv(ctx, a, MO_TEQ);
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2020-08-12 22:13:19 +03:00
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}
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static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
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{
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2021-04-24 06:34:12 +03:00
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REQUIRE_64BIT(ctx);
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2020-08-12 22:13:19 +03:00
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REQUIRE_EXT(ctx, RVH);
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2021-08-23 22:55:28 +03:00
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return do_hsv(ctx, a, MO_TEQ);
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}
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2021-04-24 06:34:12 +03:00
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2020-08-12 22:13:19 +03:00
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#ifndef CONFIG_USER_ONLY
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2021-08-23 22:55:28 +03:00
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static bool do_hlvx(DisasContext *ctx, arg_r2 *a,
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void (*func)(TCGv, TCGv_env, TCGv))
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{
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if (check_access(ctx)) {
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
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func(dest, cpu_env, addr);
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gen_set_gpr(ctx, a->rd, dest);
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}
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2020-08-12 22:13:19 +03:00
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return true;
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}
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2021-08-23 22:55:28 +03:00
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#endif
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2020-08-12 22:13:19 +03:00
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static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
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{
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REQUIRE_EXT(ctx, RVH);
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#ifndef CONFIG_USER_ONLY
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2021-08-23 22:55:28 +03:00
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return do_hlvx(ctx, a, gen_helper_hyp_hlvx_hu);
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2020-08-12 22:13:19 +03:00
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#else
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return false;
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#endif
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}
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static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
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{
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REQUIRE_EXT(ctx, RVH);
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#ifndef CONFIG_USER_ONLY
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2021-08-23 22:55:28 +03:00
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return do_hlvx(ctx, a, gen_helper_hyp_hlvx_wu);
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2020-08-12 22:13:19 +03:00
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#else
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return false;
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#endif
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}
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2020-04-04 00:05:01 +03:00
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static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
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{
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2020-04-04 01:54:59 +03:00
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REQUIRE_EXT(ctx, RVH);
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2020-04-04 00:05:01 +03:00
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#ifndef CONFIG_USER_ONLY
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2020-08-12 22:13:49 +03:00
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gen_helper_hyp_gvma_tlb_flush(cpu_env);
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2020-04-04 01:54:59 +03:00
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return true;
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2020-04-04 00:05:01 +03:00
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#endif
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return false;
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}
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static bool trans_hfence_vvma(DisasContext *ctx, arg_sfence_vma *a)
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{
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2020-04-04 01:54:59 +03:00
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REQUIRE_EXT(ctx, RVH);
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2020-04-04 00:05:01 +03:00
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#ifndef CONFIG_USER_ONLY
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2020-04-04 01:54:59 +03:00
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gen_helper_hyp_tlb_flush(cpu_env);
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return true;
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2020-04-04 00:05:01 +03:00
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#endif
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return false;
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}
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