246 lines
9.1 KiB
C
246 lines
9.1 KiB
C
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/*
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* x86_64 cpu init and loop
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TARGET_ARCH_CPU_H_
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#define _TARGET_ARCH_CPU_H_
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#include "target_arch.h"
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#define TARGET_DEFAULT_CPU_MODEL "qemu64"
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static inline void target_cpu_init(CPUX86State *env,
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struct target_pt_regs *regs)
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{
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uint64_t *gdt_table;
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env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
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env->hflags |= HF_PE_MASK | HF_CPL_MASK;
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if (env->features[FEAT_1_EDX] & CPUID_SSE) {
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env->cr[4] |= CR4_OSFXSR_MASK;
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env->hflags |= HF_OSFXSR_MASK;
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}
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/* enable 64 bit mode if possible */
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if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
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fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
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exit(1);
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}
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env->cr[4] |= CR4_PAE_MASK;
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env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
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env->hflags |= HF_LMA_MASK;
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/* flags setup : we activate the IRQs by default as in user mode */
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env->eflags |= IF_MASK;
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/* register setup */
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env->regs[R_EAX] = regs->rax;
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env->regs[R_EBX] = regs->rbx;
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env->regs[R_ECX] = regs->rcx;
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env->regs[R_EDX] = regs->rdx;
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env->regs[R_ESI] = regs->rsi;
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env->regs[R_EDI] = regs->rdi;
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env->regs[R_EBP] = regs->rbp;
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env->regs[R_ESP] = regs->rsp;
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env->eip = regs->rip;
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/* interrupt setup */
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env->idt.limit = 511;
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env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
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PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
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bsd_x86_64_set_idt_base(env->idt.base);
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bsd_x86_64_set_idt(0, 0);
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bsd_x86_64_set_idt(1, 0);
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bsd_x86_64_set_idt(2, 0);
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bsd_x86_64_set_idt(3, 3);
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bsd_x86_64_set_idt(4, 3);
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bsd_x86_64_set_idt(5, 0);
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bsd_x86_64_set_idt(6, 0);
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bsd_x86_64_set_idt(7, 0);
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bsd_x86_64_set_idt(8, 0);
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bsd_x86_64_set_idt(9, 0);
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bsd_x86_64_set_idt(10, 0);
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bsd_x86_64_set_idt(11, 0);
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bsd_x86_64_set_idt(12, 0);
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bsd_x86_64_set_idt(13, 0);
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bsd_x86_64_set_idt(14, 0);
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bsd_x86_64_set_idt(15, 0);
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bsd_x86_64_set_idt(16, 0);
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bsd_x86_64_set_idt(17, 0);
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bsd_x86_64_set_idt(18, 0);
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bsd_x86_64_set_idt(19, 0);
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bsd_x86_64_set_idt(0x80, 3);
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/* segment setup */
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env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
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PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
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env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
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gdt_table = g2h_untagged(env->gdt.base);
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/* 64 bit code segment */
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bsd_x86_64_write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | DESC_L_MASK
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| (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
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bsd_x86_64_write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
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(3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
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cpu_x86_load_seg(env, R_CS, __USER_CS);
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cpu_x86_load_seg(env, R_SS, __USER_DS);
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cpu_x86_load_seg(env, R_DS, 0);
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cpu_x86_load_seg(env, R_ES, 0);
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cpu_x86_load_seg(env, R_FS, 0);
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cpu_x86_load_seg(env, R_GS, 0);
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}
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static inline void target_cpu_loop(CPUX86State *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr;
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abi_ulong pc;
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/* target_siginfo_t info; */
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for (;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch (trapnr) {
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case 0x80:
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/* syscall from int $0x80 */
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if (bsd_type == target_freebsd) {
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abi_ulong params = (abi_ulong) env->regs[R_ESP] +
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sizeof(int32_t);
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int32_t syscall_nr = env->regs[R_EAX];
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int32_t arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8;
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if (syscall_nr == TARGET_FREEBSD_NR_syscall) {
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get_user_s32(syscall_nr, params);
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params += sizeof(int32_t);
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} else if (syscall_nr == TARGET_FREEBSD_NR___syscall) {
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get_user_s32(syscall_nr, params);
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params += sizeof(int64_t);
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}
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get_user_s32(arg1, params);
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params += sizeof(int32_t);
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get_user_s32(arg2, params);
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params += sizeof(int32_t);
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get_user_s32(arg3, params);
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params += sizeof(int32_t);
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get_user_s32(arg4, params);
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params += sizeof(int32_t);
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get_user_s32(arg5, params);
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params += sizeof(int32_t);
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get_user_s32(arg6, params);
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params += sizeof(int32_t);
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get_user_s32(arg7, params);
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params += sizeof(int32_t);
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get_user_s32(arg8, params);
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env->regs[R_EAX] = do_freebsd_syscall(env,
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syscall_nr,
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arg1,
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arg2,
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arg3,
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arg4,
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arg5,
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arg6,
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arg7,
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arg8);
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} else { /* if (bsd_type == target_openbsd) */
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env->regs[R_EAX] = do_openbsd_syscall(env,
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env->regs[R_EAX],
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env->regs[R_EBX],
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env->regs[R_ECX],
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env->regs[R_EDX],
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env->regs[R_ESI],
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env->regs[R_EDI],
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env->regs[R_EBP]);
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}
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if (((abi_ulong)env->regs[R_EAX]) >= (abi_ulong)(-515)) {
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env->regs[R_EAX] = -env->regs[R_EAX];
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env->eflags |= CC_C;
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} else {
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env->eflags &= ~CC_C;
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}
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break;
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case EXCP_SYSCALL:
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/* syscall from syscall instruction */
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if (bsd_type == target_freebsd) {
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env->regs[R_EAX] = do_freebsd_syscall(env,
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env->regs[R_EAX],
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env->regs[R_EDI],
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env->regs[R_ESI],
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env->regs[R_EDX],
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env->regs[R_ECX],
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env->regs[8],
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env->regs[9], 0, 0);
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} else { /* if (bsd_type == target_openbsd) */
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env->regs[R_EAX] = do_openbsd_syscall(env,
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env->regs[R_EAX],
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env->regs[R_EDI],
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env->regs[R_ESI],
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env->regs[R_EDX],
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env->regs[10],
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env->regs[8],
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env->regs[9]);
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}
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env->eip = env->exception_next_eip;
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if (((abi_ulong)env->regs[R_EAX]) >= (abi_ulong)(-515)) {
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env->regs[R_EAX] = -env->regs[R_EAX];
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env->eflags |= CC_C;
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} else {
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env->eflags &= ~CC_C;
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}
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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pc = env->segs[R_CS].base + env->eip;
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fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - "
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"aborting\n", (long)pc, trapnr);
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abort();
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}
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process_pending_signals(env);
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}
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}
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static inline void target_cpu_clone_regs(CPUX86State *env, target_ulong newsp)
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{
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if (newsp) {
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env->regs[R_ESP] = newsp;
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}
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env->regs[R_EAX] = 0;
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}
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static inline void target_cpu_reset(CPUArchState *cpu)
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{
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cpu_reset(env_cpu(cpu));
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}
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#endif /* ! _TARGET_ARCH_CPU_H_ */
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