2013-12-17 23:42:38 +04:00
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/*
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* Allwinner A10 interrupt controller device emulation
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*
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* Copyright (C) 2013 Li Guang
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* Written by Li Guang <lig.fnst@cn.fujitsu.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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2016-01-26 21:17:05 +03:00
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#include "qemu/osdep.h"
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2013-12-17 23:42:38 +04:00
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#include "hw/sysbus.h"
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2019-08-12 08:23:45 +03:00
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#include "migration/vmstate.h"
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2013-12-17 23:42:38 +04:00
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#include "hw/intc/allwinner-a10-pic.h"
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2019-08-12 08:23:42 +03:00
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#include "hw/irq.h"
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2015-12-15 15:16:16 +03:00
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#include "qemu/log.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2013-12-17 23:42:38 +04:00
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static void aw_a10_pic_update(AwA10PICState *s)
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{
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uint8_t i;
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2015-03-23 18:29:27 +03:00
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int irq = 0, fiq = 0, zeroes;
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2014-03-25 22:22:04 +04:00
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s->vector = 0;
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2013-12-17 23:42:38 +04:00
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for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
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irq |= s->irq_pending[i] & ~s->mask[i];
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fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
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2014-03-25 22:22:04 +04:00
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if (!s->vector) {
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2015-03-23 18:29:27 +03:00
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zeroes = ctz32(s->irq_pending[i] & ~s->mask[i]);
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if (zeroes != 32) {
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s->vector = (i * 32 + zeroes) * 4;
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2014-03-25 22:22:04 +04:00
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}
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}
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2013-12-17 23:42:38 +04:00
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}
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qemu_set_irq(s->parent_irq, !!irq);
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qemu_set_irq(s->parent_fiq, !!fiq);
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}
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static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
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{
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AwA10PICState *s = opaque;
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2023-04-24 18:28:33 +03:00
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uint32_t *pending_reg = &s->irq_pending[irq / 32];
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2013-12-17 23:42:38 +04:00
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2023-04-24 18:28:33 +03:00
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*pending_reg = deposit32(*pending_reg, irq % 32, 1, level);
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2013-12-17 23:42:38 +04:00
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aw_a10_pic_update(s);
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}
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static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size)
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{
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AwA10PICState *s = opaque;
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uint8_t index = (offset & 0xc) / 4;
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switch (offset) {
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case AW_A10_PIC_VECTOR:
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return s->vector;
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case AW_A10_PIC_BASE_ADDR:
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return s->base_addr;
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case AW_A10_PIC_PROTECT:
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return s->protect;
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case AW_A10_PIC_NMI:
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return s->nmi;
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case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
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return s->irq_pending[index];
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case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
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return s->fiq_pending[index];
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case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
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return s->select[index];
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case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
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return s->enable[index];
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case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
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return s->mask[index];
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%x\n", __func__, (int)offset);
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break;
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}
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return 0;
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}
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static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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AwA10PICState *s = opaque;
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uint8_t index = (offset & 0xc) / 4;
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switch (offset) {
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case AW_A10_PIC_BASE_ADDR:
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s->base_addr = value & ~0x3;
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2014-05-13 19:09:38 +04:00
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break;
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2013-12-17 23:42:38 +04:00
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case AW_A10_PIC_PROTECT:
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s->protect = value;
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break;
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case AW_A10_PIC_NMI:
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s->nmi = value;
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break;
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case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
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2014-03-25 22:22:05 +04:00
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/*
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* The register is read-only; nevertheless, Linux (including
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* the version originally shipped by Allwinner) pretends to
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* write to the register. Just ignore it.
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*/
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2013-12-17 23:42:38 +04:00
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break;
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case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
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s->fiq_pending[index] &= ~value;
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break;
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case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
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s->select[index] = value;
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break;
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case AW_A10_PIC_ENABLE ... AW_A10_PIC_ENABLE + 8:
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s->enable[index] = value;
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break;
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case AW_A10_PIC_MASK ... AW_A10_PIC_MASK + 8:
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s->mask[index] = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%x\n", __func__, (int)offset);
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break;
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}
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aw_a10_pic_update(s);
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}
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static const MemoryRegionOps aw_a10_pic_ops = {
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.read = aw_a10_pic_read,
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.write = aw_a10_pic_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_aw_a10_pic = {
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.name = "a10.pic",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(vector, AwA10PICState),
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VMSTATE_UINT32(base_addr, AwA10PICState),
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VMSTATE_UINT32(protect, AwA10PICState),
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VMSTATE_UINT32(nmi, AwA10PICState),
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VMSTATE_UINT32_ARRAY(irq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
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VMSTATE_UINT32_ARRAY(fiq_pending, AwA10PICState, AW_A10_PIC_REG_NUM),
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VMSTATE_UINT32_ARRAY(enable, AwA10PICState, AW_A10_PIC_REG_NUM),
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VMSTATE_UINT32_ARRAY(select, AwA10PICState, AW_A10_PIC_REG_NUM),
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VMSTATE_UINT32_ARRAY(mask, AwA10PICState, AW_A10_PIC_REG_NUM),
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VMSTATE_END_OF_LIST()
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}
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};
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static void aw_a10_pic_init(Object *obj)
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{
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AwA10PICState *s = AW_A10_PIC(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR);
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sysbus_init_irq(dev, &s->parent_irq);
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sysbus_init_irq(dev, &s->parent_fiq);
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memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s,
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TYPE_AW_A10_PIC, 0x400);
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sysbus_init_mmio(dev, &s->iomem);
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}
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static void aw_a10_pic_reset(DeviceState *d)
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{
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AwA10PICState *s = AW_A10_PIC(d);
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uint8_t i;
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s->base_addr = 0;
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s->protect = 0;
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s->nmi = 0;
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s->vector = 0;
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for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
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s->irq_pending[i] = 0;
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s->fiq_pending[i] = 0;
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s->select[i] = 0;
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s->enable[i] = 0;
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s->mask[i] = 0;
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}
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}
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static void aw_a10_pic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = aw_a10_pic_reset;
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dc->desc = "allwinner a10 pic";
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dc->vmsd = &vmstate_aw_a10_pic;
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}
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static const TypeInfo aw_a10_pic_info = {
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.name = TYPE_AW_A10_PIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AwA10PICState),
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.instance_init = aw_a10_pic_init,
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.class_init = aw_a10_pic_class_init,
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};
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static void aw_a10_register_types(void)
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{
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type_register_static(&aw_a10_pic_info);
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}
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type_init(aw_a10_register_types);
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