2003-06-16 00:02:25 +04:00
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/*
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* defines common to all virtual CPUs
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2007-09-17 01:08:06 +04:00
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*
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2003-06-16 00:02:25 +04:00
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-17 00:47:01 +04:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2003-06-16 00:02:25 +04:00
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*/
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#ifndef CPU_ALL_H
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#define CPU_ALL_H
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2012-12-17 21:19:49 +04:00
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#include "exec/cpu-common.h"
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2013-10-08 18:14:39 +04:00
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#include "exec/memory.h"
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2011-08-17 11:01:33 +04:00
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#include "qemu/thread.h"
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2019-07-09 18:20:52 +03:00
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#include "hw/core/cpu.h"
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2013-09-09 19:58:40 +04:00
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#include "qemu/rcu.h"
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2004-01-04 18:44:17 +03:00
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2015-05-31 09:11:42 +03:00
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#define EXCP_INTERRUPT 0x10000 /* async interruption */
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#define EXCP_HLT 0x10001 /* hlt instruction reached */
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#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
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#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
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#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
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2016-06-30 08:12:55 +03:00
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#define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
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2015-05-31 09:11:42 +03:00
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2007-09-17 01:08:06 +04:00
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/* some important defines:
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*
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2009-07-27 18:13:06 +04:00
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* HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
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2004-01-04 18:44:17 +03:00
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* otherwise little endian.
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2007-09-17 01:08:06 +04:00
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*
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2004-01-04 18:44:17 +03:00
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* TARGET_WORDS_BIGENDIAN : same for target cpu
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*/
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2009-07-27 18:13:06 +04:00
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#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
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2004-03-21 20:06:25 +03:00
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#define BSWAP_NEEDED
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#endif
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#ifdef BSWAP_NEEDED
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static inline uint16_t tswap16(uint16_t s)
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{
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return bswap16(s);
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}
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static inline uint32_t tswap32(uint32_t s)
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{
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return bswap32(s);
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}
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static inline uint64_t tswap64(uint64_t s)
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{
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return bswap64(s);
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}
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static inline void tswap16s(uint16_t *s)
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{
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*s = bswap16(*s);
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}
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static inline void tswap32s(uint32_t *s)
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{
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*s = bswap32(*s);
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}
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static inline void tswap64s(uint64_t *s)
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{
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*s = bswap64(*s);
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}
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#else
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static inline uint16_t tswap16(uint16_t s)
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{
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return s;
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}
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static inline uint32_t tswap32(uint32_t s)
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{
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return s;
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}
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static inline uint64_t tswap64(uint64_t s)
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{
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return s;
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}
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static inline void tswap16s(uint16_t *s)
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{
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}
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static inline void tswap32s(uint32_t *s)
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{
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}
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static inline void tswap64s(uint64_t *s)
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{
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}
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#endif
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#if TARGET_LONG_SIZE == 4
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#define tswapl(s) tswap32(s)
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#define tswapls(s) tswap32s((uint32_t *)(s))
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2005-02-11 01:00:27 +03:00
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#define bswaptls(s) bswap32s(s)
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2004-03-21 20:06:25 +03:00
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#else
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#define tswapl(s) tswap64(s)
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#define tswapls(s) tswap64s((uint64_t *)(s))
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2005-02-11 01:00:27 +03:00
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#define bswaptls(s) bswap64s(s)
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2004-03-21 20:06:25 +03:00
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#endif
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2015-01-20 18:19:35 +03:00
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/* Target-endianness CPU memory access functions. These fit into the
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* {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
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2004-02-22 14:53:50 +03:00
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*/
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2005-11-19 20:47:39 +03:00
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#if defined(TARGET_WORDS_BIGENDIAN)
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#define lduw_p(p) lduw_be_p(p)
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#define ldsw_p(p) ldsw_be_p(p)
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#define ldl_p(p) ldl_be_p(p)
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#define ldq_p(p) ldq_be_p(p)
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#define ldfl_p(p) ldfl_be_p(p)
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#define ldfq_p(p) ldfq_be_p(p)
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#define stw_p(p, v) stw_be_p(p, v)
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#define stl_p(p, v) stl_be_p(p, v)
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#define stq_p(p, v) stq_be_p(p, v)
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#define stfl_p(p, v) stfl_be_p(p, v)
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#define stfq_p(p, v) stfq_be_p(p, v)
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2018-06-15 16:57:14 +03:00
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#define ldn_p(p, sz) ldn_be_p(p, sz)
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#define stn_p(p, sz, v) stn_be_p(p, sz, v)
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2005-11-19 20:47:39 +03:00
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#else
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#define lduw_p(p) lduw_le_p(p)
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#define ldsw_p(p) ldsw_le_p(p)
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#define ldl_p(p) ldl_le_p(p)
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#define ldq_p(p) ldq_le_p(p)
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#define ldfl_p(p) ldfl_le_p(p)
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#define ldfq_p(p) ldfq_le_p(p)
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#define stw_p(p, v) stw_le_p(p, v)
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#define stl_p(p, v) stl_le_p(p, v)
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#define stq_p(p, v) stq_le_p(p, v)
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#define stfl_p(p, v) stfl_le_p(p, v)
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#define stfq_p(p, v) stfq_le_p(p, v)
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2018-06-15 16:57:14 +03:00
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#define ldn_p(p, sz) ldn_le_p(p, sz)
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#define stn_p(p, sz, v) stn_le_p(p, sz, v)
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2003-06-16 00:02:25 +04:00
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#endif
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2003-10-28 00:22:23 +03:00
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/* MMU memory access macros */
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2006-03-25 22:31:22 +03:00
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#if defined(CONFIG_USER_ONLY)
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2012-12-17 21:19:49 +04:00
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#include "exec/user/abitypes.h"
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2008-12-08 21:12:11 +03:00
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2006-03-25 22:31:22 +03:00
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/* On some host systems the guest address space is reserved on the host.
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* This allows the guest address space to be offset to a convenient location.
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*/
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2009-07-17 15:48:08 +04:00
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extern unsigned long guest_base;
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extern int have_guest_base;
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2010-05-29 05:27:35 +04:00
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extern unsigned long reserved_va;
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2006-03-25 22:31:22 +03:00
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2018-03-08 00:50:10 +03:00
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#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
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#define GUEST_ADDR_MAX (~0ul)
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#else
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#define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : \
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2014-08-05 17:33:51 +04:00
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(1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1)
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2018-03-08 00:50:10 +03:00
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#endif
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2014-06-27 10:33:38 +04:00
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#else
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#include "exec/hwaddr.h"
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2018-03-05 01:31:47 +03:00
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#define SUFFIX
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#define ARG1 as
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#define ARG1_DECL AddressSpace *as
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst.inc.h"
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2018-03-18 20:26:36 +03:00
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#define SUFFIX _cached_slow
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2018-03-05 01:31:47 +03:00
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#define ARG1 cache
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#define ARG1_DECL MemoryRegionCache *cache
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst.inc.h"
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static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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address_space_stl_notdirty(as, addr, val,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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#define SUFFIX
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#define ARG1 as
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#define ARG1_DECL AddressSpace *as
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst_phys.inc.h"
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2018-03-18 20:26:36 +03:00
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/* Inline fast path for direct RAM access. */
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#define ENDIANNESS
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#include "exec/memory_ldst_cached.inc.h"
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2018-03-05 01:31:47 +03:00
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#define SUFFIX _cached
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#define ARG1 cache
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#define ARG1_DECL MemoryRegionCache *cache
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst_phys.inc.h"
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2006-03-25 22:31:22 +03:00
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#endif
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2003-06-16 00:02:25 +04:00
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/* page related stuff */
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2016-10-24 18:26:49 +03:00
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#ifdef TARGET_PAGE_BITS_VARY
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2019-09-13 18:21:53 +03:00
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typedef struct {
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bool decided;
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int bits;
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2019-09-13 19:07:40 +03:00
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target_long mask;
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2019-09-13 18:21:53 +03:00
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} TargetPageBits;
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#if defined(CONFIG_ATTRIBUTE_ALIAS) || !defined(IN_EXEC_VARY)
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extern const TargetPageBits target_page;
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#else
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extern TargetPageBits target_page;
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#endif
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2019-09-13 18:41:51 +03:00
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#ifdef CONFIG_DEBUG_TCG
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2019-09-13 18:21:53 +03:00
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#define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; })
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2019-09-13 19:07:40 +03:00
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#define TARGET_PAGE_MASK ({ assert(target_page.decided); target_page.mask; })
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2016-10-24 18:26:49 +03:00
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#else
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2019-09-13 18:41:51 +03:00
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#define TARGET_PAGE_BITS target_page.bits
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2019-09-13 19:07:40 +03:00
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#define TARGET_PAGE_MASK target_page.mask
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2019-09-13 18:41:51 +03:00
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#endif
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2019-09-13 19:07:40 +03:00
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#define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
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2019-09-13 18:41:51 +03:00
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#else
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2016-10-24 18:26:49 +03:00
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#define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
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2019-09-13 19:07:40 +03:00
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#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
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#define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
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2016-10-24 18:26:49 +03:00
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#endif
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2019-10-13 05:11:44 +03:00
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#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
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2003-06-16 00:02:25 +04:00
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2015-12-02 15:00:54 +03:00
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/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
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* when intptr_t is 32-bit and we are aligning a long long.
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*/
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2012-03-16 23:23:49 +04:00
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extern uintptr_t qemu_host_page_size;
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2015-12-02 15:00:54 +03:00
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extern intptr_t qemu_host_page_mask;
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2003-06-16 00:02:25 +04:00
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2019-10-13 05:11:44 +03:00
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#define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
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#define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size)
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2003-06-16 00:02:25 +04:00
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/* same as PROT_xxx */
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#define PAGE_READ 0x0001
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#define PAGE_WRITE 0x0002
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#define PAGE_EXEC 0x0004
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#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
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#define PAGE_VALID 0x0008
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/* original state of the write flag (used when tracking self-modifying
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code */
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2007-09-17 01:08:06 +04:00
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#define PAGE_WRITE_ORG 0x0010
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2017-10-16 23:23:57 +03:00
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/* Invalidate the TLB entry immediately, helpful for s390x
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* Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */
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#define PAGE_WRITE_INV 0x0040
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2010-05-05 19:32:59 +04:00
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#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
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/* FIXME: Code that sets/uses this is broken and needs to go away. */
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2007-12-12 04:16:23 +03:00
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#define PAGE_RESERVED 0x0020
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2010-05-05 19:32:59 +04:00
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#endif
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2003-06-16 00:02:25 +04:00
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2010-03-13 02:23:29 +03:00
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#if defined(CONFIG_USER_ONLY)
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2003-06-16 00:02:25 +04:00
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void page_dump(FILE *f);
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2010-03-11 02:53:37 +03:00
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2014-09-08 17:28:56 +04:00
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typedef int (*walk_memory_regions_fn)(void *, target_ulong,
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target_ulong, unsigned long);
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2010-03-11 02:53:37 +03:00
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int walk_memory_regions(void *, walk_memory_regions_fn);
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2006-03-25 22:31:22 +03:00
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int page_get_flags(target_ulong address);
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void page_set_flags(target_ulong start, target_ulong end, int flags);
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2007-11-02 22:02:07 +03:00
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int page_check_range(target_ulong start, target_ulong len, int flags);
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2010-03-13 02:23:29 +03:00
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#endif
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2003-06-16 00:02:25 +04:00
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2012-03-14 04:38:32 +04:00
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CPUArchState *cpu_copy(CPUArchState *env);
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2007-02-28 23:20:53 +03:00
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2011-05-05 00:34:24 +04:00
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/* Flags for use in ENV->INTERRUPT_PENDING.
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The numbers assigned here are non-sequential in order to preserve
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binary compatibility with the vmstate dump. Bit 0 (0x0001) was
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previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
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the vmstate dump. */
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/* External hardware interrupt pending. This is typically used for
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interrupts from devices. */
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#define CPU_INTERRUPT_HARD 0x0002
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/* Exit the current TB. This is typically used when some system-level device
|
|
|
|
makes some change to the memory mapping. E.g. the a20 line change. */
|
|
|
|
#define CPU_INTERRUPT_EXITTB 0x0004
|
|
|
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|
|
|
|
/* Halt the CPU. */
|
|
|
|
#define CPU_INTERRUPT_HALT 0x0020
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|
|
|
|
|
/* Debug event pending. */
|
|
|
|
#define CPU_INTERRUPT_DEBUG 0x0080
|
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|
|
2013-03-05 18:35:17 +04:00
|
|
|
/* Reset signal. */
|
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|
|
#define CPU_INTERRUPT_RESET 0x0400
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|
|
|
2011-05-05 00:34:24 +04:00
|
|
|
/* Several target-specific external hardware interrupts. Each target/cpu.h
|
|
|
|
should define proper names based on these defines. */
|
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|
|
#define CPU_INTERRUPT_TGT_EXT_0 0x0008
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|
|
#define CPU_INTERRUPT_TGT_EXT_1 0x0010
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|
#define CPU_INTERRUPT_TGT_EXT_2 0x0040
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|
#define CPU_INTERRUPT_TGT_EXT_3 0x0200
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|
#define CPU_INTERRUPT_TGT_EXT_4 0x1000
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|
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|
|
/* Several target-specific internal interrupts. These differ from the
|
2011-11-22 14:06:26 +04:00
|
|
|
preceding target-specific interrupts in that they are intended to
|
2011-05-05 00:34:24 +04:00
|
|
|
originate from within the cpu itself, typically in response to some
|
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|
|
instruction being executed. These, therefore, are not masked while
|
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|
|
single-stepping within the debugger. */
|
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|
|
#define CPU_INTERRUPT_TGT_INT_0 0x0100
|
2013-03-05 18:35:17 +04:00
|
|
|
#define CPU_INTERRUPT_TGT_INT_1 0x0800
|
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|
|
#define CPU_INTERRUPT_TGT_INT_2 0x2000
|
2011-05-05 00:34:24 +04:00
|
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|
|
2012-02-17 21:31:17 +04:00
|
|
|
/* First unused bit: 0x4000. */
|
2011-05-05 00:34:24 +04:00
|
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|
2011-05-05 00:34:25 +04:00
|
|
|
/* The set of all bits that should be masked when single-stepping. */
|
|
|
|
#define CPU_INTERRUPT_SSTEP_MASK \
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|
|
(CPU_INTERRUPT_HARD \
|
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|
|
| CPU_INTERRUPT_TGT_EXT_0 \
|
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|
|
| CPU_INTERRUPT_TGT_EXT_1 \
|
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|
|
| CPU_INTERRUPT_TGT_EXT_2 \
|
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|
|
| CPU_INTERRUPT_TGT_EXT_3 \
|
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|
|
| CPU_INTERRUPT_TGT_EXT_4)
|
2005-11-26 13:29:22 +03:00
|
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|
|
2010-03-12 19:54:58 +03:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
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|
|
|
2019-09-13 18:29:35 +03:00
|
|
|
/*
|
|
|
|
* Flags stored in the low bits of the TLB virtual address.
|
|
|
|
* These are defined so that fast path ram access is all zeros.
|
2016-06-23 21:16:46 +03:00
|
|
|
* The flags all must be between TARGET_PAGE_BITS and
|
|
|
|
* maximum address alignment bit.
|
2019-09-13 18:29:35 +03:00
|
|
|
*
|
|
|
|
* Use TARGET_PAGE_BITS_MIN so that these bits are constant
|
|
|
|
* when TARGET_PAGE_BITS_VARY is in effect.
|
2016-06-23 21:16:46 +03:00
|
|
|
*/
|
2008-06-09 04:20:13 +04:00
|
|
|
/* Zero if TLB entry is valid. */
|
2019-09-13 18:29:35 +03:00
|
|
|
#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
|
2008-06-09 04:20:13 +04:00
|
|
|
/* Set if TLB entry references a clean RAM page. The iotlb entry will
|
|
|
|
contain the page physical address. */
|
2019-09-13 18:29:35 +03:00
|
|
|
#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
|
2008-06-09 04:20:13 +04:00
|
|
|
/* Set if TLB entry is an IO callback. */
|
2019-09-13 18:29:35 +03:00
|
|
|
#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
|
2019-08-24 19:51:09 +03:00
|
|
|
/* Set if TLB entry contains a watchpoint. */
|
2019-09-13 18:29:35 +03:00
|
|
|
#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4))
|
2019-09-10 22:47:39 +03:00
|
|
|
/* Set if TLB entry requires byte swap. */
|
|
|
|
#define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5))
|
2019-09-20 03:54:10 +03:00
|
|
|
/* Set if TLB entry writes ignored. */
|
|
|
|
#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6))
|
2016-06-23 21:16:46 +03:00
|
|
|
|
|
|
|
/* Use this mask to check interception with an alignment mask
|
|
|
|
* in a TCG backend.
|
|
|
|
*/
|
2019-08-24 19:51:09 +03:00
|
|
|
#define TLB_FLAGS_MASK \
|
2019-09-20 03:54:10 +03:00
|
|
|
(TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
|
|
|
|
| TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE)
|
2008-06-09 04:20:13 +04:00
|
|
|
|
2018-06-29 19:21:21 +03:00
|
|
|
/**
|
|
|
|
* tlb_hit_page: return true if page aligned @addr is a hit against the
|
|
|
|
* TLB entry @tlb_addr
|
|
|
|
*
|
|
|
|
* @addr: virtual address to test (must be page aligned)
|
|
|
|
* @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
|
|
|
|
*/
|
|
|
|
static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr)
|
|
|
|
{
|
|
|
|
return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
|
|
|
|
*
|
|
|
|
* @addr: virtual address to test (need not be page aligned)
|
|
|
|
* @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
|
|
|
|
*/
|
|
|
|
static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr)
|
|
|
|
{
|
|
|
|
return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
|
|
|
|
}
|
|
|
|
|
2019-04-17 22:17:52 +03:00
|
|
|
void dump_exec_info(void);
|
2019-04-17 22:17:51 +03:00
|
|
|
void dump_opcount_info(void);
|
2010-03-12 19:54:58 +03:00
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
|
2013-06-29 21:40:58 +04:00
|
|
|
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
|
2019-01-17 15:49:01 +03:00
|
|
|
uint8_t *buf, target_ulong len, int is_write);
|
2010-03-12 19:54:58 +03:00
|
|
|
|
2015-07-18 12:40:28 +03:00
|
|
|
int cpu_exec(CPUState *cpu);
|
|
|
|
|
2019-03-29 00:26:22 +03:00
|
|
|
/**
|
|
|
|
* cpu_set_cpustate_pointers(cpu)
|
|
|
|
* @cpu: The cpu object
|
|
|
|
*
|
|
|
|
* Set the generic pointers in CPUState into the outer object.
|
|
|
|
*/
|
|
|
|
static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
|
|
|
|
{
|
|
|
|
cpu->parent_obj.env_ptr = &cpu->env;
|
2019-03-29 00:54:23 +03:00
|
|
|
cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr;
|
2019-03-29 00:26:22 +03:00
|
|
|
}
|
|
|
|
|
2019-03-23 03:22:52 +03:00
|
|
|
/**
|
|
|
|
* env_archcpu(env)
|
|
|
|
* @env: The architecture environment
|
|
|
|
*
|
|
|
|
* Return the ArchCPU associated with the environment.
|
|
|
|
*/
|
|
|
|
static inline ArchCPU *env_archcpu(CPUArchState *env)
|
|
|
|
{
|
|
|
|
return container_of(env, ArchCPU, env);
|
|
|
|
}
|
|
|
|
|
2019-03-23 02:07:18 +03:00
|
|
|
/**
|
|
|
|
* env_cpu(env)
|
|
|
|
* @env: The architecture environment
|
|
|
|
*
|
|
|
|
* Return the CPUState associated with the environment.
|
|
|
|
*/
|
|
|
|
static inline CPUState *env_cpu(CPUArchState *env)
|
|
|
|
{
|
2019-03-23 03:22:52 +03:00
|
|
|
return &env_archcpu(env)->parent_obj;
|
2019-03-23 02:07:18 +03:00
|
|
|
}
|
|
|
|
|
2019-03-23 03:16:06 +03:00
|
|
|
/**
|
|
|
|
* env_neg(env)
|
|
|
|
* @env: The architecture environment
|
|
|
|
*
|
|
|
|
* Return the CPUNegativeOffsetState associated with the environment.
|
|
|
|
*/
|
|
|
|
static inline CPUNegativeOffsetState *env_neg(CPUArchState *env)
|
|
|
|
{
|
|
|
|
ArchCPU *arch_cpu = container_of(env, ArchCPU, env);
|
|
|
|
return &arch_cpu->neg;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cpu_neg(cpu)
|
|
|
|
* @cpu: The generic CPUState
|
|
|
|
*
|
|
|
|
* Return the CPUNegativeOffsetState associated with the cpu.
|
|
|
|
*/
|
|
|
|
static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu)
|
|
|
|
{
|
|
|
|
ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj);
|
|
|
|
return &arch_cpu->neg;
|
|
|
|
}
|
|
|
|
|
2019-03-23 08:03:39 +03:00
|
|
|
/**
|
|
|
|
* env_tlb(env)
|
|
|
|
* @env: The architecture environment
|
|
|
|
*
|
|
|
|
* Return the CPUTLB state associated with the environment.
|
|
|
|
*/
|
|
|
|
static inline CPUTLB *env_tlb(CPUArchState *env)
|
|
|
|
{
|
|
|
|
return &env_neg(env)->tlb;
|
|
|
|
}
|
|
|
|
|
2003-06-16 00:02:25 +04:00
|
|
|
#endif /* CPU_ALL_H */
|