335 lines
9.8 KiB
C
335 lines
9.8 KiB
C
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/*
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* i.MX I2C Bus Serial Interface Emulation
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*
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* Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "hw/i2c/imx_i2c.h"
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#include "hw/i2c/i2c.h"
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#ifndef IMX_I2C_DEBUG
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#define IMX_I2C_DEBUG 0
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#endif
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#if IMX_I2C_DEBUG
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#define DPRINT(fmt, args...) \
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do { fprintf(stderr, "%s: "fmt, __func__, ## args); } while (0)
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static const char *imx_i2c_get_regname(unsigned offset)
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{
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switch (offset) {
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case IADR_ADDR:
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return "IADR";
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case IFDR_ADDR:
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return "IFDR";
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case I2CR_ADDR:
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return "I2CR";
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case I2SR_ADDR:
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return "I2SR";
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case I2DR_ADDR:
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return "I2DR";
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default:
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return "[?]";
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}
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}
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#else
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#define DPRINT(fmt, args...) do { } while (0)
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#endif
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static inline bool imx_i2c_is_enabled(IMXI2CState *s)
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{
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return s->i2cr & I2CR_IEN;
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}
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static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState *s)
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{
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return s->i2cr & I2CR_IIEN;
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}
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static inline bool imx_i2c_is_master(IMXI2CState *s)
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{
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return s->i2cr & I2CR_MSTA;
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}
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static void imx_i2c_reset(DeviceState *dev)
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{
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IMXI2CState *s = IMX_I2C(dev);
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if (s->address != ADDR_RESET) {
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i2c_end_transfer(s->bus);
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}
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s->address = ADDR_RESET;
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s->iadr = IADR_RESET;
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s->ifdr = IFDR_RESET;
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s->i2cr = I2CR_RESET;
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s->i2sr = I2SR_RESET;
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s->i2dr_read = I2DR_RESET;
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s->i2dr_write = I2DR_RESET;
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}
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static inline void imx_i2c_raise_interrupt(IMXI2CState *s)
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{
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/*
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* raise an interrupt if the device is enabled and it is configured
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* to generate some interrupts.
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*/
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if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) {
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s->i2sr |= I2SR_IIF;
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qemu_irq_raise(s->irq);
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}
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}
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static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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uint16_t value;
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IMXI2CState *s = IMX_I2C(opaque);
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switch (offset) {
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case IADR_ADDR:
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value = s->iadr;
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break;
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case IFDR_ADDR:
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value = s->ifdr;
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break;
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case I2CR_ADDR:
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value = s->i2cr;
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break;
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case I2SR_ADDR:
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value = s->i2sr;
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break;
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case I2DR_ADDR:
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value = s->i2dr_read;
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if (imx_i2c_is_master(s)) {
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int ret = 0xff;
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if (s->address == ADDR_RESET) {
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/* something is wrong as the address is not set */
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qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Trying to read "
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"without specifying the slave address\n",
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TYPE_IMX_I2C, __func__);
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} else if (s->i2cr & I2CR_MTX) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Trying to read "
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"but MTX is set\n", TYPE_IMX_I2C, __func__);
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} else {
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/* get the next byte */
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ret = i2c_recv(s->bus);
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if (ret >= 0) {
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imx_i2c_raise_interrupt(s);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: read failed "
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"for device 0x%02x\n", TYPE_IMX_I2C,
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__func__, s->address);
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ret = 0xff;
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}
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}
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s->i2dr_read = ret;
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} else {
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qemu_log_mask(LOG_UNIMP, "%s[%s]: slave mode not implemented\n",
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TYPE_IMX_I2C, __func__);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad address at offset %d\n",
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TYPE_IMX_I2C, __func__, s->address);
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value = 0;
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break;
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}
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DPRINT("read %s [0x%02x] -> 0x%02x\n", imx_i2c_get_regname(offset),
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(unsigned int)offset, value);
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return (uint64_t)value;
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}
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static void imx_i2c_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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IMXI2CState *s = IMX_I2C(opaque);
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DPRINT("write %s [0x%02x] <- 0x%02x\n", imx_i2c_get_regname(offset),
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(unsigned int)offset, (int)value);
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value &= 0xff;
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switch (offset) {
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case IADR_ADDR:
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s->iadr = value & IADR_MASK;
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/* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */
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break;
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case IFDR_ADDR:
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s->ifdr = value & IFDR_MASK;
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break;
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case I2CR_ADDR:
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if (imx_i2c_is_enabled(s) && ((value & I2CR_IEN) == 0)) {
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/* This is a soft reset. IADR is preserved during soft resets */
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uint16_t iadr = s->iadr;
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imx_i2c_reset(DEVICE(s));
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s->iadr = iadr;
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} else { /* normal write */
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s->i2cr = value & I2CR_MASK;
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if (imx_i2c_is_master(s)) {
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/* set the bus to busy */
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s->i2sr |= I2SR_IBB;
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} else { /* slave mode */
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/* bus is not busy anymore */
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s->i2sr &= ~I2SR_IBB;
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/*
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* if we unset the master mode then it ends the ongoing
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* transfer if any
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*/
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if (s->address != ADDR_RESET) {
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i2c_end_transfer(s->bus);
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s->address = ADDR_RESET;
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}
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}
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if (s->i2cr & I2CR_RSTA) { /* Restart */
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/* if this is a restart then it ends the ongoing transfer */
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if (s->address != ADDR_RESET) {
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i2c_end_transfer(s->bus);
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s->address = ADDR_RESET;
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s->i2cr &= ~I2CR_RSTA;
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}
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}
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}
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break;
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case I2SR_ADDR:
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/*
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* if the user writes 0 to IIF then lower the interrupt and
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* reset the bit
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*/
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if ((s->i2sr & I2SR_IIF) && !(value & I2SR_IIF)) {
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s->i2sr &= ~I2SR_IIF;
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qemu_irq_lower(s->irq);
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}
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/*
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* if the user writes 0 to IAL, reset the bit
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*/
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if ((s->i2sr & I2SR_IAL) && !(value & I2SR_IAL)) {
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s->i2sr &= ~I2SR_IAL;
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}
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break;
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case I2DR_ADDR:
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/* if the device is not enabled, nothing to do */
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if (!imx_i2c_is_enabled(s)) {
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break;
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}
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s->i2dr_write = value & I2DR_MASK;
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if (imx_i2c_is_master(s)) {
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/* If this is the first write cycle then it is the slave addr */
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if (s->address == ADDR_RESET) {
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if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7),
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extract32(s->i2dr_write, 0, 1))) {
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/* if non zero is returned, the adress is not valid */
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s->i2sr |= I2SR_RXAK;
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} else {
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s->address = s->i2dr_write;
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s->i2sr &= ~I2SR_RXAK;
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imx_i2c_raise_interrupt(s);
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}
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} else { /* This is a normal data write */
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if (i2c_send(s->bus, s->i2dr_write)) {
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/* if the target return non zero then end the transfer */
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s->i2sr |= I2SR_RXAK;
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s->address = ADDR_RESET;
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i2c_end_transfer(s->bus);
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} else {
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s->i2sr &= ~I2SR_RXAK;
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imx_i2c_raise_interrupt(s);
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}
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}
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} else {
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qemu_log_mask(LOG_UNIMP, "%s[%s]: slave mode not implemented\n",
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TYPE_IMX_I2C, __func__);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad address at offset %d\n",
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TYPE_IMX_I2C, __func__, s->address);
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break;
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}
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}
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static const MemoryRegionOps imx_i2c_ops = {
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.read = imx_i2c_read,
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.write = imx_i2c_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 2,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription imx_i2c_vmstate = {
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.name = TYPE_IMX_I2C,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT16(address, IMXI2CState),
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VMSTATE_UINT16(iadr, IMXI2CState),
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VMSTATE_UINT16(ifdr, IMXI2CState),
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VMSTATE_UINT16(i2cr, IMXI2CState),
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VMSTATE_UINT16(i2sr, IMXI2CState),
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VMSTATE_UINT16(i2dr_read, IMXI2CState),
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VMSTATE_UINT16(i2dr_write, IMXI2CState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void imx_i2c_realize(DeviceState *dev, Error **errp)
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{
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IMXI2CState *s = IMX_I2C(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C,
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IMX_I2C_MEM_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
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s->bus = i2c_init_bus(DEVICE(dev), "i2c");
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}
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static void imx_i2c_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &imx_i2c_vmstate;
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dc->reset = imx_i2c_reset;
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dc->realize = imx_i2c_realize;
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}
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static const TypeInfo imx_i2c_type_info = {
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.name = TYPE_IMX_I2C,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXI2CState),
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.class_init = imx_i2c_class_init,
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};
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static void imx_i2c_register_types(void)
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{
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type_register_static(&imx_i2c_type_info);
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}
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type_init(imx_i2c_register_types)
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