2018-04-11 21:56:33 +03:00
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/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "cpu_loop-common.h"
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2018-04-11 21:56:51 +03:00
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static void xtensa_rfw(CPUXtensaState *env)
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{
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xtensa_restore_owb(env);
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env->pc = env->sregs[EPC1];
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}
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static void xtensa_rfwu(CPUXtensaState *env)
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{
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env->sregs[WINDOW_START] |= (1 << env->sregs[WINDOW_BASE]);
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xtensa_rfw(env);
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}
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static void xtensa_rfwo(CPUXtensaState *env)
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{
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env->sregs[WINDOW_START] &= ~(1 << env->sregs[WINDOW_BASE]);
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xtensa_rfw(env);
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}
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static void xtensa_overflow4(CPUXtensaState *env)
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{
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put_user_ual(env->regs[0], env->regs[5] - 16);
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put_user_ual(env->regs[1], env->regs[5] - 12);
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put_user_ual(env->regs[2], env->regs[5] - 8);
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put_user_ual(env->regs[3], env->regs[5] - 4);
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xtensa_rfwo(env);
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}
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static void xtensa_underflow4(CPUXtensaState *env)
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{
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get_user_ual(env->regs[0], env->regs[5] - 16);
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get_user_ual(env->regs[1], env->regs[5] - 12);
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get_user_ual(env->regs[2], env->regs[5] - 8);
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get_user_ual(env->regs[3], env->regs[5] - 4);
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xtensa_rfwu(env);
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}
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static void xtensa_overflow8(CPUXtensaState *env)
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{
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put_user_ual(env->regs[0], env->regs[9] - 16);
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get_user_ual(env->regs[0], env->regs[1] - 12);
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put_user_ual(env->regs[1], env->regs[9] - 12);
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put_user_ual(env->regs[2], env->regs[9] - 8);
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put_user_ual(env->regs[3], env->regs[9] - 4);
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put_user_ual(env->regs[4], env->regs[0] - 32);
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put_user_ual(env->regs[5], env->regs[0] - 28);
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put_user_ual(env->regs[6], env->regs[0] - 24);
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put_user_ual(env->regs[7], env->regs[0] - 20);
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xtensa_rfwo(env);
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}
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static void xtensa_underflow8(CPUXtensaState *env)
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{
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get_user_ual(env->regs[0], env->regs[9] - 16);
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get_user_ual(env->regs[1], env->regs[9] - 12);
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get_user_ual(env->regs[2], env->regs[9] - 8);
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get_user_ual(env->regs[7], env->regs[1] - 12);
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get_user_ual(env->regs[3], env->regs[9] - 4);
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get_user_ual(env->regs[4], env->regs[7] - 32);
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get_user_ual(env->regs[5], env->regs[7] - 28);
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get_user_ual(env->regs[6], env->regs[7] - 24);
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get_user_ual(env->regs[7], env->regs[7] - 20);
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xtensa_rfwu(env);
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}
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static void xtensa_overflow12(CPUXtensaState *env)
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{
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put_user_ual(env->regs[0], env->regs[13] - 16);
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get_user_ual(env->regs[0], env->regs[1] - 12);
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put_user_ual(env->regs[1], env->regs[13] - 12);
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put_user_ual(env->regs[2], env->regs[13] - 8);
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put_user_ual(env->regs[3], env->regs[13] - 4);
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put_user_ual(env->regs[4], env->regs[0] - 48);
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put_user_ual(env->regs[5], env->regs[0] - 44);
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put_user_ual(env->regs[6], env->regs[0] - 40);
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put_user_ual(env->regs[7], env->regs[0] - 36);
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put_user_ual(env->regs[8], env->regs[0] - 32);
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put_user_ual(env->regs[9], env->regs[0] - 28);
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put_user_ual(env->regs[10], env->regs[0] - 24);
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put_user_ual(env->regs[11], env->regs[0] - 20);
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xtensa_rfwo(env);
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}
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static void xtensa_underflow12(CPUXtensaState *env)
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{
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get_user_ual(env->regs[0], env->regs[13] - 16);
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get_user_ual(env->regs[1], env->regs[13] - 12);
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get_user_ual(env->regs[2], env->regs[13] - 8);
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get_user_ual(env->regs[11], env->regs[1] - 12);
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get_user_ual(env->regs[3], env->regs[13] - 4);
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get_user_ual(env->regs[4], env->regs[11] - 48);
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get_user_ual(env->regs[5], env->regs[11] - 44);
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get_user_ual(env->regs[6], env->regs[11] - 40);
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get_user_ual(env->regs[7], env->regs[11] - 36);
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get_user_ual(env->regs[8], env->regs[11] - 32);
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get_user_ual(env->regs[9], env->regs[11] - 28);
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get_user_ual(env->regs[10], env->regs[11] - 24);
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get_user_ual(env->regs[11], env->regs[11] - 20);
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xtensa_rfwu(env);
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}
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void cpu_loop(CPUXtensaState *env)
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{
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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target_siginfo_t info;
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abi_ulong ret;
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int trapnr;
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while (1) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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env->sregs[PS] &= ~PS_EXCM;
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switch (trapnr) {
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case EXCP_INTERRUPT:
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break;
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case EXC_WINDOW_OVERFLOW4:
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xtensa_overflow4(env);
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break;
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case EXC_WINDOW_UNDERFLOW4:
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xtensa_underflow4(env);
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break;
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case EXC_WINDOW_OVERFLOW8:
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xtensa_overflow8(env);
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break;
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case EXC_WINDOW_UNDERFLOW8:
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xtensa_underflow8(env);
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break;
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case EXC_WINDOW_OVERFLOW12:
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xtensa_overflow12(env);
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break;
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case EXC_WINDOW_UNDERFLOW12:
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xtensa_underflow12(env);
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break;
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case EXC_USER:
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switch (env->sregs[EXCCAUSE]) {
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case ILLEGAL_INSTRUCTION_CAUSE:
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case PRIVILEGED_CAUSE:
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info.si_signo = TARGET_SIGILL;
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info.si_errno = 0;
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info.si_code =
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env->sregs[EXCCAUSE] == ILLEGAL_INSTRUCTION_CAUSE ?
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TARGET_ILL_ILLOPC : TARGET_ILL_PRVOPC;
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info._sifields._sigfault._addr = env->sregs[EPC1];
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case SYSCALL_CAUSE:
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env->pc += 3;
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ret = do_syscall(env, env->regs[2],
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env->regs[6], env->regs[3],
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env->regs[4], env->regs[5],
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env->regs[8], env->regs[9], 0, 0);
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switch (ret) {
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default:
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env->regs[2] = ret;
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break;
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case -TARGET_ERESTARTSYS:
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env->pc -= 3;
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break;
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case -TARGET_QEMU_ESIGRETURN:
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break;
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}
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break;
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case ALLOCA_CAUSE:
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env->sregs[PS] = deposit32(env->sregs[PS],
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PS_OWB_SHIFT,
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PS_OWB_LEN,
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env->sregs[WINDOW_BASE]);
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switch (env->regs[0] & 0xc0000000) {
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case 0x00000000:
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case 0x40000000:
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xtensa_rotate_window(env, -1);
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xtensa_underflow4(env);
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break;
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case 0x80000000:
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xtensa_rotate_window(env, -2);
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xtensa_underflow8(env);
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break;
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case 0xc0000000:
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xtensa_rotate_window(env, -3);
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xtensa_underflow12(env);
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break;
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}
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break;
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case INTEGER_DIVIDE_BY_ZERO_CAUSE:
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info.si_signo = TARGET_SIGFPE;
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info.si_errno = 0;
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info.si_code = TARGET_FPE_INTDIV;
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info._sifields._sigfault._addr = env->sregs[EPC1];
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case LOAD_PROHIBITED_CAUSE:
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case STORE_PROHIBITED_CAUSE:
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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info.si_code = TARGET_SEGV_ACCERR;
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info._sifields._sigfault._addr = env->sregs[EXCVADDR];
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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default:
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fprintf(stderr, "exccause = %d\n", env->sregs[EXCCAUSE]);
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g_assert_not_reached();
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}
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break;
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case EXCP_DEBUG:
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2018-10-19 20:49:57 +03:00
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info.si_signo = TARGET_SIGTRAP;
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info.si_errno = 0;
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info.si_code = TARGET_TRAP_BRKPT;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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2018-04-11 21:56:51 +03:00
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break;
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case EXC_DEBUG:
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default:
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fprintf(stderr, "trapnr = %d\n", trapnr);
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g_assert_not_reached();
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}
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process_pending_signals(env);
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}
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}
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2018-04-11 21:56:33 +03:00
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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2018-04-11 21:56:51 +03:00
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int i;
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for (i = 0; i < 16; ++i) {
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env->regs[i] = regs->areg[i];
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}
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env->sregs[WINDOW_START] = regs->windowstart;
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env->pc = regs->pc;
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2018-04-11 21:56:33 +03:00
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}
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