2018-04-24 22:26:16 +03:00
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/*
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* Emulation of Linux signals
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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2018-04-24 22:26:17 +03:00
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#include "qemu/osdep.h"
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#include "qemu.h"
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2021-09-08 18:44:03 +03:00
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#include "user-internals.h"
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2018-04-24 22:26:17 +03:00
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#include "signal-common.h"
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#include "linux-user/trace.h"
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2023-10-24 19:35:05 +03:00
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#include "target/arm/cpu-features.h"
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2018-04-24 22:26:17 +03:00
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struct target_sigcontext {
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uint64_t fault_address;
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/* AArch64 registers */
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uint64_t regs[31];
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uint64_t sp;
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uint64_t pc;
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uint64_t pstate;
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/* 4K reserved for FP/SIMD state and future expansion */
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char __reserved[4096] __attribute__((__aligned__(16)));
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};
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struct target_ucontext {
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abi_ulong tuc_flags;
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abi_ulong tuc_link;
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target_stack_t tuc_stack;
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target_sigset_t tuc_sigmask;
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/* glibc uses a 1024-bit sigset_t */
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char __unused[1024 / 8 - sizeof(target_sigset_t)];
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/* last for future expansion */
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struct target_sigcontext tuc_mcontext;
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};
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/*
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* Header to be used at the beginning of structures extending the user
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* context. Such structures must be placed after the rt_sigframe on the stack
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* and be 16-byte aligned. The last structure must be a dummy one with the
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* magic and size set to 0.
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*/
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struct target_aarch64_ctx {
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uint32_t magic;
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uint32_t size;
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};
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#define TARGET_FPSIMD_MAGIC 0x46508001
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struct target_fpsimd_context {
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struct target_aarch64_ctx head;
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uint32_t fpsr;
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uint32_t fpcr;
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uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */
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};
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#define TARGET_EXTRA_MAGIC 0x45585401
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struct target_extra_context {
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struct target_aarch64_ctx head;
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uint64_t datap; /* 16-byte aligned pointer to extra space cast to __u64 */
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uint32_t size; /* size in bytes of the extra space */
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uint32_t reserved[3];
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};
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#define TARGET_SVE_MAGIC 0x53564501
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struct target_sve_context {
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struct target_aarch64_ctx head;
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uint16_t vl;
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2022-07-08 18:15:30 +03:00
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uint16_t flags;
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uint16_t reserved[2];
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2020-09-17 10:50:25 +03:00
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/* The actual SVE data immediately follows. It is laid out
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2018-04-24 22:26:17 +03:00
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* according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of
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* the original struct pointer.
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*/
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};
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#define TARGET_SVE_VQ_BYTES 16
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#define TARGET_SVE_SIG_ZREG_SIZE(VQ) ((VQ) * TARGET_SVE_VQ_BYTES)
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#define TARGET_SVE_SIG_PREG_SIZE(VQ) ((VQ) * (TARGET_SVE_VQ_BYTES / 8))
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#define TARGET_SVE_SIG_REGS_OFFSET \
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QEMU_ALIGN_UP(sizeof(struct target_sve_context), TARGET_SVE_VQ_BYTES)
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#define TARGET_SVE_SIG_ZREG_OFFSET(VQ, N) \
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(TARGET_SVE_SIG_REGS_OFFSET + TARGET_SVE_SIG_ZREG_SIZE(VQ) * (N))
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#define TARGET_SVE_SIG_PREG_OFFSET(VQ, N) \
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(TARGET_SVE_SIG_ZREG_OFFSET(VQ, 32) + TARGET_SVE_SIG_PREG_SIZE(VQ) * (N))
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#define TARGET_SVE_SIG_FFR_OFFSET(VQ) \
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(TARGET_SVE_SIG_PREG_OFFSET(VQ, 16))
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#define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \
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(TARGET_SVE_SIG_PREG_OFFSET(VQ, 17))
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2022-07-08 18:15:30 +03:00
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#define TARGET_SVE_SIG_FLAG_SM 1
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2022-07-08 18:15:35 +03:00
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#define TARGET_ZA_MAGIC 0x54366345
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struct target_za_context {
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struct target_aarch64_ctx head;
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uint16_t vl;
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uint16_t reserved[3];
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/* The actual ZA data immediately follows. */
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};
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#define TARGET_ZA_SIG_REGS_OFFSET \
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QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES)
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#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \
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(TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N))
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#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \
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TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES)
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2018-04-24 22:26:17 +03:00
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struct target_rt_sigframe {
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struct target_siginfo info;
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struct target_ucontext uc;
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};
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struct target_rt_frame_record {
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uint64_t fp;
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uint64_t lr;
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};
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static void target_setup_general_frame(struct target_rt_sigframe *sf,
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CPUARMState *env, target_sigset_t *set)
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{
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int i;
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__put_user(0, &sf->uc.tuc_flags);
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__put_user(0, &sf->uc.tuc_link);
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2018-04-11 22:23:47 +03:00
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target_save_altstack(&sf->uc.tuc_stack, env);
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2018-04-24 22:26:17 +03:00
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for (i = 0; i < 31; i++) {
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__put_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]);
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}
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__put_user(env->xregs[31], &sf->uc.tuc_mcontext.sp);
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__put_user(env->pc, &sf->uc.tuc_mcontext.pc);
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__put_user(pstate_read(env), &sf->uc.tuc_mcontext.pstate);
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__put_user(env->exception.vaddress, &sf->uc.tuc_mcontext.fault_address);
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for (i = 0; i < TARGET_NSIG_WORDS; i++) {
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__put_user(set->sig[i], &sf->uc.tuc_sigmask.sig[i]);
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}
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}
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static void target_setup_fpsimd_record(struct target_fpsimd_context *fpsimd,
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CPUARMState *env)
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{
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int i;
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__put_user(TARGET_FPSIMD_MAGIC, &fpsimd->head.magic);
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__put_user(sizeof(struct target_fpsimd_context), &fpsimd->head.size);
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__put_user(vfp_get_fpsr(env), &fpsimd->fpsr);
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__put_user(vfp_get_fpcr(env), &fpsimd->fpcr);
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for (i = 0; i < 32; i++) {
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uint64_t *q = aa64_vfp_qreg(env, i);
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2022-03-23 18:57:18 +03:00
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#if TARGET_BIG_ENDIAN
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2018-04-24 22:26:17 +03:00
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__put_user(q[0], &fpsimd->vregs[i * 2 + 1]);
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__put_user(q[1], &fpsimd->vregs[i * 2]);
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#else
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__put_user(q[0], &fpsimd->vregs[i * 2]);
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__put_user(q[1], &fpsimd->vregs[i * 2 + 1]);
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#endif
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}
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}
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static void target_setup_extra_record(struct target_extra_context *extra,
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uint64_t datap, uint32_t extra_size)
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{
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__put_user(TARGET_EXTRA_MAGIC, &extra->head.magic);
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__put_user(sizeof(struct target_extra_context), &extra->head.size);
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__put_user(datap, &extra->datap);
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__put_user(extra_size, &extra->size);
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}
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static void target_setup_end_record(struct target_aarch64_ctx *end)
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{
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__put_user(0, &end->magic);
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__put_user(0, &end->size);
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}
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static void target_setup_sve_record(struct target_sve_context *sve,
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2022-07-08 18:15:35 +03:00
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CPUARMState *env, int size)
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2018-04-24 22:26:17 +03:00
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{
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2022-07-08 18:15:35 +03:00
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int i, j, vq = sve_vq(env);
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2018-04-24 22:26:17 +03:00
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2022-07-08 18:15:30 +03:00
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memset(sve, 0, sizeof(*sve));
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2018-04-24 22:26:17 +03:00
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__put_user(TARGET_SVE_MAGIC, &sve->head.magic);
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__put_user(size, &sve->head.size);
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__put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl);
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2022-07-08 18:15:30 +03:00
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if (FIELD_EX64(env->svcr, SVCR, SM)) {
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__put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags);
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}
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2018-04-24 22:26:17 +03:00
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/* Note that SVE regs are stored as a byte stream, with each byte element
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* at a subsequent address. This corresponds to a little-endian store
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* of our 64-bit hunks.
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*/
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for (i = 0; i < 32; ++i) {
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uint64_t *z = (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i);
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for (j = 0; j < vq * 2; ++j) {
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__put_user_e(env->vfp.zregs[i].d[j], z + j, le);
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}
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}
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for (i = 0; i <= 16; ++i) {
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uint16_t *p = (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i);
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for (j = 0; j < vq; ++j) {
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uint64_t r = env->vfp.pregs[i].p[j >> 2];
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__put_user_e(r >> ((j & 3) * 16), p + j, le);
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}
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}
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}
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2022-07-08 18:15:35 +03:00
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static void target_setup_za_record(struct target_za_context *za,
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CPUARMState *env, int size)
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{
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int vq = sme_vq(env);
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int vl = vq * TARGET_SVE_VQ_BYTES;
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int i, j;
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memset(za, 0, sizeof(*za));
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__put_user(TARGET_ZA_MAGIC, &za->head.magic);
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__put_user(size, &za->head.size);
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__put_user(vl, &za->vl);
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if (size == TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
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return;
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}
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assert(size == TARGET_ZA_SIG_CONTEXT_SIZE(vq));
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/*
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* Note that ZA vectors are stored as a byte stream,
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* with each byte element at a subsequent address.
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*/
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for (i = 0; i < vl; ++i) {
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uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
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for (j = 0; j < vq * 2; ++j) {
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__put_user_e(env->zarray[i].d[j], z + j, le);
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}
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}
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}
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2018-04-24 22:26:17 +03:00
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static void target_restore_general_frame(CPUARMState *env,
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struct target_rt_sigframe *sf)
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{
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sigset_t set;
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uint64_t pstate;
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int i;
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target_to_host_sigset(&set, &sf->uc.tuc_sigmask);
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set_sigmask(&set);
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for (i = 0; i < 31; i++) {
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__get_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]);
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}
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__get_user(env->xregs[31], &sf->uc.tuc_mcontext.sp);
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__get_user(env->pc, &sf->uc.tuc_mcontext.pc);
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__get_user(pstate, &sf->uc.tuc_mcontext.pstate);
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pstate_write(env, pstate);
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}
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static void target_restore_fpsimd_record(CPUARMState *env,
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struct target_fpsimd_context *fpsimd)
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{
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uint32_t fpsr, fpcr;
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int i;
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__get_user(fpsr, &fpsimd->fpsr);
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vfp_set_fpsr(env, fpsr);
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__get_user(fpcr, &fpsimd->fpcr);
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vfp_set_fpcr(env, fpcr);
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for (i = 0; i < 32; i++) {
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uint64_t *q = aa64_vfp_qreg(env, i);
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2022-03-23 18:57:18 +03:00
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#if TARGET_BIG_ENDIAN
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2018-04-24 22:26:17 +03:00
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__get_user(q[0], &fpsimd->vregs[i * 2 + 1]);
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__get_user(q[1], &fpsimd->vregs[i * 2]);
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#else
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__get_user(q[0], &fpsimd->vregs[i * 2]);
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__get_user(q[1], &fpsimd->vregs[i * 2 + 1]);
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#endif
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}
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}
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2022-07-08 18:15:34 +03:00
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static bool target_restore_sve_record(CPUARMState *env,
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struct target_sve_context *sve,
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2022-07-08 18:15:35 +03:00
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int size, int *svcr)
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2018-04-24 22:26:17 +03:00
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{
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2022-07-08 18:15:35 +03:00
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int i, j, vl, vq, flags;
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bool sm;
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__get_user(vl, &sve->vl);
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__get_user(flags, &sve->flags);
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2018-04-24 22:26:17 +03:00
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2022-07-08 18:15:35 +03:00
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sm = flags & TARGET_SVE_SIG_FLAG_SM;
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/* The cpu must support Streaming or Non-streaming SVE. */
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if (sm
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? !cpu_isar_feature(aa64_sme, env_archcpu(env))
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: !cpu_isar_feature(aa64_sve, env_archcpu(env))) {
|
2022-07-08 18:15:34 +03:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2022-07-08 18:15:35 +03:00
|
|
|
/*
|
|
|
|
* Note that we cannot use sve_vq() because that depends on the
|
|
|
|
* current setting of PSTATE.SM, not the state to be restored.
|
|
|
|
*/
|
|
|
|
vq = sve_vqm1_for_el_sm(env, 0, sm) + 1;
|
2022-07-08 18:15:34 +03:00
|
|
|
|
|
|
|
/* Reject mismatched VL. */
|
|
|
|
if (vl != vq * TARGET_SVE_VQ_BYTES) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Accept empty record -- used to clear PSTATE.SM. */
|
|
|
|
if (size <= sizeof(*sve)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Reject non-empty but incomplete record. */
|
|
|
|
if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2022-07-08 18:15:35 +03:00
|
|
|
*svcr = FIELD_DP64(*svcr, SVCR, SM, sm);
|
|
|
|
|
2022-07-08 18:15:34 +03:00
|
|
|
/*
|
|
|
|
* Note that SVE regs are stored as a byte stream, with each byte element
|
2018-04-24 22:26:17 +03:00
|
|
|
* at a subsequent address. This corresponds to a little-endian load
|
|
|
|
* of our 64-bit hunks.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < 32; ++i) {
|
|
|
|
uint64_t *z = (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i);
|
|
|
|
for (j = 0; j < vq * 2; ++j) {
|
|
|
|
__get_user_e(env->vfp.zregs[i].d[j], z + j, le);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
for (i = 0; i <= 16; ++i) {
|
|
|
|
uint16_t *p = (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i);
|
|
|
|
for (j = 0; j < vq; ++j) {
|
|
|
|
uint16_t r;
|
|
|
|
__get_user_e(r, p + j, le);
|
|
|
|
if (j & 3) {
|
|
|
|
env->vfp.pregs[i].p[j >> 2] |= (uint64_t)r << ((j & 3) * 16);
|
|
|
|
} else {
|
|
|
|
env->vfp.pregs[i].p[j >> 2] = r;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2022-07-08 18:15:34 +03:00
|
|
|
return true;
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
|
|
|
|
2022-07-08 18:15:35 +03:00
|
|
|
static bool target_restore_za_record(CPUARMState *env,
|
|
|
|
struct target_za_context *za,
|
|
|
|
int size, int *svcr)
|
|
|
|
{
|
|
|
|
int i, j, vl, vq;
|
|
|
|
|
|
|
|
if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
__get_user(vl, &za->vl);
|
|
|
|
vq = sme_vq(env);
|
|
|
|
|
|
|
|
/* Reject mismatched VL. */
|
|
|
|
if (vl != vq * TARGET_SVE_VQ_BYTES) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Accept empty record -- used to clear PSTATE.ZA. */
|
|
|
|
if (size <= TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Reject non-empty but incomplete record. */
|
|
|
|
if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
*svcr = FIELD_DP64(*svcr, SVCR, ZA, 1);
|
|
|
|
|
|
|
|
for (i = 0; i < vl; ++i) {
|
|
|
|
uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
|
|
|
|
for (j = 0; j < vq * 2; ++j) {
|
|
|
|
__get_user_e(env->zarray[i].d[j], z + j, le);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-04-24 22:26:17 +03:00
|
|
|
static int target_restore_sigframe(CPUARMState *env,
|
|
|
|
struct target_rt_sigframe *sf)
|
|
|
|
{
|
|
|
|
struct target_aarch64_ctx *ctx, *extra = NULL;
|
|
|
|
struct target_fpsimd_context *fpsimd = NULL;
|
|
|
|
struct target_sve_context *sve = NULL;
|
2022-07-08 18:15:35 +03:00
|
|
|
struct target_za_context *za = NULL;
|
2018-04-24 22:26:17 +03:00
|
|
|
uint64_t extra_datap = 0;
|
|
|
|
bool used_extra = false;
|
2022-07-08 18:15:34 +03:00
|
|
|
int sve_size = 0;
|
2022-07-08 18:15:35 +03:00
|
|
|
int za_size = 0;
|
|
|
|
int svcr = 0;
|
2018-04-24 22:26:17 +03:00
|
|
|
|
|
|
|
target_restore_general_frame(env, sf);
|
|
|
|
|
|
|
|
ctx = (struct target_aarch64_ctx *)sf->uc.tuc_mcontext.__reserved;
|
|
|
|
while (ctx) {
|
|
|
|
uint32_t magic, size, extra_size;
|
|
|
|
|
|
|
|
__get_user(magic, &ctx->magic);
|
|
|
|
__get_user(size, &ctx->size);
|
|
|
|
switch (magic) {
|
|
|
|
case 0:
|
|
|
|
if (size != 0) {
|
2022-07-08 18:15:31 +03:00
|
|
|
goto err;
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
|
|
|
if (used_extra) {
|
|
|
|
ctx = NULL;
|
|
|
|
} else {
|
|
|
|
ctx = extra;
|
|
|
|
used_extra = true;
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
|
|
|
|
case TARGET_FPSIMD_MAGIC:
|
|
|
|
if (fpsimd || size != sizeof(struct target_fpsimd_context)) {
|
2022-07-08 18:15:31 +03:00
|
|
|
goto err;
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
|
|
|
fpsimd = (struct target_fpsimd_context *)ctx;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TARGET_SVE_MAGIC:
|
2022-07-08 18:15:32 +03:00
|
|
|
if (sve || size < sizeof(struct target_sve_context)) {
|
|
|
|
goto err;
|
|
|
|
}
|
2022-07-08 18:15:34 +03:00
|
|
|
sve = (struct target_sve_context *)ctx;
|
|
|
|
sve_size = size;
|
|
|
|
break;
|
2018-04-24 22:26:17 +03:00
|
|
|
|
2022-07-08 18:15:35 +03:00
|
|
|
case TARGET_ZA_MAGIC:
|
|
|
|
if (za || size < sizeof(struct target_za_context)) {
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
za = (struct target_za_context *)ctx;
|
|
|
|
za_size = size;
|
|
|
|
break;
|
|
|
|
|
2018-04-24 22:26:17 +03:00
|
|
|
case TARGET_EXTRA_MAGIC:
|
|
|
|
if (extra || size != sizeof(struct target_extra_context)) {
|
2022-07-08 18:15:31 +03:00
|
|
|
goto err;
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
|
|
|
__get_user(extra_datap,
|
|
|
|
&((struct target_extra_context *)ctx)->datap);
|
|
|
|
__get_user(extra_size,
|
|
|
|
&((struct target_extra_context *)ctx)->size);
|
|
|
|
extra = lock_user(VERIFY_READ, extra_datap, extra_size, 0);
|
2022-07-08 18:15:33 +03:00
|
|
|
if (!extra) {
|
|
|
|
return 1;
|
|
|
|
}
|
2018-04-24 22:26:17 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
/* Unknown record -- we certainly didn't generate it.
|
|
|
|
* Did we in fact get out of sync?
|
|
|
|
*/
|
2022-07-08 18:15:31 +03:00
|
|
|
goto err;
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
|
|
|
ctx = (void *)ctx + size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Require FPSIMD always. */
|
|
|
|
if (fpsimd) {
|
|
|
|
target_restore_fpsimd_record(env, fpsimd);
|
|
|
|
} else {
|
2022-07-08 18:15:31 +03:00
|
|
|
goto err;
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* SVE data, if present, overwrites FPSIMD data. */
|
2022-07-08 18:15:35 +03:00
|
|
|
if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) {
|
2022-07-08 18:15:34 +03:00
|
|
|
goto err;
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
2022-07-08 18:15:35 +03:00
|
|
|
if (za && !target_restore_za_record(env, za, za_size, &svcr)) {
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
if (env->svcr != svcr) {
|
|
|
|
env->svcr = svcr;
|
|
|
|
arm_rebuild_hflags(env);
|
|
|
|
}
|
2022-07-08 18:15:31 +03:00
|
|
|
unlock_user(extra, extra_datap, 0);
|
|
|
|
return 0;
|
2018-04-24 22:26:17 +03:00
|
|
|
|
2022-07-08 18:15:31 +03:00
|
|
|
err:
|
2018-04-24 22:26:17 +03:00
|
|
|
unlock_user(extra, extra_datap, 0);
|
2022-07-08 18:15:31 +03:00
|
|
|
return 1;
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static abi_ulong get_sigframe(struct target_sigaction *ka,
|
|
|
|
CPUARMState *env, int size)
|
|
|
|
{
|
|
|
|
abi_ulong sp;
|
|
|
|
|
2018-04-11 22:23:47 +03:00
|
|
|
sp = target_sigsp(get_sp_from_cpustate(env), ka);
|
2018-04-24 22:26:17 +03:00
|
|
|
|
|
|
|
sp = (sp - size) & ~15;
|
|
|
|
|
|
|
|
return sp;
|
|
|
|
}
|
|
|
|
|
|
|
|
typedef struct {
|
|
|
|
int total_size;
|
|
|
|
int extra_base;
|
|
|
|
int extra_size;
|
|
|
|
int std_end_ofs;
|
|
|
|
int extra_ofs;
|
|
|
|
int extra_end_ofs;
|
|
|
|
} target_sigframe_layout;
|
|
|
|
|
|
|
|
static int alloc_sigframe_space(int this_size, target_sigframe_layout *l)
|
|
|
|
{
|
|
|
|
/* Make sure there will always be space for the end marker. */
|
|
|
|
const int std_size = sizeof(struct target_rt_sigframe)
|
|
|
|
- sizeof(struct target_aarch64_ctx);
|
|
|
|
int this_loc = l->total_size;
|
|
|
|
|
|
|
|
if (l->extra_base) {
|
|
|
|
/* Once we have begun an extra space, all allocations go there. */
|
|
|
|
l->extra_size += this_size;
|
|
|
|
} else if (this_size + this_loc > std_size) {
|
|
|
|
/* This allocation does not fit in the standard space. */
|
|
|
|
/* Allocate the extra record. */
|
|
|
|
l->extra_ofs = this_loc;
|
|
|
|
l->total_size += sizeof(struct target_extra_context);
|
|
|
|
|
|
|
|
/* Allocate the standard end record. */
|
|
|
|
l->std_end_ofs = l->total_size;
|
|
|
|
l->total_size += sizeof(struct target_aarch64_ctx);
|
|
|
|
|
|
|
|
/* Allocate the requested record. */
|
|
|
|
l->extra_base = this_loc = l->total_size;
|
|
|
|
l->extra_size = this_size;
|
|
|
|
}
|
|
|
|
l->total_size += this_size;
|
|
|
|
|
|
|
|
return this_loc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void target_setup_frame(int usig, struct target_sigaction *ka,
|
|
|
|
target_siginfo_t *info, target_sigset_t *set,
|
|
|
|
CPUARMState *env)
|
|
|
|
{
|
|
|
|
target_sigframe_layout layout = {
|
|
|
|
/* Begin with the size pointing to the reserved space. */
|
|
|
|
.total_size = offsetof(struct target_rt_sigframe,
|
|
|
|
uc.tuc_mcontext.__reserved),
|
|
|
|
};
|
2022-07-08 18:15:35 +03:00
|
|
|
int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0;
|
|
|
|
int sve_size = 0, za_size = 0;
|
2018-04-24 22:26:17 +03:00
|
|
|
struct target_rt_sigframe *frame;
|
|
|
|
struct target_rt_frame_record *fr;
|
|
|
|
abi_ulong frame_addr, return_addr;
|
|
|
|
|
|
|
|
/* FPSIMD record is always in the standard space. */
|
|
|
|
fpsimd_ofs = alloc_sigframe_space(sizeof(struct target_fpsimd_context),
|
|
|
|
&layout);
|
|
|
|
|
|
|
|
/* SVE state needs saving only if it exists. */
|
2022-07-08 18:15:35 +03:00
|
|
|
if (cpu_isar_feature(aa64_sve, env_archcpu(env)) ||
|
|
|
|
cpu_isar_feature(aa64_sme, env_archcpu(env))) {
|
|
|
|
sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)), 16);
|
2018-04-24 22:26:17 +03:00
|
|
|
sve_ofs = alloc_sigframe_space(sve_size, &layout);
|
|
|
|
}
|
2022-07-08 18:15:35 +03:00
|
|
|
if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
|
|
|
|
/* ZA state needs saving only if it is enabled. */
|
|
|
|
if (FIELD_EX64(env->svcr, SVCR, ZA)) {
|
|
|
|
za_size = TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env));
|
|
|
|
} else {
|
|
|
|
za_size = TARGET_ZA_SIG_CONTEXT_SIZE(0);
|
|
|
|
}
|
|
|
|
za_ofs = alloc_sigframe_space(za_size, &layout);
|
|
|
|
}
|
2018-04-24 22:26:17 +03:00
|
|
|
|
|
|
|
if (layout.extra_ofs) {
|
|
|
|
/* Reserve space for the extra end marker. The standard end marker
|
|
|
|
* will have been allocated when we allocated the extra record.
|
|
|
|
*/
|
|
|
|
layout.extra_end_ofs
|
|
|
|
= alloc_sigframe_space(sizeof(struct target_aarch64_ctx), &layout);
|
|
|
|
} else {
|
|
|
|
/* Reserve space for the standard end marker.
|
|
|
|
* Do not use alloc_sigframe_space because we cheat
|
|
|
|
* std_size therein to reserve space for this.
|
|
|
|
*/
|
|
|
|
layout.std_end_ofs = layout.total_size;
|
|
|
|
layout.total_size += sizeof(struct target_aarch64_ctx);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We must always provide at least the standard 4K reserved space,
|
|
|
|
* even if we don't use all of it (this is part of the ABI)
|
|
|
|
*/
|
|
|
|
layout.total_size = MAX(layout.total_size,
|
|
|
|
sizeof(struct target_rt_sigframe));
|
|
|
|
|
2021-09-29 16:05:29 +03:00
|
|
|
/*
|
|
|
|
* Reserve space for the standard frame unwind pair: fp, lr.
|
|
|
|
* Despite the name this is not a "real" record within the frame.
|
2018-04-24 22:26:17 +03:00
|
|
|
*/
|
|
|
|
fr_ofs = layout.total_size;
|
|
|
|
layout.total_size += sizeof(struct target_rt_frame_record);
|
|
|
|
|
|
|
|
frame_addr = get_sigframe(ka, env, layout.total_size);
|
|
|
|
trace_user_setup_frame(env, frame_addr);
|
|
|
|
frame = lock_user(VERIFY_WRITE, frame_addr, layout.total_size, 0);
|
|
|
|
if (!frame) {
|
|
|
|
goto give_sigsegv;
|
|
|
|
}
|
|
|
|
|
|
|
|
target_setup_general_frame(frame, env, set);
|
|
|
|
target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env);
|
|
|
|
target_setup_end_record((void *)frame + layout.std_end_ofs);
|
|
|
|
if (layout.extra_ofs) {
|
|
|
|
target_setup_extra_record((void *)frame + layout.extra_ofs,
|
|
|
|
frame_addr + layout.extra_base,
|
|
|
|
layout.extra_size);
|
|
|
|
target_setup_end_record((void *)frame + layout.extra_end_ofs);
|
|
|
|
}
|
|
|
|
if (sve_ofs) {
|
2022-07-08 18:15:35 +03:00
|
|
|
target_setup_sve_record((void *)frame + sve_ofs, env, sve_size);
|
|
|
|
}
|
|
|
|
if (za_ofs) {
|
|
|
|
target_setup_za_record((void *)frame + za_ofs, env, za_size);
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Set up the stack frame for unwinding. */
|
|
|
|
fr = (void *)frame + fr_ofs;
|
|
|
|
__put_user(env->xregs[29], &fr->fp);
|
|
|
|
__put_user(env->xregs[30], &fr->lr);
|
|
|
|
|
|
|
|
if (ka->sa_flags & TARGET_SA_RESTORER) {
|
|
|
|
return_addr = ka->sa_restorer;
|
|
|
|
} else {
|
2021-09-29 16:05:29 +03:00
|
|
|
return_addr = default_rt_sigreturn;
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
|
|
|
env->xregs[0] = usig;
|
|
|
|
env->xregs[29] = frame_addr + fr_ofs;
|
|
|
|
env->xregs[30] = return_addr;
|
2020-10-21 20:37:38 +03:00
|
|
|
env->xregs[31] = frame_addr;
|
|
|
|
env->pc = ka->_sa_handler;
|
|
|
|
|
|
|
|
/* Invoke the signal handler as if by indirect call. */
|
|
|
|
if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
|
|
|
|
env->btype = 2;
|
|
|
|
}
|
|
|
|
|
2023-01-12 13:24:33 +03:00
|
|
|
/* Invoke the signal handler with both SM and ZA disabled. */
|
2023-01-12 13:24:32 +03:00
|
|
|
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
|
2022-07-08 18:15:35 +03:00
|
|
|
|
2018-04-24 22:26:17 +03:00
|
|
|
if (info) {
|
2024-03-09 06:08:58 +03:00
|
|
|
frame->info = *info;
|
2018-04-24 22:26:17 +03:00
|
|
|
env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);
|
|
|
|
env->xregs[2] = frame_addr + offsetof(struct target_rt_sigframe, uc);
|
|
|
|
}
|
|
|
|
|
|
|
|
unlock_user(frame, frame_addr, layout.total_size);
|
|
|
|
return;
|
|
|
|
|
|
|
|
give_sigsegv:
|
|
|
|
unlock_user(frame, frame_addr, layout.total_size);
|
|
|
|
force_sigsegv(usig);
|
|
|
|
}
|
|
|
|
|
|
|
|
void setup_rt_frame(int sig, struct target_sigaction *ka,
|
|
|
|
target_siginfo_t *info, target_sigset_t *set,
|
|
|
|
CPUARMState *env)
|
|
|
|
{
|
|
|
|
target_setup_frame(sig, ka, info, set, env);
|
|
|
|
}
|
|
|
|
|
|
|
|
void setup_frame(int sig, struct target_sigaction *ka,
|
|
|
|
target_sigset_t *set, CPUARMState *env)
|
|
|
|
{
|
|
|
|
target_setup_frame(sig, ka, 0, set, env);
|
|
|
|
}
|
|
|
|
|
|
|
|
long do_rt_sigreturn(CPUARMState *env)
|
|
|
|
{
|
|
|
|
struct target_rt_sigframe *frame = NULL;
|
|
|
|
abi_ulong frame_addr = env->xregs[31];
|
|
|
|
|
|
|
|
trace_user_do_rt_sigreturn(env, frame_addr);
|
|
|
|
if (frame_addr & 15) {
|
|
|
|
goto badframe;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) {
|
|
|
|
goto badframe;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (target_restore_sigframe(env, frame)) {
|
|
|
|
goto badframe;
|
|
|
|
}
|
|
|
|
|
2021-04-26 05:53:13 +03:00
|
|
|
target_restore_altstack(&frame->uc.tuc_stack, env);
|
2018-04-24 22:26:17 +03:00
|
|
|
|
|
|
|
unlock_user_struct(frame, frame_addr, 0);
|
2021-11-17 16:14:52 +03:00
|
|
|
return -QEMU_ESIGRETURN;
|
2018-04-24 22:26:17 +03:00
|
|
|
|
|
|
|
badframe:
|
|
|
|
unlock_user_struct(frame, frame_addr, 0);
|
|
|
|
force_sig(TARGET_SIGSEGV);
|
2021-11-17 16:14:52 +03:00
|
|
|
return -QEMU_ESIGRETURN;
|
2018-04-24 22:26:17 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
long do_sigreturn(CPUARMState *env)
|
|
|
|
{
|
|
|
|
return do_rt_sigreturn(env);
|
|
|
|
}
|
2021-09-29 16:05:29 +03:00
|
|
|
|
|
|
|
void setup_sigtramp(abi_ulong sigtramp_page)
|
|
|
|
{
|
|
|
|
uint32_t *tramp = lock_user(VERIFY_WRITE, sigtramp_page, 8, 0);
|
|
|
|
assert(tramp != NULL);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* mov x8,#__NR_rt_sigreturn; svc #0
|
|
|
|
* Since these are instructions they need to be put as little-endian
|
|
|
|
* regardless of target default or current CPU endianness.
|
|
|
|
*/
|
|
|
|
__put_user_e(0xd2801168, &tramp[0], le);
|
|
|
|
__put_user_e(0xd4000001, &tramp[1], le);
|
|
|
|
|
|
|
|
default_rt_sigreturn = sigtramp_page;
|
|
|
|
unlock_user(tramp, sigtramp_page, 8);
|
|
|
|
}
|