313 lines
12 KiB
C
313 lines
12 KiB
C
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/*
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* SD Association Host Standard Specification v2.0 controller emulation
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Mitsyanko Igor <i.mitsyanko@samsung.com>
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* Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
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*
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* Based on MMC controller for Samsung S5PC1xx-based board emulation
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* by Alexey Merkulov and Vladimir Monakhov.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SDHCI_H
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#define SDHCI_H
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#include "qemu-common.h"
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#include "sysbus.h"
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#include "sd.h"
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/* R/W SDMA System Address register 0x0 */
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#define SDHC_SYSAD 0x00
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/* R/W Host DMA Buffer Boundary and Transfer Block Size Register 0x0 */
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#define SDHC_BLKSIZE 0x04
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/* R/W Blocks count for current transfer 0x0 */
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#define SDHC_BLKCNT 0x06
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/* R/W Command Argument Register 0x0 */
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#define SDHC_ARGUMENT 0x08
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/* R/W Transfer Mode Setting Register 0x0 */
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#define SDHC_TRNMOD 0x0C
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#define SDHC_TRNS_DMA 0x0001
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#define SDHC_TRNS_BLK_CNT_EN 0x0002
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#define SDHC_TRNS_ACMD12 0x0004
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#define SDHC_TRNS_READ 0x0010
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#define SDHC_TRNS_MULTI 0x0020
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/* R/W Command Register 0x0 */
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#define SDHC_CMDREG 0x0E
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#define SDHC_CMD_RSP_WITH_BUSY (3 << 0)
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#define SDHC_CMD_DATA_PRESENT (1 << 5)
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#define SDHC_CMD_SUSPEND (1 << 6)
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#define SDHC_CMD_RESUME (1 << 7)
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#define SDHC_CMD_ABORT ((1 << 6)|(1 << 7))
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#define SDHC_CMD_TYPE_MASK ((1 << 6)|(1 << 7))
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#define SDHC_COMMAND_TYPE(x) ((x) & SDHC_CMD_TYPE_MASK)
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/* ROC Response Register 0 0x0 */
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#define SDHC_RSPREG0 0x10
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/* ROC Response Register 1 0x0 */
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#define SDHC_RSPREG1 0x14
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/* ROC Response Register 2 0x0 */
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#define SDHC_RSPREG2 0x18
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/* ROC Response Register 3 0x0 */
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#define SDHC_RSPREG3 0x1C
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/* R/W Buffer Data Register 0x0 */
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#define SDHC_BDATA 0x20
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/* R/ROC Present State Register 0x000A0000 */
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#define SDHC_PRNSTS 0x24
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#define SDHC_CMD_INHIBIT 0x00000001
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#define SDHC_DATA_INHIBIT 0x00000002
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#define SDHC_DAT_LINE_ACTIVE 0x00000004
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#define SDHC_DOING_WRITE 0x00000100
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#define SDHC_DOING_READ 0x00000200
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#define SDHC_SPACE_AVAILABLE 0x00000400
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#define SDHC_DATA_AVAILABLE 0x00000800
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#define SDHC_CARD_PRESENT 0x00010000
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#define SDHC_CARD_DETECT 0x00040000
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#define SDHC_WRITE_PROTECT 0x00080000
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#define TRANSFERRING_DATA(x) \
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((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE))
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/* R/W Host control Register 0x0 */
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#define SDHC_HOSTCTL 0x28
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#define SDHC_CTRL_DMA_CHECK_MASK 0x18
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#define SDHC_CTRL_SDMA 0x00
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#define SDHC_CTRL_ADMA1_32 0x08
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#define SDHC_CTRL_ADMA2_32 0x10
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#define SDHC_CTRL_ADMA2_64 0x18
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#define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK)
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/* R/W Power Control Register 0x0 */
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#define SDHC_PWRCON 0x29
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#define SDHC_POWER_ON (1 << 0)
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/* R/W Block Gap Control Register 0x0 */
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#define SDHC_BLKGAP 0x2A
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#define SDHC_STOP_AT_GAP_REQ 0x01
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#define SDHC_CONTINUE_REQ 0x02
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/* R/W WakeUp Control Register 0x0 */
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#define SDHC_WAKCON 0x2B
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#define SDHC_WKUP_ON_INS (1 << 1)
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#define SDHC_WKUP_ON_RMV (1 << 2)
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/* CLKCON */
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#define SDHC_CLKCON 0x2C
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#define SDHC_CLOCK_INT_STABLE 0x0002
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#define SDHC_CLOCK_INT_EN 0x0001
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#define SDHC_CLOCK_SDCLK_EN (1 << 2)
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#define SDHC_CLOCK_CHK_MASK 0x0007
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#define SDHC_CLOCK_IS_ON(x) \
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(((x) & SDHC_CLOCK_CHK_MASK) == SDHC_CLOCK_CHK_MASK)
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/* R/W Timeout Control Register 0x0 */
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#define SDHC_TIMEOUTCON 0x2E
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/* R/W Software Reset Register 0x0 */
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#define SDHC_SWRST 0x2F
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#define SDHC_RESET_ALL 0x01
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#define SDHC_RESET_CMD 0x02
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#define SDHC_RESET_DATA 0x04
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/* ROC/RW1C Normal Interrupt Status Register 0x0 */
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#define SDHC_NORINTSTS 0x30
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#define SDHC_NIS_ERR 0x8000
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#define SDHC_NIS_CMDCMP 0x0001
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#define SDHC_NIS_TRSCMP 0x0002
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#define SDHC_NIS_BLKGAP 0x0004
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#define SDHC_NIS_DMA 0x0008
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#define SDHC_NIS_WBUFRDY 0x0010
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#define SDHC_NIS_RBUFRDY 0x0020
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#define SDHC_NIS_INSERT 0x0040
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#define SDHC_NIS_REMOVE 0x0080
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#define SDHC_NIS_CARDINT 0x0100
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/* ROC/RW1C Error Interrupt Status Register 0x0 */
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#define SDHC_ERRINTSTS 0x32
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#define SDHC_EIS_CMDTIMEOUT 0x0001
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#define SDHC_EIS_BLKGAP 0x0004
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#define SDHC_EIS_CMDIDX 0x0008
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#define SDHC_EIS_CMD12ERR 0x0100
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#define SDHC_EIS_ADMAERR 0x0200
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/* R/W Normal Interrupt Status Enable Register 0x0 */
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#define SDHC_NORINTSTSEN 0x34
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#define SDHC_NISEN_CMDCMP 0x0001
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#define SDHC_NISEN_TRSCMP 0x0002
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#define SDHC_NISEN_DMA 0x0008
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#define SDHC_NISEN_WBUFRDY 0x0010
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#define SDHC_NISEN_RBUFRDY 0x0020
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#define SDHC_NISEN_INSERT 0x0040
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#define SDHC_NISEN_REMOVE 0x0080
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#define SDHC_NISEN_CARDINT 0x0100
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/* R/W Error Interrupt Status Enable Register 0x0 */
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#define SDHC_ERRINTSTSEN 0x36
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#define SDHC_EISEN_CMDTIMEOUT 0x0001
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#define SDHC_EISEN_BLKGAP 0x0004
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#define SDHC_EISEN_CMDIDX 0x0008
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#define SDHC_EISEN_ADMAERR 0x0200
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/* R/W Normal Interrupt Signal Enable Register 0x0 */
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#define SDHC_NORINTSIGEN 0x38
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#define SDHC_NORINTSIG_INSERT (1 << 6)
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#define SDHC_NORINTSIG_REMOVE (1 << 7)
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/* R/W Error Interrupt Signal Enable Register 0x0 */
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#define SDHC_ERRINTSIGEN 0x3A
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/* ROC Auto CMD12 error status register 0x0 */
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#define SDHC_ACMD12ERRSTS 0x3C
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/* HWInit Capabilities Register 0x05E80080 */
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#define SDHC_CAPAREG 0x40
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#define SDHC_CAN_DO_DMA 0x00400000
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#define SDHC_CAN_DO_ADMA2 0x00080000
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#define SDHC_CAN_DO_ADMA1 0x00100000
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#define SDHC_64_BIT_BUS_SUPPORT (1 << 28)
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#define SDHC_CAPAB_BLOCKSIZE(x) (((x) >> 16) & 0x3)
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/* HWInit Maximum Current Capabilities Register 0x0 */
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#define SDHC_MAXCURR 0x48
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/* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */
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#define SDHC_FEAER 0x50
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/* W Force Event Error Interrupt Register Error Interrupt 0x0000 */
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#define SDHC_FEERR 0x52
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/* R/W ADMA Error Status Register 0x00 */
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#define SDHC_ADMAERR 0x54
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#define SDHC_ADMAERR_LENGTH_MISMATCH (1 << 2)
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#define SDHC_ADMAERR_STATE_ST_STOP (0 << 0)
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#define SDHC_ADMAERR_STATE_ST_FDS (1 << 0)
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#define SDHC_ADMAERR_STATE_ST_TFR (3 << 0)
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#define SDHC_ADMAERR_STATE_MASK (3 << 0)
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/* R/W ADMA System Address Register 0x00 */
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#define SDHC_ADMASYSADDR 0x58
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#define SDHC_ADMA_ATTR_SET_LEN (1 << 4)
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#define SDHC_ADMA_ATTR_ACT_TRAN (1 << 5)
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#define SDHC_ADMA_ATTR_ACT_LINK (3 << 4)
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#define SDHC_ADMA_ATTR_INT (1 << 2)
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#define SDHC_ADMA_ATTR_END (1 << 1)
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#define SDHC_ADMA_ATTR_VALID (1 << 0)
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#define SDHC_ADMA_ATTR_ACT_MASK ((1 << 4)|(1 << 5))
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/* Slot interrupt status */
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#define SDHC_SLOT_INT_STATUS 0xFC
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/* HWInit Host Controller Version Register 0x0401 */
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#define SDHC_HCVER 0xFE
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#define SD_HOST_SPECv2_VERS 0x2401
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#define SDHC_REGISTERS_MAP_SIZE 0x100
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#define SDHC_INSERTION_DELAY (get_ticks_per_sec())
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#define SDHC_TRANSFER_DELAY 100
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#define SDHC_ADMA_DESCS_PER_DELAY 5
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#define SDHC_CMD_RESPONSE (3 << 0)
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enum {
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sdhc_not_stopped = 0, /* normal SDHC state */
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sdhc_gap_read = 1, /* SDHC stopped at block gap during read operation */
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sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */
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};
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/* SD/MMC host controller state */
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typedef struct SDHCIState {
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SysBusDevice busdev;
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SDState *card;
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MemoryRegion iomem;
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QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
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QEMUTimer *transfer_timer;
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qemu_irq eject_cb;
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qemu_irq ro_cb;
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qemu_irq irq;
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uint32_t sdmasysad; /* SDMA System Address register */
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uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
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uint16_t blkcnt; /* Blocks count for current transfer */
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uint32_t argument; /* Command Argument Register */
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uint16_t trnmod; /* Transfer Mode Setting Register */
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uint16_t cmdreg; /* Command Register */
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uint32_t rspreg[4]; /* Response Registers 0-3 */
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uint32_t prnsts; /* Present State Register */
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uint8_t hostctl; /* Host Control Register */
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uint8_t pwrcon; /* Power control Register */
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uint8_t blkgap; /* Block Gap Control Register */
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uint8_t wakcon; /* WakeUp Control Register */
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uint16_t clkcon; /* Clock control Register */
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uint8_t timeoutcon; /* Timeout Control Register */
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uint8_t admaerr; /* ADMA Error Status Register */
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uint16_t norintsts; /* Normal Interrupt Status Register */
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uint16_t errintsts; /* Error Interrupt Status Register */
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uint16_t norintstsen; /* Normal Interrupt Status Enable Register */
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uint16_t errintstsen; /* Error Interrupt Status Enable Register */
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uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */
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uint16_t errintsigen; /* Error Interrupt Signal Enable Register */
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uint16_t acmd12errsts; /* Auto CMD12 error status register */
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uint64_t admasysaddr; /* ADMA System Address Register */
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uint32_t capareg; /* Capabilities Register */
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uint32_t maxcurr; /* Maximum Current Capabilities Register */
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uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
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uint32_t buf_maxsz;
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uint16_t data_count; /* current element in FIFO buffer */
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uint8_t stopped_state;/* Current SDHC state */
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/* Buffer Data Port Register - virtual access point to R and W buffers */
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/* Software Reset Register - always reads as 0 */
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/* Force Event Auto CMD12 Error Interrupt Reg - write only */
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/* Force Event Error Interrupt Register- write only */
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/* RO Host Controller Version Register always reads as 0x2401 */
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} SDHCIState;
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typedef struct SDHCIClass {
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SysBusDeviceClass busdev_class;
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void (*reset)(SDHCIState *s);
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uint32_t (*mem_read)(SDHCIState *s, unsigned int offset, unsigned size);
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void (*mem_write)(SDHCIState *s, unsigned int offset, uint32_t value,
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unsigned size);
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void (*send_command)(SDHCIState *s);
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bool (*can_issue_command)(SDHCIState *s);
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void (*data_transfer)(SDHCIState *s);
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void (*end_data_transfer)(SDHCIState *s);
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void (*do_sdma_single)(SDHCIState *s);
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void (*do_sdma_multi)(SDHCIState *s);
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void (*do_adma)(SDHCIState *s);
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void (*read_block_from_card)(SDHCIState *s);
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void (*write_block_to_card)(SDHCIState *s);
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uint32_t (*bdata_read)(SDHCIState *s, unsigned size);
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void (*bdata_write)(SDHCIState *s, uint32_t value, unsigned size);
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} SDHCIClass;
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extern const VMStateDescription sdhci_vmstate;
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#define TYPE_SDHCI "generic-sdhci"
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#define SDHCI(obj) \
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OBJECT_CHECK(SDHCIState, (obj), TYPE_SDHCI)
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#define SDHCI_CLASS(klass) \
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OBJECT_CLASS_CHECK(SDHCIClass, (klass), TYPE_SDHCI)
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#define SDHCI_GET_CLASS(obj) \
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OBJECT_GET_CLASS(SDHCIClass, (obj), TYPE_SDHCI)
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#endif /* SDHCI_H */
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