112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
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/*
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* Header file for the Xilinx Versal's OSPI controller
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*
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* Copyright (C) 2021 Xilinx Inc
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* Written by Francisco Iglesias <francisco.iglesias@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* This is a model of Xilinx Versal's Octal SPI flash memory controller
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* documented in Versal's Technical Reference manual [1] and the Versal ACAP
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* Register reference [2].
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*
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* References:
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*
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* [1] Versal ACAP Technical Reference Manual,
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* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
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*
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* [2] Versal ACAP Register Reference,
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* https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___ospi.html
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*
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*
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* QEMU interface:
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* + sysbus MMIO region 0: MemoryRegion for the device's registers
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* + sysbus MMIO region 1: MemoryRegion for flash memory linear address space
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* (data transfer).
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* + sysbus IRQ 0: Device interrupt.
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* + Named GPIO input "ospi-mux-sel": 0: enables indirect access mode
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* and 1: enables direct access mode.
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* + Property "dac-with-indac": Allow both direct accesses and indirect
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* accesses simultaneously.
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* + Property "indac-write-disabled": Disable indirect access writes.
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*/
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#ifndef XILINX_VERSAL_OSPI_H
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#define XILINX_VERSAL_OSPI_H
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#include "hw/register.h"
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#include "hw/ssi/ssi.h"
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#include "qemu/fifo8.h"
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#include "hw/dma/xlnx_csu_dma.h"
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#define TYPE_XILINX_VERSAL_OSPI "xlnx.versal-ospi"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalOspi, XILINX_VERSAL_OSPI)
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#define XILINX_VERSAL_OSPI_R_MAX (0xfc / 4 + 1)
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/*
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* Indirect operations
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*/
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typedef struct IndOp {
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uint32_t flash_addr;
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uint32_t num_bytes;
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uint32_t done_bytes;
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bool completed;
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} IndOp;
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struct XlnxVersalOspi {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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MemoryRegion iomem_dac;
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uint8_t num_cs;
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qemu_irq *cs_lines;
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SSIBus *spi;
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Fifo8 rx_fifo;
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Fifo8 tx_fifo;
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Fifo8 rx_sram;
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Fifo8 tx_sram;
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qemu_irq irq;
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XlnxCSUDMA *dma_src;
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bool ind_write_disabled;
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bool dac_with_indac;
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bool dac_enable;
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bool src_dma_inprog;
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IndOp rd_ind_op[2];
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IndOp wr_ind_op[2];
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uint32_t regs[XILINX_VERSAL_OSPI_R_MAX];
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RegisterInfo regs_info[XILINX_VERSAL_OSPI_R_MAX];
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/* Maximum inferred membank size is 512 bytes */
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uint8_t stig_membank[512];
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};
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#endif /* XILINX_VERSAL_OSPI_H */
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