2014-09-01 15:59:46 +04:00
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/*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h>
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#include "cpu.h"
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#include "qemu/host-utils.h"
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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2014-09-26 23:36:09 +04:00
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/* Addressing mode helper */
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static uint16_t reverse16(uint16_t val)
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{
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uint8_t high = (uint8_t)(val >> 8);
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uint8_t low = (uint8_t)(val & 0xff);
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uint16_t rh, rl;
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rl = (uint16_t)((high * 0x0202020202ULL & 0x010884422010ULL) % 1023);
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rh = (uint16_t)((low * 0x0202020202ULL & 0x010884422010ULL) % 1023);
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return (rh << 8) | rl;
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}
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uint32_t helper_br_update(uint32_t reg)
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{
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uint32_t index = reg & 0xffff;
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uint32_t incr = reg >> 16;
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uint32_t new_index = reverse16(reverse16(index) + reverse16(incr));
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return reg - index + new_index;
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}
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uint32_t helper_circ_update(uint32_t reg, uint32_t off)
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{
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uint32_t index = reg & 0xffff;
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uint32_t length = reg >> 16;
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int32_t new_index = index + off;
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if (new_index < 0) {
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new_index += length;
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} else {
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new_index %= length;
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}
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return reg - index + new_index;
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}
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2014-09-01 15:59:52 +04:00
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#define SSOV(env, ret, arg, len) do { \
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int64_t max_pos = INT##len ##_MAX; \
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int64_t max_neg = INT##len ##_MIN; \
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if (arg > max_pos) { \
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env->PSW_USB_V = (1 << 31); \
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env->PSW_USB_SV = (1 << 31); \
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ret = (target_ulong)max_pos; \
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} else { \
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if (arg < max_neg) { \
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env->PSW_USB_V = (1 << 31); \
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env->PSW_USB_SV = (1 << 31); \
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ret = (target_ulong)max_neg; \
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} else { \
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env->PSW_USB_V = 0; \
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ret = (target_ulong)arg; \
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} \
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} \
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env->PSW_USB_AV = arg ^ arg * 2u; \
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env->PSW_USB_SAV |= env->PSW_USB_AV; \
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} while (0)
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target-tricore: Add instructions of RC opcode format
Add instructions of RC opcode format.
Add helper for mul, sha, absdif with signed saturation on overflow.
Add helper for add, sub, mul with unsigned saturation on overflow.
Add microcode generator functions:
* gen_add_CC, which calculates the carry bit.
* gen_addc_CC, which adds the carry bit to the add and calculates the carry bit.
* gen_absdif, which calculates the absolute difference.
* gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg.
* gen_sh_hi, which shifts two 16bit words in one reg.
* gen_sha_hi, which does a arithmetic shift on two 16bit words.
* gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb.
* gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
with the lsb of the result.
* gen_eqany_bi/hi, which checks ever byte/hword on equality.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-27 00:49:41 +03:00
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#define SUOV(env, ret, arg, len) do { \
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int64_t max_pos = UINT##len ##_MAX; \
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if (arg > max_pos) { \
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env->PSW_USB_V = (1 << 31); \
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env->PSW_USB_SV = (1 << 31); \
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ret = (target_ulong)max_pos; \
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} else { \
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if (arg < 0) { \
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env->PSW_USB_V = (1 << 31); \
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env->PSW_USB_SV = (1 << 31); \
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ret = 0; \
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} else { \
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env->PSW_USB_V = 0; \
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ret = (target_ulong)arg; \
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} \
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} \
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env->PSW_USB_AV = arg ^ arg * 2u; \
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env->PSW_USB_SAV |= env->PSW_USB_AV; \
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} while (0)
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2014-09-01 15:59:52 +04:00
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target_ulong helper_add_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t2 = sextract64(r2, 0, 32);
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int64_t result = t1 + t2;
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SSOV(env, ret, result, 32);
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return ret;
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}
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target-tricore: Add instructions of RC opcode format
Add instructions of RC opcode format.
Add helper for mul, sha, absdif with signed saturation on overflow.
Add helper for add, sub, mul with unsigned saturation on overflow.
Add microcode generator functions:
* gen_add_CC, which calculates the carry bit.
* gen_addc_CC, which adds the carry bit to the add and calculates the carry bit.
* gen_absdif, which calculates the absolute difference.
* gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg.
* gen_sh_hi, which shifts two 16bit words in one reg.
* gen_sha_hi, which does a arithmetic shift on two 16bit words.
* gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb.
* gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
with the lsb of the result.
* gen_eqany_bi/hi, which checks ever byte/hword on equality.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-27 00:49:41 +03:00
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target_ulong helper_add_suov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = extract64(r1, 0, 32);
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int64_t t2 = extract64(r2, 0, 32);
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int64_t result = t1 + t2;
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SUOV(env, ret, result, 32);
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return ret;
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}
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2014-09-01 15:59:52 +04:00
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target_ulong helper_sub_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t2 = sextract64(r2, 0, 32);
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int64_t result = t1 - t2;
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SSOV(env, ret, result, 32);
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return ret;
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}
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target-tricore: Add instructions of RC opcode format
Add instructions of RC opcode format.
Add helper for mul, sha, absdif with signed saturation on overflow.
Add helper for add, sub, mul with unsigned saturation on overflow.
Add microcode generator functions:
* gen_add_CC, which calculates the carry bit.
* gen_addc_CC, which adds the carry bit to the add and calculates the carry bit.
* gen_absdif, which calculates the absolute difference.
* gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg.
* gen_sh_hi, which shifts two 16bit words in one reg.
* gen_sha_hi, which does a arithmetic shift on two 16bit words.
* gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb.
* gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
with the lsb of the result.
* gen_eqany_bi/hi, which checks ever byte/hword on equality.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-27 00:49:41 +03:00
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target_ulong helper_sub_suov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = extract64(r1, 0, 32);
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int64_t t2 = extract64(r2, 0, 32);
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int64_t result = t1 - t2;
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SUOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_mul_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t2 = sextract64(r2, 0, 32);
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int64_t result = t1 * t2;
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SSOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_mul_suov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = extract64(r1, 0, 32);
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int64_t t2 = extract64(r2, 0, 32);
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int64_t result = t1 * t2;
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SUOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_sha_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int32_t t2 = sextract64(r2, 0, 6);
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int64_t result;
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if (t2 == 0) {
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result = t1;
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} else if (t2 > 0) {
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result = t1 << t2;
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} else {
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result = t1 >> -t2;
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}
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SSOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_absdif_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t2 = sextract64(r2, 0, 32);
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int64_t result;
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if (t1 > t2) {
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result = t1 - t2;
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} else {
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result = t2 - t1;
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}
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SSOV(env, ret, result, 32);
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return ret;
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}
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2014-11-02 20:31:45 +03:00
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target_ulong helper_madd32_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2, target_ulong r3)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t2 = sextract64(r2, 0, 32);
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int64_t t3 = sextract64(r3, 0, 32);
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int64_t result;
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result = t2 + (t1 * t3);
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SSOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_madd32_suov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2, target_ulong r3)
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{
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target_ulong ret;
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uint64_t t1 = extract64(r1, 0, 32);
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uint64_t t2 = extract64(r2, 0, 32);
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uint64_t t3 = extract64(r3, 0, 32);
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int64_t result;
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result = t2 + (t1 * t3);
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SUOV(env, ret, result, 32);
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return ret;
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}
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uint64_t helper_madd64_ssov(CPUTriCoreState *env, target_ulong r1,
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uint64_t r2, target_ulong r3)
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{
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uint64_t ret, ovf;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t3 = sextract64(r3, 0, 32);
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int64_t mul;
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mul = t1 * t3;
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ret = mul + r2;
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ovf = (ret ^ mul) & ~(mul ^ r2);
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if ((int64_t)ovf < 0) {
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env->PSW_USB_V = (1 << 31);
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env->PSW_USB_SV = (1 << 31);
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/* ext_ret > MAX_INT */
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if (mul >= 0) {
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ret = INT64_MAX;
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/* ext_ret < MIN_INT */
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} else {
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ret = INT64_MIN;
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}
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} else {
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env->PSW_USB_V = 0;
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}
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t1 = ret >> 32;
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env->PSW_USB_AV = t1 ^ t1 * 2u;
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env->PSW_USB_SAV |= env->PSW_USB_AV;
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return ret;
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}
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uint64_t helper_madd64_suov(CPUTriCoreState *env, target_ulong r1,
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uint64_t r2, target_ulong r3)
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{
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uint64_t ret, mul;
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uint64_t t1 = extract64(r1, 0, 32);
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uint64_t t3 = extract64(r3, 0, 32);
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mul = t1 * t3;
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ret = mul + r2;
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if (ret < r2) {
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env->PSW_USB_V = (1 << 31);
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|
env->PSW_USB_SV = (1 << 31);
|
|
|
|
|
/* saturate */
|
|
|
|
|
ret = UINT64_MAX;
|
|
|
|
|
} else {
|
|
|
|
|
env->PSW_USB_V = 0;
|
|
|
|
|
}
|
|
|
|
|
t1 = ret >> 32;
|
|
|
|
|
env->PSW_USB_AV = t1 ^ t1 * 2u;
|
|
|
|
|
env->PSW_USB_SAV |= env->PSW_USB_AV;
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
target_ulong helper_msub32_ssov(CPUTriCoreState *env, target_ulong r1,
|
|
|
|
|
target_ulong r2, target_ulong r3)
|
|
|
|
|
{
|
|
|
|
|
target_ulong ret;
|
|
|
|
|
int64_t t1 = sextract64(r1, 0, 32);
|
|
|
|
|
int64_t t2 = sextract64(r2, 0, 32);
|
|
|
|
|
int64_t t3 = sextract64(r3, 0, 32);
|
|
|
|
|
int64_t result;
|
|
|
|
|
|
|
|
|
|
result = t2 - (t1 * t3);
|
|
|
|
|
SSOV(env, ret, result, 32);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
target_ulong helper_msub32_suov(CPUTriCoreState *env, target_ulong r1,
|
|
|
|
|
target_ulong r2, target_ulong r3)
|
|
|
|
|
{
|
|
|
|
|
target_ulong ret;
|
|
|
|
|
int64_t t1 = extract64(r1, 0, 32);
|
|
|
|
|
int64_t t2 = extract64(r2, 0, 32);
|
|
|
|
|
int64_t t3 = extract64(r3, 0, 32);
|
|
|
|
|
int64_t result;
|
|
|
|
|
|
|
|
|
|
result = t2 - (t1 * t3);
|
|
|
|
|
SUOV(env, ret, result, 32);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint64_t helper_msub64_ssov(CPUTriCoreState *env, target_ulong r1,
|
|
|
|
|
uint64_t r2, target_ulong r3)
|
|
|
|
|
{
|
|
|
|
|
uint64_t ret, ovf;
|
|
|
|
|
int64_t t1 = sextract64(r1, 0, 32);
|
|
|
|
|
int64_t t3 = sextract64(r3, 0, 32);
|
|
|
|
|
int64_t mul;
|
|
|
|
|
|
|
|
|
|
mul = t1 * t3;
|
|
|
|
|
ret = r2 - mul;
|
|
|
|
|
ovf = (ret ^ r2) & (mul ^ r2);
|
|
|
|
|
|
|
|
|
|
if ((int64_t)ovf < 0) {
|
|
|
|
|
env->PSW_USB_V = (1 << 31);
|
|
|
|
|
env->PSW_USB_SV = (1 << 31);
|
|
|
|
|
/* ext_ret > MAX_INT */
|
|
|
|
|
if (mul < 0) {
|
|
|
|
|
ret = INT64_MAX;
|
|
|
|
|
/* ext_ret < MIN_INT */
|
|
|
|
|
} else {
|
|
|
|
|
ret = INT64_MIN;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
env->PSW_USB_V = 0;
|
|
|
|
|
}
|
|
|
|
|
t1 = ret >> 32;
|
|
|
|
|
env->PSW_USB_AV = t1 ^ t1 * 2u;
|
|
|
|
|
env->PSW_USB_SAV |= env->PSW_USB_AV;
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint64_t helper_msub64_suov(CPUTriCoreState *env, target_ulong r1,
|
|
|
|
|
uint64_t r2, target_ulong r3)
|
|
|
|
|
{
|
|
|
|
|
uint64_t ret, mul;
|
|
|
|
|
uint64_t t1 = extract64(r1, 0, 32);
|
|
|
|
|
uint64_t t3 = extract64(r3, 0, 32);
|
|
|
|
|
|
|
|
|
|
mul = t1 * t3;
|
|
|
|
|
ret = r2 - mul;
|
|
|
|
|
|
|
|
|
|
if (ret > r2) {
|
|
|
|
|
env->PSW_USB_V = (1 << 31);
|
|
|
|
|
env->PSW_USB_SV = (1 << 31);
|
|
|
|
|
/* saturate */
|
|
|
|
|
ret = 0;
|
|
|
|
|
} else {
|
|
|
|
|
env->PSW_USB_V = 0;
|
|
|
|
|
}
|
|
|
|
|
t1 = ret >> 32;
|
|
|
|
|
env->PSW_USB_AV = t1 ^ t1 * 2u;
|
|
|
|
|
env->PSW_USB_SAV |= env->PSW_USB_AV;
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 15:59:55 +04:00
|
|
|
|
/* context save area (CSA) related helpers */
|
|
|
|
|
|
|
|
|
|
static int cdc_increment(target_ulong *psw)
|
|
|
|
|
{
|
|
|
|
|
if ((*psw & MASK_PSW_CDC) == 0x7f) {
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
(*psw)++;
|
|
|
|
|
/* check for overflow */
|
|
|
|
|
int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
|
|
|
|
|
int mask = (1u << (7 - lo)) - 1;
|
|
|
|
|
int count = *psw & mask;
|
|
|
|
|
if (count == 0) {
|
|
|
|
|
(*psw)--;
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int cdc_decrement(target_ulong *psw)
|
|
|
|
|
{
|
|
|
|
|
if ((*psw & MASK_PSW_CDC) == 0x7f) {
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
/* check for underflow */
|
|
|
|
|
int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
|
|
|
|
|
int mask = (1u << (7 - lo)) - 1;
|
|
|
|
|
int count = *psw & mask;
|
|
|
|
|
if (count == 0) {
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
(*psw)--;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 16:00:00 +04:00
|
|
|
|
static bool cdc_zero(target_ulong *psw)
|
|
|
|
|
{
|
|
|
|
|
int cdc = *psw & MASK_PSW_CDC;
|
|
|
|
|
/* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
|
|
|
|
|
7'b1111111, otherwise returns FALSE. */
|
|
|
|
|
if (cdc == 0x7f) {
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
/* find CDC.COUNT */
|
|
|
|
|
int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
|
|
|
|
|
int mask = (1u << (7 - lo)) - 1;
|
|
|
|
|
int count = *psw & mask;
|
|
|
|
|
return count == 0;
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-26 23:04:51 +04:00
|
|
|
|
static void save_context_upper(CPUTriCoreState *env, int ea)
|
2014-09-01 15:59:55 +04:00
|
|
|
|
{
|
|
|
|
|
cpu_stl_data(env, ea, env->PCXI);
|
|
|
|
|
cpu_stl_data(env, ea+4, env->PSW);
|
|
|
|
|
cpu_stl_data(env, ea+8, env->gpr_a[10]);
|
|
|
|
|
cpu_stl_data(env, ea+12, env->gpr_a[11]);
|
|
|
|
|
cpu_stl_data(env, ea+16, env->gpr_d[8]);
|
|
|
|
|
cpu_stl_data(env, ea+20, env->gpr_d[9]);
|
|
|
|
|
cpu_stl_data(env, ea+24, env->gpr_d[10]);
|
|
|
|
|
cpu_stl_data(env, ea+28, env->gpr_d[11]);
|
|
|
|
|
cpu_stl_data(env, ea+32, env->gpr_a[12]);
|
|
|
|
|
cpu_stl_data(env, ea+36, env->gpr_a[13]);
|
|
|
|
|
cpu_stl_data(env, ea+40, env->gpr_a[14]);
|
|
|
|
|
cpu_stl_data(env, ea+44, env->gpr_a[15]);
|
|
|
|
|
cpu_stl_data(env, ea+48, env->gpr_d[12]);
|
|
|
|
|
cpu_stl_data(env, ea+52, env->gpr_d[13]);
|
|
|
|
|
cpu_stl_data(env, ea+56, env->gpr_d[14]);
|
|
|
|
|
cpu_stl_data(env, ea+60, env->gpr_d[15]);
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-26 23:04:51 +04:00
|
|
|
|
static void save_context_lower(CPUTriCoreState *env, int ea)
|
2014-09-01 15:59:58 +04:00
|
|
|
|
{
|
|
|
|
|
cpu_stl_data(env, ea, env->PCXI);
|
2014-09-26 23:04:51 +04:00
|
|
|
|
cpu_stl_data(env, ea+4, env->gpr_a[11]);
|
2014-09-01 15:59:58 +04:00
|
|
|
|
cpu_stl_data(env, ea+8, env->gpr_a[2]);
|
|
|
|
|
cpu_stl_data(env, ea+12, env->gpr_a[3]);
|
|
|
|
|
cpu_stl_data(env, ea+16, env->gpr_d[0]);
|
|
|
|
|
cpu_stl_data(env, ea+20, env->gpr_d[1]);
|
|
|
|
|
cpu_stl_data(env, ea+24, env->gpr_d[2]);
|
|
|
|
|
cpu_stl_data(env, ea+28, env->gpr_d[3]);
|
|
|
|
|
cpu_stl_data(env, ea+32, env->gpr_a[4]);
|
|
|
|
|
cpu_stl_data(env, ea+36, env->gpr_a[5]);
|
|
|
|
|
cpu_stl_data(env, ea+40, env->gpr_a[6]);
|
|
|
|
|
cpu_stl_data(env, ea+44, env->gpr_a[7]);
|
|
|
|
|
cpu_stl_data(env, ea+48, env->gpr_d[4]);
|
|
|
|
|
cpu_stl_data(env, ea+52, env->gpr_d[5]);
|
|
|
|
|
cpu_stl_data(env, ea+56, env->gpr_d[6]);
|
|
|
|
|
cpu_stl_data(env, ea+60, env->gpr_d[7]);
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 15:59:55 +04:00
|
|
|
|
static void restore_context_upper(CPUTriCoreState *env, int ea,
|
|
|
|
|
target_ulong *new_PCXI, target_ulong *new_PSW)
|
|
|
|
|
{
|
|
|
|
|
*new_PCXI = cpu_ldl_data(env, ea);
|
|
|
|
|
*new_PSW = cpu_ldl_data(env, ea+4);
|
|
|
|
|
env->gpr_a[10] = cpu_ldl_data(env, ea+8);
|
|
|
|
|
env->gpr_a[11] = cpu_ldl_data(env, ea+12);
|
|
|
|
|
env->gpr_d[8] = cpu_ldl_data(env, ea+16);
|
|
|
|
|
env->gpr_d[9] = cpu_ldl_data(env, ea+20);
|
|
|
|
|
env->gpr_d[10] = cpu_ldl_data(env, ea+24);
|
|
|
|
|
env->gpr_d[11] = cpu_ldl_data(env, ea+28);
|
|
|
|
|
env->gpr_a[12] = cpu_ldl_data(env, ea+32);
|
|
|
|
|
env->gpr_a[13] = cpu_ldl_data(env, ea+36);
|
|
|
|
|
env->gpr_a[14] = cpu_ldl_data(env, ea+40);
|
|
|
|
|
env->gpr_a[15] = cpu_ldl_data(env, ea+44);
|
|
|
|
|
env->gpr_d[12] = cpu_ldl_data(env, ea+48);
|
|
|
|
|
env->gpr_d[13] = cpu_ldl_data(env, ea+52);
|
|
|
|
|
env->gpr_d[14] = cpu_ldl_data(env, ea+56);
|
|
|
|
|
env->gpr_d[15] = cpu_ldl_data(env, ea+60);
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-26 23:26:31 +04:00
|
|
|
|
static void restore_context_lower(CPUTriCoreState *env, int ea,
|
|
|
|
|
target_ulong *ra, target_ulong *pcxi)
|
|
|
|
|
{
|
|
|
|
|
*pcxi = cpu_ldl_data(env, ea);
|
|
|
|
|
*ra = cpu_ldl_data(env, ea+4);
|
|
|
|
|
env->gpr_a[2] = cpu_ldl_data(env, ea+8);
|
|
|
|
|
env->gpr_a[3] = cpu_ldl_data(env, ea+12);
|
|
|
|
|
env->gpr_d[0] = cpu_ldl_data(env, ea+16);
|
|
|
|
|
env->gpr_d[1] = cpu_ldl_data(env, ea+20);
|
|
|
|
|
env->gpr_d[2] = cpu_ldl_data(env, ea+24);
|
|
|
|
|
env->gpr_d[3] = cpu_ldl_data(env, ea+28);
|
|
|
|
|
env->gpr_a[4] = cpu_ldl_data(env, ea+32);
|
|
|
|
|
env->gpr_a[5] = cpu_ldl_data(env, ea+36);
|
|
|
|
|
env->gpr_a[6] = cpu_ldl_data(env, ea+40);
|
|
|
|
|
env->gpr_a[7] = cpu_ldl_data(env, ea+44);
|
|
|
|
|
env->gpr_d[4] = cpu_ldl_data(env, ea+48);
|
|
|
|
|
env->gpr_d[5] = cpu_ldl_data(env, ea+52);
|
|
|
|
|
env->gpr_d[6] = cpu_ldl_data(env, ea+56);
|
|
|
|
|
env->gpr_d[7] = cpu_ldl_data(env, ea+60);
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 15:59:55 +04:00
|
|
|
|
void helper_call(CPUTriCoreState *env, uint32_t next_pc)
|
|
|
|
|
{
|
|
|
|
|
target_ulong tmp_FCX;
|
|
|
|
|
target_ulong ea;
|
|
|
|
|
target_ulong new_FCX;
|
|
|
|
|
target_ulong psw;
|
|
|
|
|
|
|
|
|
|
psw = psw_read(env);
|
|
|
|
|
/* if (FCX == 0) trap(FCU); */
|
|
|
|
|
if (env->FCX == 0) {
|
|
|
|
|
/* FCU trap */
|
|
|
|
|
}
|
|
|
|
|
/* if (PSW.CDE) then if (cdc_increment()) then trap(CDO); */
|
|
|
|
|
if (psw & MASK_PSW_CDE) {
|
|
|
|
|
if (cdc_increment(&psw)) {
|
|
|
|
|
/* CDO trap */
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
/* PSW.CDE = 1;*/
|
|
|
|
|
psw |= MASK_PSW_CDE;
|
|
|
|
|
/* tmp_FCX = FCX; */
|
|
|
|
|
tmp_FCX = env->FCX;
|
|
|
|
|
/* EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; */
|
|
|
|
|
ea = ((env->FCX & MASK_FCX_FCXS) << 12) +
|
|
|
|
|
((env->FCX & MASK_FCX_FCXO) << 6);
|
2014-09-26 23:04:51 +04:00
|
|
|
|
/* new_FCX = M(EA, word); */
|
|
|
|
|
new_FCX = cpu_ldl_data(env, ea);
|
|
|
|
|
/* M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],
|
|
|
|
|
A[12], A[13], A[14], A[15], D[12], D[13], D[14],
|
|
|
|
|
D[15]}; */
|
|
|
|
|
save_context_upper(env, ea);
|
2014-09-01 15:59:55 +04:00
|
|
|
|
|
|
|
|
|
/* PCXI.PCPN = ICR.CCPN; */
|
|
|
|
|
env->PCXI = (env->PCXI & 0xffffff) +
|
|
|
|
|
((env->ICR & MASK_ICR_CCPN) << 24);
|
|
|
|
|
/* PCXI.PIE = ICR.IE; */
|
|
|
|
|
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
|
|
|
|
|
((env->ICR & MASK_ICR_IE) << 15));
|
|
|
|
|
/* PCXI.UL = 1; */
|
|
|
|
|
env->PCXI |= MASK_PCXI_UL;
|
|
|
|
|
|
|
|
|
|
/* PCXI[19: 0] = FCX[19: 0]; */
|
|
|
|
|
env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
|
|
|
|
|
/* FCX[19: 0] = new_FCX[19: 0]; */
|
|
|
|
|
env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
|
|
|
|
|
/* A[11] = next_pc[31: 0]; */
|
|
|
|
|
env->gpr_a[11] = next_pc;
|
|
|
|
|
|
|
|
|
|
/* if (tmp_FCX == LCX) trap(FCD);*/
|
|
|
|
|
if (tmp_FCX == env->LCX) {
|
|
|
|
|
/* FCD trap */
|
|
|
|
|
}
|
|
|
|
|
psw_write(env, psw);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void helper_ret(CPUTriCoreState *env)
|
|
|
|
|
{
|
|
|
|
|
target_ulong ea;
|
|
|
|
|
target_ulong new_PCXI;
|
|
|
|
|
target_ulong new_PSW, psw;
|
|
|
|
|
|
|
|
|
|
psw = psw_read(env);
|
|
|
|
|
/* if (PSW.CDE) then if (cdc_decrement()) then trap(CDU);*/
|
|
|
|
|
if (env->PSW & MASK_PSW_CDE) {
|
|
|
|
|
if (cdc_decrement(&(env->PSW))) {
|
|
|
|
|
/* CDU trap */
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
/* if (PCXI[19: 0] == 0) then trap(CSU); */
|
|
|
|
|
if ((env->PCXI & 0xfffff) == 0) {
|
|
|
|
|
/* CSU trap */
|
|
|
|
|
}
|
|
|
|
|
/* if (PCXI.UL == 0) then trap(CTYP); */
|
|
|
|
|
if ((env->PCXI & MASK_PCXI_UL) == 0) {
|
|
|
|
|
/* CTYP trap */
|
|
|
|
|
}
|
|
|
|
|
/* PC = {A11 [31: 1], 1’b0}; */
|
|
|
|
|
env->PC = env->gpr_a[11] & 0xfffffffe;
|
|
|
|
|
|
|
|
|
|
/* EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; */
|
|
|
|
|
ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
|
|
|
|
|
((env->PCXI & MASK_PCXI_PCXO) << 6);
|
|
|
|
|
/* {new_PCXI, new_PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
|
2014-09-26 23:04:51 +04:00
|
|
|
|
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
|
2014-09-01 15:59:55 +04:00
|
|
|
|
restore_context_upper(env, ea, &new_PCXI, &new_PSW);
|
2014-09-26 23:04:51 +04:00
|
|
|
|
/* M(EA, word) = FCX; */
|
|
|
|
|
cpu_stl_data(env, ea, env->FCX);
|
2014-09-01 15:59:55 +04:00
|
|
|
|
/* FCX[19: 0] = PCXI[19: 0]; */
|
|
|
|
|
env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
|
|
|
|
|
/* PCXI = new_PCXI; */
|
|
|
|
|
env->PCXI = new_PCXI;
|
|
|
|
|
|
|
|
|
|
if (tricore_feature(env, TRICORE_FEATURE_13)) {
|
|
|
|
|
/* PSW = new_PSW */
|
|
|
|
|
psw_write(env, new_PSW);
|
|
|
|
|
} else {
|
|
|
|
|
/* PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]}; */
|
|
|
|
|
psw_write(env, (new_PSW & ~(0x3000000)) + (psw & (0x3000000)));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 15:59:58 +04:00
|
|
|
|
void helper_bisr(CPUTriCoreState *env, uint32_t const9)
|
|
|
|
|
{
|
|
|
|
|
target_ulong tmp_FCX;
|
|
|
|
|
target_ulong ea;
|
|
|
|
|
target_ulong new_FCX;
|
|
|
|
|
|
|
|
|
|
if (env->FCX == 0) {
|
|
|
|
|
/* FCU trap */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
tmp_FCX = env->FCX;
|
|
|
|
|
ea = ((env->FCX & 0xf0000) << 12) + ((env->FCX & 0xffff) << 6);
|
|
|
|
|
|
2014-09-26 23:04:51 +04:00
|
|
|
|
/* new_FCX = M(EA, word); */
|
|
|
|
|
new_FCX = cpu_ldl_data(env, ea);
|
|
|
|
|
/* M(EA, 16 * word) = {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4]
|
|
|
|
|
, A[5], A[6], A[7], D[4], D[5], D[6], D[7]}; */
|
|
|
|
|
save_context_lower(env, ea);
|
|
|
|
|
|
2014-09-01 15:59:58 +04:00
|
|
|
|
|
|
|
|
|
/* PCXI.PCPN = ICR.CCPN */
|
|
|
|
|
env->PCXI = (env->PCXI & 0xffffff) +
|
|
|
|
|
((env->ICR & MASK_ICR_CCPN) << 24);
|
|
|
|
|
/* PCXI.PIE = ICR.IE */
|
|
|
|
|
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
|
|
|
|
|
((env->ICR & MASK_ICR_IE) << 15));
|
|
|
|
|
/* PCXI.UL = 0 */
|
|
|
|
|
env->PCXI &= ~(MASK_PCXI_UL);
|
|
|
|
|
/* PCXI[19: 0] = FCX[19: 0] */
|
|
|
|
|
env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
|
|
|
|
|
/* FXC[19: 0] = new_FCX[19: 0] */
|
|
|
|
|
env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
|
|
|
|
|
/* ICR.IE = 1 */
|
|
|
|
|
env->ICR |= MASK_ICR_IE;
|
|
|
|
|
|
|
|
|
|
env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/
|
|
|
|
|
|
|
|
|
|
if (tmp_FCX == env->LCX) {
|
|
|
|
|
/* FCD trap */
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 16:00:00 +04:00
|
|
|
|
void helper_rfe(CPUTriCoreState *env)
|
|
|
|
|
{
|
|
|
|
|
target_ulong ea;
|
|
|
|
|
target_ulong new_PCXI;
|
|
|
|
|
target_ulong new_PSW;
|
|
|
|
|
/* if (PCXI[19: 0] == 0) then trap(CSU); */
|
|
|
|
|
if ((env->PCXI & 0xfffff) == 0) {
|
|
|
|
|
/* raise csu trap */
|
|
|
|
|
}
|
|
|
|
|
/* if (PCXI.UL == 0) then trap(CTYP); */
|
|
|
|
|
if ((env->PCXI & MASK_PCXI_UL) == 0) {
|
|
|
|
|
/* raise CTYP trap */
|
|
|
|
|
}
|
|
|
|
|
/* if (!cdc_zero() AND PSW.CDE) then trap(NEST); */
|
|
|
|
|
if (!cdc_zero(&(env->PSW)) && (env->PSW & MASK_PSW_CDE)) {
|
|
|
|
|
/* raise MNG trap */
|
|
|
|
|
}
|
|
|
|
|
/* ICR.IE = PCXI.PIE; */
|
|
|
|
|
env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
|
|
|
|
|
/* ICR.CCPN = PCXI.PCPN; */
|
|
|
|
|
env->ICR = (env->ICR & ~MASK_ICR_CCPN) +
|
|
|
|
|
((env->PCXI & MASK_PCXI_PCPN) >> 24);
|
|
|
|
|
/*EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};*/
|
|
|
|
|
ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
|
|
|
|
|
((env->PCXI & MASK_PCXI_PCXO) << 6);
|
|
|
|
|
/*{new_PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
|
2014-09-26 23:04:51 +04:00
|
|
|
|
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
|
2014-09-01 16:00:00 +04:00
|
|
|
|
restore_context_upper(env, ea, &new_PCXI, &new_PSW);
|
2014-09-26 23:04:51 +04:00
|
|
|
|
/* M(EA, word) = FCX;*/
|
|
|
|
|
cpu_stl_data(env, ea, env->FCX);
|
2014-09-01 16:00:00 +04:00
|
|
|
|
/* FCX[19: 0] = PCXI[19: 0]; */
|
|
|
|
|
env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
|
|
|
|
|
/* PCXI = new_PCXI; */
|
|
|
|
|
env->PCXI = new_PCXI;
|
|
|
|
|
/* write psw */
|
|
|
|
|
psw_write(env, new_PSW);
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-26 23:26:31 +04:00
|
|
|
|
void helper_ldlcx(CPUTriCoreState *env, uint32_t ea)
|
|
|
|
|
{
|
|
|
|
|
uint32_t dummy;
|
|
|
|
|
/* insn doesn't load PCXI and RA */
|
|
|
|
|
restore_context_lower(env, ea, &dummy, &dummy);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void helper_lducx(CPUTriCoreState *env, uint32_t ea)
|
|
|
|
|
{
|
|
|
|
|
uint32_t dummy;
|
|
|
|
|
/* insn doesn't load PCXI and PSW */
|
|
|
|
|
restore_context_upper(env, ea, &dummy, &dummy);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void helper_stlcx(CPUTriCoreState *env, uint32_t ea)
|
|
|
|
|
{
|
|
|
|
|
save_context_lower(env, ea);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void helper_stucx(CPUTriCoreState *env, uint32_t ea)
|
|
|
|
|
{
|
|
|
|
|
save_context_upper(env, ea);
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-30 15:06:53 +03:00
|
|
|
|
void helper_psw_write(CPUTriCoreState *env, uint32_t arg)
|
|
|
|
|
{
|
|
|
|
|
psw_write(env, arg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint32_t helper_psw_read(CPUTriCoreState *env)
|
|
|
|
|
{
|
|
|
|
|
return psw_read(env);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2014-09-01 15:59:48 +04:00
|
|
|
|
static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
|
|
|
|
|
uint32_t exception,
|
|
|
|
|
int error_code,
|
|
|
|
|
uintptr_t pc)
|
|
|
|
|
{
|
|
|
|
|
CPUState *cs = CPU(tricore_env_get_cpu(env));
|
|
|
|
|
cs->exception_index = exception;
|
|
|
|
|
env->error_code = error_code;
|
|
|
|
|
|
|
|
|
|
if (pc) {
|
|
|
|
|
/* now we have a real cpu fault */
|
|
|
|
|
cpu_restore_state(cs, pc);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
cpu_loop_exit(cs);
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 15:59:46 +04:00
|
|
|
|
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
|
|
|
|
|
uintptr_t retaddr)
|
|
|
|
|
{
|
2014-09-01 15:59:48 +04:00
|
|
|
|
int ret;
|
|
|
|
|
ret = cpu_tricore_handle_mmu_fault(cs, addr, is_write, mmu_idx);
|
|
|
|
|
if (ret) {
|
|
|
|
|
TriCoreCPU *cpu = TRICORE_CPU(cs);
|
|
|
|
|
CPUTriCoreState *env = &cpu->env;
|
|
|
|
|
do_raise_exception_err(env, cs->exception_index,
|
|
|
|
|
env->error_code, retaddr);
|
|
|
|
|
}
|
2014-09-01 15:59:46 +04:00
|
|
|
|
}
|