2023-06-12 14:10:34 +03:00
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/*
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* QEMU RISC-V Disassembler for xthead.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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2024-01-25 19:34:01 +03:00
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#include "qemu/osdep.h"
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2023-06-12 14:10:34 +03:00
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#include "disas/riscv.h"
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#include "disas/riscv-xthead.h"
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typedef enum {
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/* 0 is reserved for rv_op_illegal. */
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/* XTheadBa */
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rv_op_th_addsl = 1,
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/* XTheadBb */
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rv_op_th_srri,
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rv_op_th_srriw,
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rv_op_th_ext,
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rv_op_th_extu,
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rv_op_th_ff0,
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rv_op_th_ff1,
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rv_op_th_rev,
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rv_op_th_revw,
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rv_op_th_tstnbz,
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/* XTheadBs */
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rv_op_th_tst,
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/* XTheadCmo */
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rv_op_th_dcache_call,
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rv_op_th_dcache_ciall,
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rv_op_th_dcache_iall,
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rv_op_th_dcache_cpa,
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rv_op_th_dcache_cipa,
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rv_op_th_dcache_ipa,
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rv_op_th_dcache_cva,
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rv_op_th_dcache_civa,
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rv_op_th_dcache_iva,
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rv_op_th_dcache_csw,
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rv_op_th_dcache_cisw,
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rv_op_th_dcache_isw,
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rv_op_th_dcache_cpal1,
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rv_op_th_dcache_cval1,
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rv_op_th_icache_iall,
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rv_op_th_icache_ialls,
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rv_op_th_icache_ipa,
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rv_op_th_icache_iva,
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rv_op_th_l2cache_call,
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rv_op_th_l2cache_ciall,
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rv_op_th_l2cache_iall,
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/* XTheadCondMov */
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rv_op_th_mveqz,
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rv_op_th_mvnez,
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/* XTheadFMemIdx */
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rv_op_th_flrd,
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rv_op_th_flrw,
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rv_op_th_flurd,
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rv_op_th_flurw,
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rv_op_th_fsrd,
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rv_op_th_fsrw,
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rv_op_th_fsurd,
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rv_op_th_fsurw,
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/* XTheadFmv */
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rv_op_th_fmv_hw_x,
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rv_op_th_fmv_x_hw,
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/* XTheadMac */
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rv_op_th_mula,
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rv_op_th_mulah,
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rv_op_th_mulaw,
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rv_op_th_muls,
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rv_op_th_mulsw,
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rv_op_th_mulsh,
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/* XTheadMemIdx */
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rv_op_th_lbia,
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rv_op_th_lbib,
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rv_op_th_lbuia,
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rv_op_th_lbuib,
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rv_op_th_lhia,
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rv_op_th_lhib,
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rv_op_th_lhuia,
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rv_op_th_lhuib,
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rv_op_th_lwia,
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rv_op_th_lwib,
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rv_op_th_lwuia,
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rv_op_th_lwuib,
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rv_op_th_ldia,
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rv_op_th_ldib,
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rv_op_th_sbia,
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rv_op_th_sbib,
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rv_op_th_shia,
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rv_op_th_shib,
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rv_op_th_swia,
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rv_op_th_swib,
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rv_op_th_sdia,
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rv_op_th_sdib,
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rv_op_th_lrb,
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rv_op_th_lrbu,
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rv_op_th_lrh,
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rv_op_th_lrhu,
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rv_op_th_lrw,
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rv_op_th_lrwu,
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rv_op_th_lrd,
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rv_op_th_srb,
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rv_op_th_srh,
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rv_op_th_srw,
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rv_op_th_srd,
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rv_op_th_lurb,
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rv_op_th_lurbu,
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rv_op_th_lurh,
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rv_op_th_lurhu,
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rv_op_th_lurw,
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rv_op_th_lurwu,
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rv_op_th_lurd,
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rv_op_th_surb,
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rv_op_th_surh,
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rv_op_th_surw,
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rv_op_th_surd,
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/* XTheadMemPair */
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rv_op_th_ldd,
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rv_op_th_lwd,
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rv_op_th_lwud,
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rv_op_th_sdd,
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rv_op_th_swd,
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/* XTheadSync */
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rv_op_th_sfence_vmas,
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rv_op_th_sync,
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rv_op_th_sync_i,
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rv_op_th_sync_is,
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rv_op_th_sync_s,
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} rv_xthead_op;
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const rv_opcode_data xthead_opcode_data[] = {
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{ "th.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
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/* XTheadBa */
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{ "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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/* XTheadBb */
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{ "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 },
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{ "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 },
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{ "th.ff0", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "th.ff1", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "th.rev", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "th.revw", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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/* XTheadBs */
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{ "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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/* XTheadCmo */
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{ "th.dcache.call", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
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{ "th.dcache.ciall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
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{ "th.dcache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
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{ "th.dcache.cpa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.dcache.cipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.dcache.ipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.dcache.cva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.dcache.civa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.dcache.iva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.dcache.csw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.dcache.cisw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.dcache.isw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.dcache.cval1", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.icache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
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{ "th.icache.ialls", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
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{ "th.icache.ipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.icache.iva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
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{ "th.l2cache.call", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
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{ "th.l2cache.ciall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
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{ "th.l2cache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
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/* XTheadCondMov */
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{ "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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/* XTheadFMemIdx */
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{ "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
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/* XTheadFmv */
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{ "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
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{ "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
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/* XTheadMac */
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{ "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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/* XTheadMemIdx */
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{ "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 },
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{ "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
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{ "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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{ "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
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|
|
{ "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
/* XTheadMemPair */
|
|
|
|
|
{ "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
|
|
|
|
|
/* XTheadSync */
|
|
|
|
|
{ "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.sync", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.sync.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.sync.is", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
|
|
|
|
{ "th.sync.s", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void decode_xtheadba(rv_decode *dec, rv_isa isa)
|
|
|
|
|
{
|
|
|
|
|
rv_inst inst = dec->inst;
|
|
|
|
|
rv_opcode op = rv_op_illegal;
|
|
|
|
|
|
|
|
|
|
switch (((inst >> 0) & 0b11)) {
|
|
|
|
|
case 3:
|
|
|
|
|
switch (((inst >> 2) & 0b11111)) {
|
|
|
|
|
case 2:
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
switch ((inst >> 12) & 0b111) {
|
|
|
|
|
case 1:
|
|
|
|
|
switch ((inst >> 25) & 0b1111111) {
|
|
|
|
|
case 0b0000000:
|
|
|
|
|
case 0b0000001:
|
|
|
|
|
case 0b0000010:
|
|
|
|
|
case 0b0000011: op = rv_op_th_addsl; break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dec->op = op;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void decode_xtheadbb(rv_decode *dec, rv_isa isa)
|
|
|
|
|
{
|
|
|
|
|
rv_inst inst = dec->inst;
|
|
|
|
|
rv_opcode op = rv_op_illegal;
|
|
|
|
|
|
|
|
|
|
switch (((inst >> 0) & 0b11)) {
|
|
|
|
|
case 3:
|
|
|
|
|
switch (((inst >> 2) & 0b11111)) {
|
|
|
|
|
case 2:
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
switch ((inst >> 12) & 0b111) {
|
|
|
|
|
case 1:
|
|
|
|
|
switch ((inst >> 25) & 0b1111111) {
|
|
|
|
|
case 0b0001010: op = rv_op_th_srriw; break;
|
|
|
|
|
case 0b1000000:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_tstnbz;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b1000001:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_rev;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b1000010:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_ff0;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b1000011:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_ff1;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b1000100:
|
|
|
|
|
case 0b1001000:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_revw;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b0000100:
|
|
|
|
|
case 0b0000101: op = rv_op_th_srri; break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 2: op = rv_op_th_ext; break;
|
|
|
|
|
case 3: op = rv_op_th_extu; break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dec->op = op;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void decode_xtheadbs(rv_decode *dec, rv_isa isa)
|
|
|
|
|
{
|
|
|
|
|
rv_inst inst = dec->inst;
|
|
|
|
|
rv_opcode op = rv_op_illegal;
|
|
|
|
|
|
|
|
|
|
switch (((inst >> 0) & 0b11)) {
|
|
|
|
|
case 3:
|
|
|
|
|
switch (((inst >> 2) & 0b11111)) {
|
|
|
|
|
case 2:
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
switch ((inst >> 12) & 0b111) {
|
|
|
|
|
case 1:
|
|
|
|
|
switch ((inst >> 26) & 0b111111) {
|
|
|
|
|
case 0b100010: op = rv_op_th_tst; break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dec->op = op;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void decode_xtheadcmo(rv_decode *dec, rv_isa isa)
|
|
|
|
|
{
|
|
|
|
|
rv_inst inst = dec->inst;
|
|
|
|
|
rv_opcode op = rv_op_illegal;
|
|
|
|
|
|
|
|
|
|
switch (((inst >> 0) & 0b11)) {
|
|
|
|
|
case 3:
|
|
|
|
|
switch (((inst >> 2) & 0b11111)) {
|
|
|
|
|
case 2:
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
switch ((inst >> 12) & 0b111) {
|
|
|
|
|
case 0:
|
|
|
|
|
switch ((inst >> 20 & 0b111111111111)) {
|
|
|
|
|
case 0b000000000001:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_dcache_call;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b000000000011:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_dcache_ciall;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b000000000010:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_dcache_iall;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b000000101001: op = rv_op_th_dcache_cpa; break;
|
|
|
|
|
case 0b000000101011: op = rv_op_th_dcache_cipa; break;
|
|
|
|
|
case 0b000000101010: op = rv_op_th_dcache_ipa; break;
|
|
|
|
|
case 0b000000100101: op = rv_op_th_dcache_cva; break;
|
|
|
|
|
case 0b000000100111: op = rv_op_th_dcache_civa; break;
|
|
|
|
|
case 0b000000100110: op = rv_op_th_dcache_iva; break;
|
|
|
|
|
case 0b000000100001: op = rv_op_th_dcache_csw; break;
|
|
|
|
|
case 0b000000100011: op = rv_op_th_dcache_cisw; break;
|
|
|
|
|
case 0b000000100010: op = rv_op_th_dcache_isw; break;
|
|
|
|
|
case 0b000000101000: op = rv_op_th_dcache_cpal1; break;
|
|
|
|
|
case 0b000000100100: op = rv_op_th_dcache_cval1; break;
|
|
|
|
|
case 0b000000010000:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_icache_iall;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b000000010001:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_icache_ialls;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b000000111000: op = rv_op_th_icache_ipa; break;
|
|
|
|
|
case 0b000000110000: op = rv_op_th_icache_iva; break;
|
|
|
|
|
case 0b000000010101:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_l2cache_call;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b000000010111:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_l2cache_ciall;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b000000010110:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_l2cache_iall;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dec->op = op;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
|
|
|
|
|
{
|
|
|
|
|
rv_inst inst = dec->inst;
|
|
|
|
|
rv_opcode op = rv_op_illegal;
|
|
|
|
|
|
|
|
|
|
switch (((inst >> 0) & 0b11)) {
|
|
|
|
|
case 3:
|
|
|
|
|
switch (((inst >> 2) & 0b11111)) {
|
|
|
|
|
case 2:
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
switch ((inst >> 12) & 0b111) {
|
|
|
|
|
case 1:
|
|
|
|
|
switch ((inst >> 25) & 0b1111111) {
|
|
|
|
|
case 0b0100000: op = rv_op_th_mveqz; break;
|
|
|
|
|
case 0b0100001: op = rv_op_th_mvnez; break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dec->op = op;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
|
|
|
|
|
{
|
|
|
|
|
rv_inst inst = dec->inst;
|
|
|
|
|
rv_opcode op = rv_op_illegal;
|
|
|
|
|
|
|
|
|
|
switch (((inst >> 0) & 0b11)) {
|
|
|
|
|
case 3:
|
|
|
|
|
switch (((inst >> 2) & 0b11111)) {
|
|
|
|
|
case 2:
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
switch ((inst >> 12) & 0b111) {
|
|
|
|
|
case 6:
|
|
|
|
|
switch ((inst >> 27) & 0b11111) {
|
|
|
|
|
case 8: op = rv_op_th_flrw; break;
|
|
|
|
|
case 10: op = rv_op_th_flurw; break;
|
|
|
|
|
case 12: op = rv_op_th_flrd; break;
|
|
|
|
|
case 14: op = rv_op_th_flurd; break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
switch ((inst >> 27) & 0b11111) {
|
|
|
|
|
case 8: op = rv_op_th_fsrw; break;
|
|
|
|
|
case 10: op = rv_op_th_fsurw; break;
|
|
|
|
|
case 12: op = rv_op_th_fsrd; break;
|
|
|
|
|
case 14: op = rv_op_th_fsurd; break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dec->op = op;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void decode_xtheadfmv(rv_decode *dec, rv_isa isa)
|
|
|
|
|
{
|
|
|
|
|
rv_inst inst = dec->inst;
|
|
|
|
|
rv_opcode op = rv_op_illegal;
|
|
|
|
|
|
|
|
|
|
switch (((inst >> 0) & 0b11)) {
|
|
|
|
|
case 3:
|
|
|
|
|
switch (((inst >> 2) & 0b11111)) {
|
|
|
|
|
case 2:
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
switch ((inst >> 12) & 0b111) {
|
|
|
|
|
case 1:
|
|
|
|
|
switch ((inst >> 25) & 0b1111111) {
|
|
|
|
|
case 0b1010000:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_fmv_hw_x;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0b1100000:
|
|
|
|
|
if (((inst >> 20) & 0b11111) == 0) {
|
|
|
|
|
op = rv_op_th_fmv_x_hw;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
/* custom-0 */
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dec->op = op;
|
|
|
|
|
}
|
|
|
|
|
|
|
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void decode_xtheadmac(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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rv_opcode op = rv_op_illegal;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 1:
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switch ((inst >> 25) & 0b1111111) {
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case 0b0010000: op = rv_op_th_mula; break;
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case 0b0010001: op = rv_op_th_muls; break;
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case 0b0010010: op = rv_op_th_mulaw; break;
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case 0b0010011: op = rv_op_th_mulsw; break;
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case 0b0010100: op = rv_op_th_mulah; break;
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case 0b0010101: op = rv_op_th_mulsh; break;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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dec->op = op;
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}
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void decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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rv_opcode op = rv_op_illegal;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 4:
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switch ((inst >> 27) & 0b11111) {
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case 0: op = rv_op_th_lrb; break;
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case 1: op = rv_op_th_lbib; break;
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case 2: op = rv_op_th_lurb; break;
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case 3: op = rv_op_th_lbia; break;
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case 4: op = rv_op_th_lrh; break;
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case 5: op = rv_op_th_lhib; break;
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case 6: op = rv_op_th_lurh; break;
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case 7: op = rv_op_th_lhia; break;
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case 8: op = rv_op_th_lrw; break;
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case 9: op = rv_op_th_lwib; break;
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case 10: op = rv_op_th_lurw; break;
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case 11: op = rv_op_th_lwia; break;
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case 12: op = rv_op_th_lrd; break;
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case 13: op = rv_op_th_ldib; break;
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case 14: op = rv_op_th_lurd; break;
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case 15: op = rv_op_th_ldia; break;
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case 16: op = rv_op_th_lrbu; break;
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case 17: op = rv_op_th_lbuib; break;
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case 18: op = rv_op_th_lurbu; break;
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case 19: op = rv_op_th_lbuia; break;
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case 20: op = rv_op_th_lrhu; break;
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case 21: op = rv_op_th_lhuib; break;
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case 22: op = rv_op_th_lurhu; break;
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case 23: op = rv_op_th_lhuia; break;
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case 24: op = rv_op_th_lrwu; break;
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case 25: op = rv_op_th_lwuib; break;
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case 26: op = rv_op_th_lurwu; break;
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case 27: op = rv_op_th_lwuia; break;
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}
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break;
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case 5:
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switch ((inst >> 27) & 0b11111) {
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case 0: op = rv_op_th_srb; break;
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case 1: op = rv_op_th_sbib; break;
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case 2: op = rv_op_th_surb; break;
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case 3: op = rv_op_th_sbia; break;
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case 4: op = rv_op_th_srh; break;
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case 5: op = rv_op_th_shib; break;
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case 6: op = rv_op_th_surh; break;
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case 7: op = rv_op_th_shia; break;
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case 8: op = rv_op_th_srw; break;
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case 9: op = rv_op_th_swib; break;
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case 10: op = rv_op_th_surw; break;
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case 11: op = rv_op_th_swia; break;
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case 12: op = rv_op_th_srd; break;
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case 13: op = rv_op_th_sdib; break;
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case 14: op = rv_op_th_surd; break;
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case 15: op = rv_op_th_sdia; break;
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}
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break;
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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dec->op = op;
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}
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void decode_xtheadmempair(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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rv_opcode op = rv_op_illegal;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 4:
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switch ((inst >> 27) & 0b11111) {
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case 28: op = rv_op_th_lwd; break;
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case 30: op = rv_op_th_lwud; break;
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case 31: op = rv_op_th_ldd; break;
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}
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break;
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case 5:
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switch ((inst >> 27) & 0b11111) {
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case 28: op = rv_op_th_swd; break;
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case 31: op = rv_op_th_sdd; break;
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}
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break;
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}
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break;
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/* custom-0 */
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}
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break;
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}
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dec->op = op;
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}
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void decode_xtheadsync(rv_decode *dec, rv_isa isa)
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{
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rv_inst inst = dec->inst;
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rv_opcode op = rv_op_illegal;
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switch (((inst >> 0) & 0b11)) {
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case 3:
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switch (((inst >> 2) & 0b11111)) {
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case 2:
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/* custom-0 */
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switch ((inst >> 12) & 0b111) {
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case 0:
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switch ((inst >> 25) & 0b1111111) {
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case 0b0000010: op = rv_op_th_sfence_vmas; break;
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case 0b0000000:
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switch ((inst >> 20) & 0b11111) {
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case 0b11000: op = rv_op_th_sync; break;
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case 0b11010: op = rv_op_th_sync_i; break;
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case 0b11011: op = rv_op_th_sync_is; break;
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case 0b11001: op = rv_op_th_sync_s; break;
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}
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break;
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}
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break;
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}
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|
break;
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|
|
/* custom-0 */
|
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|
}
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|
break;
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}
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dec->op = op;
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}
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