qemu/include/hw/i386/pc.h

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#ifndef HW_PC_H
#define HW_PC_H
#include "qemu-common.h"
#include "exec/memory.h"
#include "hw/boards.h"
#include "hw/isa/isa.h"
#include "hw/block/fdc.h"
#include "net/net.h"
#include "hw/i386/ioapic.h"
#include "qemu/range.h"
#include "qemu/bitmap.h"
#include "sysemu/sysemu.h"
#include "hw/pci/pci.h"
#include "hw/compat.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
#include "hw/acpi/acpi_dev_interface.h"
#define HPET_INTCAP "hpet-intcap"
/**
* PCMachineState:
* @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
* @boot_cpus: number of present VCPUs
*/
struct PCMachineState {
/*< private >*/
MachineState parent_obj;
/* <public> */
/* State for other subsystems/APIs: */
Notifier machine_done;
/* Pointers to devices and objects: */
HotplugHandler *acpi_dev;
ISADevice *rtc;
PCIBus *bus;
FWCfgState *fw_cfg;
qemu_irq *gsi;
/* Configuration options: */
uint64_t max_ram_below_4g;
OnOffAuto vmport;
OnOffAuto smm;
AcpiNVDIMMState acpi_nvdimm_state;
bool acpi_build_enabled;
bool smbus_enabled;
bool sata_enabled;
bool pit_enabled;
/* RAM information (sizes, addresses, configuration): */
ram_addr_t below_4g_mem_size, above_4g_mem_size;
/* CPU and apic information: */
bool apic_xrupt_override;
unsigned apic_id_limit;
uint16_t boot_cpus;
/* NUMA information: */
uint64_t numa_nodes;
uint64_t *node_mem;
/* Address space used by IOAPIC device. All IOAPIC interrupts
* will be translated to MSI messages in the address space. */
AddressSpace *ioapic_as;
};
#define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
#define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
#define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
#define PC_MACHINE_VMPORT "vmport"
#define PC_MACHINE_SMM "smm"
#define PC_MACHINE_NVDIMM "nvdimm"
#define PC_MACHINE_NVDIMM_PERSIST "nvdimm-persistence"
#define PC_MACHINE_SMBUS "smbus"
#define PC_MACHINE_SATA "sata"
#define PC_MACHINE_PIT "pit"
/**
* PCMachineClass:
*
* Compat fields:
*
* @enforce_aligned_dimm: check that DIMM's address/size is aligned by
* backend's alignment value if provided
* @acpi_data_size: Size of the chunk of memory at the top of RAM
* for the BIOS ACPI tables and other BIOS
* datastructures.
* @gigabyte_align: Make sure that guest addresses aligned at
* 1Gbyte boundaries get mapped to host
* addresses aligned at 1Gbyte boundaries. This
* way we can use 1GByte pages in the host.
*
*/
struct PCMachineClass {
/*< private >*/
MachineClass parent_class;
/*< public >*/
/* Device configuration: */
bool pci_enabled;
bool kvmclock_enabled;
const char *default_nic_model;
/* Compat options: */
/* ACPI compat: */
bool has_acpi_build;
bool rsdp_in_ram;
int legacy_acpi_table_size;
unsigned acpi_data_size;
/* SMBIOS compat: */
bool smbios_defaults;
bool smbios_legacy_mode;
bool smbios_uuid_encoded;
/* RAM / address space compat: */
bool gigabyte_align;
bool has_reserved_memory;
bool enforce_aligned_dimm;
bool broken_reserved_end;
/* TSC rate migration: */
bool save_tsc_khz;
/* generate legacy CPU hotplug AML */
bool legacy_cpu_hotplug;
/* use DMA capable linuxboot option rom */
bool linuxboot_dma_enabled;
};
#define TYPE_PC_MACHINE "generic-pc-machine"
#define PC_MACHINE(obj) \
OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
#define PC_MACHINE_GET_CLASS(obj) \
OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
#define PC_MACHINE_CLASS(klass) \
OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
/* i8259.c */
extern DeviceState *isa_pic;
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
qemu_irq *kvm_i8259_init(ISABus *bus);
int pic_read_irq(DeviceState *d);
int pic_get_output(DeviceState *d);
/* ioapic.c */
/* Global System Interrupts */
#define GSI_NUM_PINS IOAPIC_NUM_PINS
typedef struct GSIState {
qemu_irq i8259_irq[ISA_NUM_IRQS];
qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
} GSIState;
void gsi_handler(void *opaque, int n, int level);
/* vmport.c */
#define TYPE_VMPORT "vmport"
typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
static inline void vmport_init(ISABus *bus)
{
isa_create_simple(bus, TYPE_VMPORT);
}
void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
void vmmouse_get_data(uint32_t *data);
void vmmouse_set_data(const uint32_t *data);
/* pc.c */
extern int fd_bootchk;
bool pc_machine_is_smm_enabled(PCMachineState *pcms);
void pc_register_ferr_irq(qemu_irq irq);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
void pc_cpus_init(PCMachineState *pcms);
void pc_hot_add_cpu(const int64_t id, Error **errp);
void pc_acpi_init(const char *default_dsdt);
void pc_guest_info_init(PCMachineState *pcms);
#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
#define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
#define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
#define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
MemoryRegion *pci_address_space);
void xen_load_linux(PCMachineState *pcms);
void pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
MemoryRegion *rom_memory,
MemoryRegion **ram_memory);
uint64_t pc_pci_hole64_start(void);
qemu_irq pc_allocate_cpu_irq(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
ISADevice **rtc_state,
bool create_fdctrl,
bool no_vmport,
bool has_pit,
uint32_t hpet_irqs);
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
void pc_cmos_init(PCMachineState *pcms,
BusState *ide0, BusState *ide1,
ISADevice *s);
void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
void pc_pci_device_init(PCIBus *pci_bus);
typedef void (*cpu_set_smm_t)(int smm, void *arg);
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
ISADevice *pc_find_fdc0(void);
int cmos_get_fd_drive_type(FloppyDriveType fd0);
#define FW_CFG_IO_BASE 0x510
#define PORT92_A20_LINE "a20"
/* acpi_piix.c */
I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm);
/* hpet.c */
extern int no_hpet;
/* piix_pci.c */
struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;
#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
#define TYPE_I440FX_PCI_DEVICE "i440FX"
#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
/*
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
*/
#define RCR_IOPORT 0xcf9
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state, int *piix_devfn,
ISABus **isa_bus, qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
ram_addr_t below_4g_mem_size,
ram_addr_t above_4g_mem_size,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);
PCIBus *find_i440fx(void);
/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
/* pc_sysfw.c */
void pc_system_firmware_init(MemoryRegion *rom_memory,
bool isapc_ram_fw);
/* acpi-build.c */
void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
const CPUArchIdList *apic_ids, GArray *entry);
/* e820 types */
#define E820_RAM 1
#define E820_RESERVED 2
#define E820_ACPI 3
#define E820_NVS 4
#define E820_UNUSABLE 5
int e820_add_entry(uint64_t, uint64_t, uint32_t);
int e820_get_num_entries(void);
bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
#define PC_COMPAT_3_1 \
HW_COMPAT_3_1 \
{\
.driver = "intel-iommu",\
.property = "dma-drain",\
.value = "off",\
},
#define PC_COMPAT_3_0 \
HW_COMPAT_3_0 \
{\
.driver = TYPE_X86_CPU,\
.property = "x-hv-synic-kvm-only",\
.value = "on",\
},{\
.driver = "Skylake-Server" "-" TYPE_X86_CPU,\
.property = "pku",\
.value = "off",\
},{\
.driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,\
.property = "pku",\
.value = "off",\
},
#define PC_COMPAT_2_12 \
HW_COMPAT_2_12 \
{\
.driver = TYPE_X86_CPU,\
.property = "legacy-cache",\
.value = "on",\
},{\
.driver = TYPE_X86_CPU,\
.property = "topoext",\
.value = "off",\
},{\
.driver = "EPYC-" TYPE_X86_CPU,\
.property = "xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "EPYC-IBPB-" TYPE_X86_CPU,\
.property = "xlevel",\
.value = stringify(0x8000000a),\
},
#define PC_COMPAT_2_11 \
HW_COMPAT_2_11 \
{\
.driver = TYPE_X86_CPU,\
.property = "x-migrate-smi-count",\
.value = "off",\
},{\
.driver = "Skylake-Server" "-" TYPE_X86_CPU,\
.property = "clflushopt",\
.value = "off",\
},
#define PC_COMPAT_2_10 \
HW_COMPAT_2_10 \
{\
.driver = TYPE_X86_CPU,\
.property = "x-hv-max-vps",\
.value = "0x40",\
},{\
.driver = "i440FX-pcihost",\
.property = "x-pci-hole64-fix",\
.value = "off",\
},{\
.driver = "q35-pcihost",\
.property = "x-pci-hole64-fix",\
.value = "off",\
},
#define PC_COMPAT_2_9 \
HW_COMPAT_2_9 \
q35/mch: implement extended TSEG sizes The q35 machine type currently lets the guest firmware select a 1MB, 2MB or 8MB TSEG (basically, SMRAM) size. In edk2/OVMF, we use 8MB, but even that is not enough when a lot of VCPUs (more than approx. 224) are configured -- SMRAM footprint scales largely proportionally with VCPU count. Introduce a new property for "mch" called "extended-tseg-mbytes", which expresses (in megabytes) the user's choice of TSEG (SMRAM) size. Invent a new, QEMU-specific register in the config space of the DRAM Controller, at offset 0x50, in order to allow guest firmware to query the TSEG (SMRAM) size. According to Intel Document Number 316966-002, Table 5-1 "DRAM Controller Register Address Map (D0:F0)": Warning: Address locations that are not listed are considered Intel Reserved registers locations. Reads to Reserved registers may return non-zero values. Writes to reserved locations may cause system failures. All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in this component are simply not included in this document. The reserved/unimplemented space in the PCI configuration header space is not documented as such in this summary. Offsets 0x50 and 0x51 are not listed in Table 5-1. They are also not part of the standard PCI config space header. And they precede the capability list as well, which starts at 0xe0 for this device. When the guest writes value 0xffff to this register, the value that can be read back is that of "mch.extended-tseg-mbytes" -- unless it remains 0xffff. The guest is required to write 0xffff first (as opposed to a read-only register) because PCI config space is generally not cleared on QEMU reset, and after S3 resume or reboot, new guest firmware running on old QEMU could read a guest OS-injected value from this register. After reading the available "extended" TSEG size, the guest firmware may actually request that TSEG size by writing pattern 11b to the ESMRAMC register's TSEG_SZ bit-field. (The Intel spec referenced above defines only patterns 00b (1MB), 01b (2MB) and 10b (8MB); 11b is reserved.) On the QEMU command line, the value can be set with -global mch.extended-tseg-mbytes=N The default value for 2.10+ q35 machine types is 16. The value is limited to 0xfff (4095) at the moment, purely so that the product (4095 MB) can be stored to the uint32_t variable "tseg_size" in mch_update_smram(). Users are responsible for choosing sensible TSEG sizes. On 2.9 and earlier q35 machine types, the default value is 0. This lets the 11b bit pattern in ESMRAMC.TSEG_SZ, and the register at offset 0x50, keep their original behavior. When "extended-tseg-mbytes" is nonzero, the new register at offset 0x50 is set to that value on reset, for completeness. PCI config space is migrated automatically, so no VMSD changes are necessary. Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1447027 Ref: https://lists.01.org/pipermail/edk2-devel/2017-May/010456.html Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-06-08 19:10:13 +03:00
{\
.driver = "mch",\
.property = "extended-tseg-mbytes",\
.value = stringify(0),\
},\
target-i386: present virtual L3 cache info for vcpus Some software algorithms are based on the hardware's cache info, for example, for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger a resched IPI and told cpu2 to do the wakeup if they don't share low level cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc. The relevant linux-kernel code as bellow: static void ttwu_queue(struct task_struct *p, int cpu) { struct rq *rq = cpu_rq(cpu); ...... if (... && !cpus_share_cache(smp_processor_id(), cpu)) { ...... ttwu_queue_remote(p, cpu); /* will trigger RES IPI */ return; } ...... ttwu_do_activate(rq, p, 0); /* access target's rq directly */ ...... } In real hardware, the cpus on the same socket share L3 cache, so one won't trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs under some workloads even if the virtual cpus belongs to the same virtual socket. For KVM, there will be lots of vmexit due to guest send IPIs. The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates) and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during the period: No-L3 With-L3(applied this patch) cpu0: 363890 44582 cpu1: 373405 43109 cpu2: 340783 43797 cpu3: 333854 43409 cpu4: 327170 40038 cpu5: 325491 39922 cpu6: 319129 42391 cpu7: 306480 41035 cpu8: 161139 32188 cpu9: 164649 31024 cpu10: 149823 30398 cpu11: 149823 32455 cpu12: 164830 35143 cpu13: 172269 35805 cpu14: 179979 33898 cpu15: 194505 32754 avg: 268963.6 40129.8 The VM's topology is "1*socket 8*cores 2*threads". After present virtual L3 cache info for VM, the amounts of RES IPIs in guest reduce 85%. For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause severe performance degradation. We had tested the overall system performance if vcpus actually run on sparate physical socket. With L3 cache, the performance improves 7.2%~33.1%(avg:15.7%). Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 08:21:13 +03:00
#define PC_COMPAT_2_8 \
HW_COMPAT_2_8 \
{\
.driver = TYPE_X86_CPU,\
.property = "tcg-cpuid",\
.value = "off",\
},\
{\
.driver = "kvmclock",\
.property = "x-mach-use-reliable-get-clock",\
.value = "off",\
},\
{\
.driver = "ICH9-LPC",\
.property = "x-smi-broadcast",\
.value = "off",\
},\
{\
.driver = TYPE_X86_CPU,\
.property = "vmware-cpuid-freq",\
.value = "off",\
},\
{\
.driver = "Haswell-" TYPE_X86_CPU,\
.property = "stepping",\
.value = "1",\
},
#define PC_COMPAT_2_7 \
HW_COMPAT_2_7 \
target-i386: present virtual L3 cache info for vcpus Some software algorithms are based on the hardware's cache info, for example, for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger a resched IPI and told cpu2 to do the wakeup if they don't share low level cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc. The relevant linux-kernel code as bellow: static void ttwu_queue(struct task_struct *p, int cpu) { struct rq *rq = cpu_rq(cpu); ...... if (... && !cpus_share_cache(smp_processor_id(), cpu)) { ...... ttwu_queue_remote(p, cpu); /* will trigger RES IPI */ return; } ...... ttwu_do_activate(rq, p, 0); /* access target's rq directly */ ...... } In real hardware, the cpus on the same socket share L3 cache, so one won't trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs under some workloads even if the virtual cpus belongs to the same virtual socket. For KVM, there will be lots of vmexit due to guest send IPIs. The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates) and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during the period: No-L3 With-L3(applied this patch) cpu0: 363890 44582 cpu1: 373405 43109 cpu2: 340783 43797 cpu3: 333854 43409 cpu4: 327170 40038 cpu5: 325491 39922 cpu6: 319129 42391 cpu7: 306480 41035 cpu8: 161139 32188 cpu9: 164649 31024 cpu10: 149823 30398 cpu11: 149823 32455 cpu12: 164830 35143 cpu13: 172269 35805 cpu14: 179979 33898 cpu15: 194505 32754 avg: 268963.6 40129.8 The VM's topology is "1*socket 8*cores 2*threads". After present virtual L3 cache info for VM, the amounts of RES IPIs in guest reduce 85%. For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause severe performance degradation. We had tested the overall system performance if vcpus actually run on sparate physical socket. With L3 cache, the performance improves 7.2%~33.1%(avg:15.7%). Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 08:21:13 +03:00
{\
.driver = TYPE_X86_CPU,\
.property = "l3-cache",\
.value = "off",\
},\
{\
.driver = TYPE_X86_CPU,\
.property = "full-cpuid-auto-level",\
.value = "off",\
},\
{\
.driver = "Opteron_G3" "-" TYPE_X86_CPU,\
.property = "family",\
.value = "15",\
},\
{\
.driver = "Opteron_G3" "-" TYPE_X86_CPU,\
.property = "model",\
.value = "6",\
},\
{\
.driver = "Opteron_G3" "-" TYPE_X86_CPU,\
.property = "stepping",\
.value = "1",\
},\
{\
.driver = "isa-pcspk",\
.property = "migrate",\
.value = "off",\
target-i386: present virtual L3 cache info for vcpus Some software algorithms are based on the hardware's cache info, for example, for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger a resched IPI and told cpu2 to do the wakeup if they don't share low level cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc. The relevant linux-kernel code as bellow: static void ttwu_queue(struct task_struct *p, int cpu) { struct rq *rq = cpu_rq(cpu); ...... if (... && !cpus_share_cache(smp_processor_id(), cpu)) { ...... ttwu_queue_remote(p, cpu); /* will trigger RES IPI */ return; } ...... ttwu_do_activate(rq, p, 0); /* access target's rq directly */ ...... } In real hardware, the cpus on the same socket share L3 cache, so one won't trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs under some workloads even if the virtual cpus belongs to the same virtual socket. For KVM, there will be lots of vmexit due to guest send IPIs. The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates) and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during the period: No-L3 With-L3(applied this patch) cpu0: 363890 44582 cpu1: 373405 43109 cpu2: 340783 43797 cpu3: 333854 43409 cpu4: 327170 40038 cpu5: 325491 39922 cpu6: 319129 42391 cpu7: 306480 41035 cpu8: 161139 32188 cpu9: 164649 31024 cpu10: 149823 30398 cpu11: 149823 32455 cpu12: 164830 35143 cpu13: 172269 35805 cpu14: 179979 33898 cpu15: 194505 32754 avg: 268963.6 40129.8 The VM's topology is "1*socket 8*cores 2*threads". After present virtual L3 cache info for VM, the amounts of RES IPIs in guest reduce 85%. For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause severe performance degradation. We had tested the overall system performance if vcpus actually run on sparate physical socket. With L3 cache, the performance improves 7.2%~33.1%(avg:15.7%). Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 08:21:13 +03:00
},
#define PC_COMPAT_2_6 \
HW_COMPAT_2_6 \
{\
.driver = TYPE_X86_CPU,\
.property = "cpuid-0xb",\
.value = "off",\
},{\
.driver = "vmxnet3",\
.property = "romfile",\
.value = "",\
},\
{\
.driver = TYPE_X86_CPU,\
.property = "fill-mtrr-mask",\
.value = "off",\
},\
{\
.driver = "apic-common",\
.property = "legacy-instance-id",\
.value = "on",\
},
#define PC_COMPAT_2_5 \
HW_COMPAT_2_5
/* Helper for setting model-id for CPU models that changed model-id
* depending on QEMU versions up to QEMU 2.4.
*/
#define PC_CPU_MODEL_IDS(v) \
{\
.driver = "qemu32-" TYPE_X86_CPU,\
.property = "model-id",\
.value = "QEMU Virtual CPU version " v,\
},\
{\
.driver = "qemu64-" TYPE_X86_CPU,\
.property = "model-id",\
.value = "QEMU Virtual CPU version " v,\
},\
{\
.driver = "athlon-" TYPE_X86_CPU,\
.property = "model-id",\
.value = "QEMU Virtual CPU version " v,\
},
#define PC_COMPAT_2_4 \
HW_COMPAT_2_4 \
PC_CPU_MODEL_IDS("2.4.0") \
{\
.driver = "Haswell-" TYPE_X86_CPU,\
.property = "abm",\
.value = "off",\
},\
{\
.driver = "Haswell-noTSX-" TYPE_X86_CPU,\
.property = "abm",\
.value = "off",\
},\
{\
.driver = "Broadwell-" TYPE_X86_CPU,\
.property = "abm",\
.value = "off",\
},\
{\
.driver = "Broadwell-noTSX-" TYPE_X86_CPU,\
.property = "abm",\
.value = "off",\
},\
{\
.driver = "host" "-" TYPE_X86_CPU,\
.property = "host-cache-info",\
.value = "on",\
},\
{\
.driver = TYPE_X86_CPU,\
.property = "check",\
.value = "off",\
},\
{\
.driver = "qemu64" "-" TYPE_X86_CPU,\
.property = "sse4a",\
.value = "on",\
},\
{\
.driver = "qemu64" "-" TYPE_X86_CPU,\
.property = "abm",\
.value = "on",\
},\
{\
.driver = "qemu64" "-" TYPE_X86_CPU,\
.property = "popcnt",\
.value = "on",\
},\
{\
.driver = "qemu32" "-" TYPE_X86_CPU,\
.property = "popcnt",\
.value = "on",\
},{\
.driver = "Opteron_G2" "-" TYPE_X86_CPU,\
.property = "rdtscp",\
.value = "on",\
},{\
.driver = "Opteron_G3" "-" TYPE_X86_CPU,\
.property = "rdtscp",\
.value = "on",\
},{\
.driver = "Opteron_G4" "-" TYPE_X86_CPU,\
.property = "rdtscp",\
.value = "on",\
},{\
.driver = "Opteron_G5" "-" TYPE_X86_CPU,\
.property = "rdtscp",\
.value = "on",\
},
#define PC_COMPAT_2_3 \
HW_COMPAT_2_3 \
PC_CPU_MODEL_IDS("2.3.0") \
{\
.driver = TYPE_X86_CPU,\
.property = "arat",\
.value = "off",\
},{\
.driver = "qemu64" "-" TYPE_X86_CPU,\
.property = "min-level",\
.value = stringify(4),\
},{\
.driver = "kvm64" "-" TYPE_X86_CPU,\
.property = "min-level",\
.value = stringify(5),\
},{\
.driver = "pentium3" "-" TYPE_X86_CPU,\
.property = "min-level",\
.value = stringify(2),\
},{\
.driver = "n270" "-" TYPE_X86_CPU,\
.property = "min-level",\
.value = stringify(5),\
},{\
.driver = "Conroe" "-" TYPE_X86_CPU,\
.property = "min-level",\
.value = stringify(4),\
},{\
.driver = "Penryn" "-" TYPE_X86_CPU,\
.property = "min-level",\
.value = stringify(4),\
},{\
.driver = "Nehalem" "-" TYPE_X86_CPU,\
.property = "min-level",\
.value = stringify(4),\
},{\
.driver = "n270" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Penryn" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Conroe" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Nehalem" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Westmere" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "SandyBridge" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "IvyBridge" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Haswell" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Haswell-noTSX" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Broadwell" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,\
.property = "min-xlevel",\
.value = stringify(0x8000000a),\
},{\
.driver = TYPE_X86_CPU,\
.property = "kvm-no-smi-migration",\
.value = "on",\
},
#define PC_COMPAT_2_2 \
HW_COMPAT_2_2 \
PC_CPU_MODEL_IDS("2.2.0") \
{\
.driver = "kvm64" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "kvm32" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Conroe" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Penryn" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Nehalem" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Westmere" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "SandyBridge" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Haswell" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Broadwell" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Opteron_G1" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Opteron_G2" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Opteron_G3" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Opteron_G4" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Opteron_G5" "-" TYPE_X86_CPU,\
.property = "vme",\
.value = "off",\
},\
{\
.driver = "Haswell" "-" TYPE_X86_CPU,\
.property = "f16c",\
.value = "off",\
},\
{\
.driver = "Haswell" "-" TYPE_X86_CPU,\
.property = "rdrand",\
.value = "off",\
},\
{\
.driver = "Broadwell" "-" TYPE_X86_CPU,\
.property = "f16c",\
.value = "off",\
},\
{\
.driver = "Broadwell" "-" TYPE_X86_CPU,\
.property = "rdrand",\
.value = "off",\
},
#define PC_COMPAT_2_1 \
HW_COMPAT_2_1 \
PC_CPU_MODEL_IDS("2.1.0") \
{\
.driver = "coreduo" "-" TYPE_X86_CPU,\
.property = "vmx",\
.value = "on",\
},\
{\
.driver = "core2duo" "-" TYPE_X86_CPU,\
.property = "vmx",\
.value = "on",\
},
#define PC_COMPAT_2_0 \
PC_CPU_MODEL_IDS("2.0.0") \
{\
.driver = "virtio-scsi-pci",\
.property = "any_layout",\
.value = "off",\
},{\
.driver = "PIIX4_PM",\
.property = "memory-hotplug-support",\
.value = "off",\
},\
{\
.driver = "apic",\
.property = "version",\
.value = stringify(0x11),\
},\
{\
.driver = "nec-usb-xhci",\
.property = "superspeed-ports-first",\
.value = "off",\
},\
{\
.driver = "nec-usb-xhci",\
.property = "force-pcie-endcap",\
.value = "on",\
},\
{\
.driver = "pci-serial",\
.property = "prog_if",\
.value = stringify(0),\
},\
{\
.driver = "pci-serial-2x",\
.property = "prog_if",\
.value = stringify(0),\
},\
{\
.driver = "pci-serial-4x",\
.property = "prog_if",\
.value = stringify(0),\
},\
{\
.driver = "virtio-net-pci",\
.property = "guest_announce",\
.value = "off",\
},\
{\
.driver = "ICH9-LPC",\
.property = "memory-hotplug-support",\
.value = "off",\
},{\
.driver = "xio3130-downstream",\
.property = COMPAT_PROP_PCP,\
.value = "off",\
},{\
.driver = "ioh3420",\
.property = COMPAT_PROP_PCP,\
.value = "off",\
},
#define PC_COMPAT_1_7 \
PC_CPU_MODEL_IDS("1.7.0") \
{\
.driver = TYPE_USB_DEVICE,\
.property = "msos-desc",\
.value = "no",\
},\
{\
.driver = "PIIX4_PM",\
.property = "acpi-pci-hotplug-with-bridge-support",\
.value = "off",\
},\
{\
.driver = "hpet",\
.property = HPET_INTCAP,\
.value = stringify(4),\
},
#define PC_COMPAT_1_6 \
PC_CPU_MODEL_IDS("1.6.0") \
{\
.driver = "e1000",\
.property = "mitigation",\
.value = "off",\
},{\
.driver = "qemu64-" TYPE_X86_CPU,\
.property = "model",\
.value = stringify(2),\
},{\
.driver = "qemu32-" TYPE_X86_CPU,\
.property = "model",\
.value = stringify(3),\
},{\
.driver = "i440FX-pcihost",\
.property = "short_root_bus",\
.value = stringify(1),\
},{\
.driver = "q35-pcihost",\
.property = "short_root_bus",\
.value = stringify(1),\
},
#define PC_COMPAT_1_5 \
PC_CPU_MODEL_IDS("1.5.0") \
{\
.driver = "Conroe-" TYPE_X86_CPU,\
.property = "model",\
.value = stringify(2),\
},{\
.driver = "Conroe-" TYPE_X86_CPU,\
.property = "min-level",\
.value = stringify(2),\
},{\
.driver = "Penryn-" TYPE_X86_CPU,\
.property = "model",\
.value = stringify(2),\
},{\
.driver = "Penryn-" TYPE_X86_CPU,\
.property = "min-level",\
.value = stringify(2),\
},{\
.driver = "Nehalem-" TYPE_X86_CPU,\
.property = "model",\
.value = stringify(2),\
},{\
.driver = "Nehalem-" TYPE_X86_CPU,\
.property = "min-level",\
.value = stringify(2),\
},{\
.driver = "virtio-net-pci",\
.property = "any_layout",\
.value = "off",\
},{\
.driver = TYPE_X86_CPU,\
.property = "pmu",\
.value = "on",\
},{\
.driver = "i440FX-pcihost",\
.property = "short_root_bus",\
.value = stringify(0),\
},{\
.driver = "q35-pcihost",\
.property = "short_root_bus",\
.value = stringify(0),\
},
#define PC_COMPAT_1_4 \
PC_CPU_MODEL_IDS("1.4.0") \
{\
.driver = "scsi-hd",\
.property = "discard_granularity",\
.value = stringify(0),\
},{\
.driver = "scsi-cd",\
.property = "discard_granularity",\
.value = stringify(0),\
},{\
.driver = "scsi-disk",\
.property = "discard_granularity",\
.value = stringify(0),\
},{\
.driver = "ide-hd",\
.property = "discard_granularity",\
.value = stringify(0),\
},{\
.driver = "ide-cd",\
.property = "discard_granularity",\
.value = stringify(0),\
},{\
.driver = "ide-drive",\
.property = "discard_granularity",\
.value = stringify(0),\
},{\
.driver = "virtio-blk-pci",\
.property = "discard_granularity",\
.value = stringify(0),\
},{\
.driver = "virtio-serial-pci",\
.property = "vectors",\
/* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
.value = stringify(0xFFFFFFFF),\
},{ \
.driver = "virtio-net-pci", \
.property = "ctrl_guest_offloads", \
.value = "off", \
},{\
.driver = "e1000",\
.property = "romfile",\
.value = "pxe-e1000.rom",\
},{\
.driver = "ne2k_pci",\
.property = "romfile",\
.value = "pxe-ne2k_pci.rom",\
},{\
.driver = "pcnet",\
.property = "romfile",\
.value = "pxe-pcnet.rom",\
},{\
.driver = "rtl8139",\
.property = "romfile",\
.value = "pxe-rtl8139.rom",\
},{\
.driver = "virtio-net-pci",\
.property = "romfile",\
.value = "pxe-virtio.rom",\
},{\
.driver = "486-" TYPE_X86_CPU,\
.property = "model",\
.value = stringify(0),\
},\
{\
.driver = "n270" "-" TYPE_X86_CPU,\
.property = "movbe",\
.value = "off",\
},\
{\
.driver = "Westmere" "-" TYPE_X86_CPU,\
.property = "pclmulqdq",\
.value = "off",\
},
#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
{ \
MachineClass *mc = MACHINE_CLASS(oc); \
optsfn(mc); \
mc->init = initfn; \
} \
static const TypeInfo pc_machine_type_##suffix = { \
.name = namestr TYPE_MACHINE_SUFFIX, \
.parent = TYPE_PC_MACHINE, \
.class_init = pc_machine_##suffix##_class_init, \
}; \
static void pc_machine_init_##suffix(void) \
{ \
type_register(&pc_machine_type_##suffix); \
} \
type_init(pc_machine_init_##suffix)
extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
#endif