256 lines
11 KiB
C
256 lines
11 KiB
C
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/*
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* QEMU monitor
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "cpu.h"
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#include "monitor/monitor.h"
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#include "monitor/hmp-target.h"
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#include "hmp.h"
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static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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unsigned int u;
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int i;
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u = 0;
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for (i = 0; i < 8; i++)
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u |= env->crf[i] << (32 - (4 * (i + 1)));
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return u;
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}
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static target_long monitor_get_msr (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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return env->msr;
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}
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static target_long monitor_get_xer (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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return env->xer;
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}
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static target_long monitor_get_decr (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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return cpu_ppc_load_decr(env);
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}
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static target_long monitor_get_tbu (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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return cpu_ppc_load_tbu(env);
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}
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static target_long monitor_get_tbl (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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return cpu_ppc_load_tbl(env);
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}
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void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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{
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CPUArchState *env1 = mon_get_cpu_env();
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dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
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}
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const MonitorDef monitor_defs[] = {
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/* General purpose registers */
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{ "r0", offsetof(CPUPPCState, gpr[0]) },
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{ "r1", offsetof(CPUPPCState, gpr[1]) },
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{ "r2", offsetof(CPUPPCState, gpr[2]) },
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{ "r3", offsetof(CPUPPCState, gpr[3]) },
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{ "r4", offsetof(CPUPPCState, gpr[4]) },
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{ "r5", offsetof(CPUPPCState, gpr[5]) },
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{ "r6", offsetof(CPUPPCState, gpr[6]) },
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{ "r7", offsetof(CPUPPCState, gpr[7]) },
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{ "r8", offsetof(CPUPPCState, gpr[8]) },
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{ "r9", offsetof(CPUPPCState, gpr[9]) },
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{ "r10", offsetof(CPUPPCState, gpr[10]) },
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{ "r11", offsetof(CPUPPCState, gpr[11]) },
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{ "r12", offsetof(CPUPPCState, gpr[12]) },
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{ "r13", offsetof(CPUPPCState, gpr[13]) },
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{ "r14", offsetof(CPUPPCState, gpr[14]) },
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{ "r15", offsetof(CPUPPCState, gpr[15]) },
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{ "r16", offsetof(CPUPPCState, gpr[16]) },
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{ "r17", offsetof(CPUPPCState, gpr[17]) },
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{ "r18", offsetof(CPUPPCState, gpr[18]) },
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{ "r19", offsetof(CPUPPCState, gpr[19]) },
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{ "r20", offsetof(CPUPPCState, gpr[20]) },
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{ "r21", offsetof(CPUPPCState, gpr[21]) },
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{ "r22", offsetof(CPUPPCState, gpr[22]) },
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{ "r23", offsetof(CPUPPCState, gpr[23]) },
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{ "r24", offsetof(CPUPPCState, gpr[24]) },
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{ "r25", offsetof(CPUPPCState, gpr[25]) },
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{ "r26", offsetof(CPUPPCState, gpr[26]) },
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{ "r27", offsetof(CPUPPCState, gpr[27]) },
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{ "r28", offsetof(CPUPPCState, gpr[28]) },
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{ "r29", offsetof(CPUPPCState, gpr[29]) },
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{ "r30", offsetof(CPUPPCState, gpr[30]) },
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{ "r31", offsetof(CPUPPCState, gpr[31]) },
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/* Floating point registers */
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{ "f0", offsetof(CPUPPCState, fpr[0]) },
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{ "f1", offsetof(CPUPPCState, fpr[1]) },
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{ "f2", offsetof(CPUPPCState, fpr[2]) },
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{ "f3", offsetof(CPUPPCState, fpr[3]) },
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{ "f4", offsetof(CPUPPCState, fpr[4]) },
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{ "f5", offsetof(CPUPPCState, fpr[5]) },
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{ "f6", offsetof(CPUPPCState, fpr[6]) },
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{ "f7", offsetof(CPUPPCState, fpr[7]) },
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{ "f8", offsetof(CPUPPCState, fpr[8]) },
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{ "f9", offsetof(CPUPPCState, fpr[9]) },
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{ "f10", offsetof(CPUPPCState, fpr[10]) },
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{ "f11", offsetof(CPUPPCState, fpr[11]) },
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{ "f12", offsetof(CPUPPCState, fpr[12]) },
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{ "f13", offsetof(CPUPPCState, fpr[13]) },
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{ "f14", offsetof(CPUPPCState, fpr[14]) },
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{ "f15", offsetof(CPUPPCState, fpr[15]) },
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{ "f16", offsetof(CPUPPCState, fpr[16]) },
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{ "f17", offsetof(CPUPPCState, fpr[17]) },
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{ "f18", offsetof(CPUPPCState, fpr[18]) },
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{ "f19", offsetof(CPUPPCState, fpr[19]) },
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{ "f20", offsetof(CPUPPCState, fpr[20]) },
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{ "f21", offsetof(CPUPPCState, fpr[21]) },
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{ "f22", offsetof(CPUPPCState, fpr[22]) },
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{ "f23", offsetof(CPUPPCState, fpr[23]) },
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{ "f24", offsetof(CPUPPCState, fpr[24]) },
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{ "f25", offsetof(CPUPPCState, fpr[25]) },
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{ "f26", offsetof(CPUPPCState, fpr[26]) },
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{ "f27", offsetof(CPUPPCState, fpr[27]) },
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{ "f28", offsetof(CPUPPCState, fpr[28]) },
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{ "f29", offsetof(CPUPPCState, fpr[29]) },
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{ "f30", offsetof(CPUPPCState, fpr[30]) },
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{ "f31", offsetof(CPUPPCState, fpr[31]) },
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{ "fpscr", offsetof(CPUPPCState, fpscr) },
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/* Next instruction pointer */
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{ "nip|pc", offsetof(CPUPPCState, nip) },
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{ "lr", offsetof(CPUPPCState, lr) },
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{ "ctr", offsetof(CPUPPCState, ctr) },
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{ "decr", 0, &monitor_get_decr, },
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{ "ccr", 0, &monitor_get_ccr, },
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/* Machine state register */
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{ "msr", 0, &monitor_get_msr, },
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{ "xer", 0, &monitor_get_xer, },
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{ "tbu", 0, &monitor_get_tbu, },
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{ "tbl", 0, &monitor_get_tbl, },
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/* Segment registers */
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{ "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
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{ "sr0", offsetof(CPUPPCState, sr[0]) },
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{ "sr1", offsetof(CPUPPCState, sr[1]) },
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{ "sr2", offsetof(CPUPPCState, sr[2]) },
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{ "sr3", offsetof(CPUPPCState, sr[3]) },
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{ "sr4", offsetof(CPUPPCState, sr[4]) },
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{ "sr5", offsetof(CPUPPCState, sr[5]) },
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{ "sr6", offsetof(CPUPPCState, sr[6]) },
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{ "sr7", offsetof(CPUPPCState, sr[7]) },
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{ "sr8", offsetof(CPUPPCState, sr[8]) },
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{ "sr9", offsetof(CPUPPCState, sr[9]) },
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{ "sr10", offsetof(CPUPPCState, sr[10]) },
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{ "sr11", offsetof(CPUPPCState, sr[11]) },
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{ "sr12", offsetof(CPUPPCState, sr[12]) },
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{ "sr13", offsetof(CPUPPCState, sr[13]) },
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{ "sr14", offsetof(CPUPPCState, sr[14]) },
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{ "sr15", offsetof(CPUPPCState, sr[15]) },
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/* Too lazy to put BATs... */
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{ "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
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{ "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
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{ "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
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{ "dar", offsetof(CPUPPCState, spr[SPR_DAR]) },
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{ "dsisr", offsetof(CPUPPCState, spr[SPR_DSISR]) },
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{ "cfar", offsetof(CPUPPCState, spr[SPR_CFAR]) },
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{ "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
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{ "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
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{ "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
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{ "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
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{ "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
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{ "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
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{ "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
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{ "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
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{ "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
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{ "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
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{ "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
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{ "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
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{ "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
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{ "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
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{ "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
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{ "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
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{ "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
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{ "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
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{ "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
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{ "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
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{ "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
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{ "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
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{ "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
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{ "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
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{ "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
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{ "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
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{ "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
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{ "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
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{ "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
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{ "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
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{ "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
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{ "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
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{ "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
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{ "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
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{ "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
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{ "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
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{ "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
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{ "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
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{ "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
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{ "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
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{ "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
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{ "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
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{ "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
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{ "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
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{ "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
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{ "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
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{ "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
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{ "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
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{ "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
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{ "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
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{ "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
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{ "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
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{ "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
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{ "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
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{ "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
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{ "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
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{ "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
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{ "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
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{ "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
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{ "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
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{ "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
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{ "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
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{ "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
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{ "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
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{ NULL },
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};
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const MonitorDef *target_monitor_defs(void)
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{
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return monitor_defs;
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}
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