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qemu/target/riscv/insn_trans/trans_rvzicbo.c.inc

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target/riscv: implement Zicboz extension The RISC-V base cache management operation (CBO) ISA extension has been ratified. It defines three extensions: Cache-Block Management, Cache-Block Prefetch and Cache-Block Zero. More information about the spec can be found at [1]. Let's start by implementing the Cache-Block Zero extension, Zicboz. It uses the cbo.zero instruction that, as with all CBO instructions that will be added later, needs to be implemented in an overlap group with the LQ instruction due to overlapping patterns. cbo.zero throws a Illegal Instruction/Virtual Instruction exception depending on CSR state. This is also the case for the remaining cbo instructions we're going to add next, so create a check_zicbo_envcfg() that will be used by all Zicbo[mz] instructions. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-24 16:25:34 +03:00
/*
* RISC-V translation routines for the RISC-V CBO Extension.
*
* Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
target/riscv: implement Zicbom extension Zicbom is the Cache-Block Management extension defined in the already ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1]. The extension contains three instructions: cbo.clean, cbo.flush and cbo.inval. All of them must be implemented in the same group as LQ and cbo.zero due to overlapping patterns. All these instructions can throw a Illegal Instruction/Virtual Instruction exception, similar to the existing cbo.zero. The same check_zicbo_envcfg() is used to handle these exceptions. Aside from that, these instructions also need to handle page faults and guest page faults. This is done in a new check_zicbom_access() helper. As with Zicboz, the cache block size for Zicbom is also configurable. Note that the spec determines that Zicbo[mp] and Zicboz can have different cache sizes (Section 2.7 of [1]), so we also include a 'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They are set to the same size, so unless users want to play around with the settings both sizes will be the same. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224132536.552293-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-24 16:25:35 +03:00
#define REQUIRE_ZICBOM(ctx) do { \
if (!ctx->cfg_ptr->ext_icbom) { \
return false; \
} \
} while (0)
target/riscv: implement Zicboz extension The RISC-V base cache management operation (CBO) ISA extension has been ratified. It defines three extensions: Cache-Block Management, Cache-Block Prefetch and Cache-Block Zero. More information about the spec can be found at [1]. Let's start by implementing the Cache-Block Zero extension, Zicboz. It uses the cbo.zero instruction that, as with all CBO instructions that will be added later, needs to be implemented in an overlap group with the LQ instruction due to overlapping patterns. cbo.zero throws a Illegal Instruction/Virtual Instruction exception depending on CSR state. This is also the case for the remaining cbo instructions we're going to add next, so create a check_zicbo_envcfg() that will be used by all Zicbo[mz] instructions. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-24 16:25:34 +03:00
#define REQUIRE_ZICBOZ(ctx) do { \
if (!ctx->cfg_ptr->ext_icboz) { \
return false; \
} \
} while (0)
target/riscv: implement Zicbom extension Zicbom is the Cache-Block Management extension defined in the already ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1]. The extension contains three instructions: cbo.clean, cbo.flush and cbo.inval. All of them must be implemented in the same group as LQ and cbo.zero due to overlapping patterns. All these instructions can throw a Illegal Instruction/Virtual Instruction exception, similar to the existing cbo.zero. The same check_zicbo_envcfg() is used to handle these exceptions. Aside from that, these instructions also need to handle page faults and guest page faults. This is done in a new check_zicbom_access() helper. As with Zicboz, the cache block size for Zicbom is also configurable. Note that the spec determines that Zicbo[mp] and Zicboz can have different cache sizes (Section 2.7 of [1]), so we also include a 'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They are set to the same size, so unless users want to play around with the settings both sizes will be the same. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224132536.552293-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-24 16:25:35 +03:00
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
{
REQUIRE_ZICBOM(ctx);
gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]);
return true;
}
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
{
REQUIRE_ZICBOM(ctx);
gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]);
return true;
}
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
{
REQUIRE_ZICBOM(ctx);
gen_helper_cbo_inval(cpu_env, cpu_gpr[a->rs1]);
return true;
}
target/riscv: implement Zicboz extension The RISC-V base cache management operation (CBO) ISA extension has been ratified. It defines three extensions: Cache-Block Management, Cache-Block Prefetch and Cache-Block Zero. More information about the spec can be found at [1]. Let's start by implementing the Cache-Block Zero extension, Zicboz. It uses the cbo.zero instruction that, as with all CBO instructions that will be added later, needs to be implemented in an overlap group with the LQ instruction due to overlapping patterns. cbo.zero throws a Illegal Instruction/Virtual Instruction exception depending on CSR state. This is also the case for the remaining cbo instructions we're going to add next, so create a check_zicbo_envcfg() that will be used by all Zicbo[mz] instructions. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-24 16:25:34 +03:00
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
{
REQUIRE_ZICBOZ(ctx);
gen_helper_cbo_zero(cpu_env, cpu_gpr[a->rs1]);
return true;
}
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