2003-08-11 01:35:13 +04:00
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/*
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* common defines for all CPUs
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2007-09-17 01:08:06 +04:00
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*
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2003-08-11 01:35:13 +04:00
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-17 00:47:01 +04:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2003-08-11 01:35:13 +04:00
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*/
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#ifndef CPU_DEFS_H
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#define CPU_DEFS_H
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2007-11-17 20:14:51 +03:00
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#ifndef NEED_CPU_H
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#error cpu.h included from common code
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#endif
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2003-08-11 01:35:13 +04:00
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#include "config.h"
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#include <setjmp.h>
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2004-02-17 01:17:43 +03:00
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#include <inttypes.h>
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2012-12-17 21:20:00 +04:00
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#include "qemu/osdep.h"
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#include "qemu/queue.h"
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2013-05-28 16:02:38 +04:00
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#ifndef CONFIG_USER_ONLY
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2012-12-17 21:19:49 +04:00
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#include "exec/hwaddr.h"
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2013-05-28 16:02:38 +04:00
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#endif
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2003-08-11 01:35:13 +04:00
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2004-01-24 18:26:06 +03:00
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#ifndef TARGET_LONG_BITS
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#error TARGET_LONG_BITS must be defined before including this header
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#endif
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#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
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2004-04-26 01:25:15 +04:00
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/* target_ulong is the type of a virtual address */
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2004-01-24 18:26:06 +03:00
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#if TARGET_LONG_SIZE == 4
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2013-04-17 18:26:41 +04:00
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typedef int32_t target_long;
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typedef uint32_t target_ulong;
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2005-01-04 02:35:10 +03:00
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#define TARGET_FMT_lx "%08x"
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2007-04-04 11:58:14 +04:00
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#define TARGET_FMT_ld "%d"
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2007-09-19 09:46:03 +04:00
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#define TARGET_FMT_lu "%u"
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2004-01-24 18:26:06 +03:00
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#elif TARGET_LONG_SIZE == 8
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2013-04-17 18:26:41 +04:00
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typedef int64_t target_long;
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typedef uint64_t target_ulong;
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2006-06-25 22:15:32 +04:00
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#define TARGET_FMT_lx "%016" PRIx64
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2007-04-04 11:58:14 +04:00
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#define TARGET_FMT_ld "%" PRId64
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2007-09-19 09:46:03 +04:00
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#define TARGET_FMT_lu "%" PRIu64
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2004-01-24 18:26:06 +03:00
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#else
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#error TARGET_LONG_SIZE undefined
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#endif
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2005-07-03 02:09:27 +04:00
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#define EXCP_INTERRUPT 0x10000 /* async interruption */
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#define EXCP_HLT 0x10001 /* hlt instruction reached */
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#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
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2005-11-24 00:02:53 +03:00
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#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
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2003-08-11 01:35:13 +04:00
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2005-11-20 13:32:34 +03:00
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#define TB_JMP_CACHE_BITS 12
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#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
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2006-11-12 23:40:55 +03:00
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/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
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addresses on the same page. The top bits are the same. This allows
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TLB invalidation to quickly clear a subset of the hash table. */
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#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
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#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
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#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
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#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
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2010-03-12 19:54:58 +03:00
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#if !defined(CONFIG_USER_ONLY)
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2005-11-29 00:19:04 +03:00
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#define CPU_TLB_BITS 8
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#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
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2003-08-11 01:35:13 +04:00
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2010-04-05 03:28:53 +04:00
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#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
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2008-01-31 12:22:27 +03:00
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#define CPU_TLB_ENTRY_BITS 4
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#else
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#define CPU_TLB_ENTRY_BITS 5
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#endif
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2003-08-11 01:35:13 +04:00
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typedef struct CPUTLBEntry {
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2008-06-09 04:20:13 +04:00
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/* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
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bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
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go directly to ram.
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2003-10-28 00:12:17 +03:00
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bit 3 : indicates that the entry is invalid
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bit 2..0 : zero
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*/
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2007-09-17 01:08:06 +04:00
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target_ulong addr_read;
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target_ulong addr_write;
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target_ulong addr_code;
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2010-04-05 03:28:53 +04:00
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/* Addend to virtual address to get host address. IO accesses
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2008-11-29 16:33:23 +03:00
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use the corresponding iotlb value. */
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2012-04-12 22:29:36 +04:00
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uintptr_t addend;
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2008-01-31 12:22:27 +03:00
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/* padding to get a power of two size */
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2012-04-12 22:29:36 +04:00
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uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
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(sizeof(target_ulong) * 3 +
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((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
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sizeof(uintptr_t))];
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2003-08-11 01:35:13 +04:00
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} CPUTLBEntry;
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2013-06-04 20:51:59 +04:00
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QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
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2010-04-05 03:28:53 +04:00
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2010-03-12 19:54:58 +03:00
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#define CPU_COMMON_TLB \
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/* The meaning of the MMU modes is defined in the target code. */ \
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CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
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2012-10-23 14:30:10 +04:00
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hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
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2010-03-17 05:14:28 +03:00
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target_ulong tlb_flush_addr; \
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target_ulong tlb_flush_mask;
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2010-03-12 19:54:58 +03:00
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#else
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#define CPU_COMMON_TLB
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#endif
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2009-07-27 18:13:06 +04:00
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#ifdef HOST_WORDS_BIGENDIAN
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2008-06-29 05:03:05 +04:00
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typedef struct icount_decr_u16 {
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uint16_t high;
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uint16_t low;
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} icount_decr_u16;
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#else
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typedef struct icount_decr_u16 {
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uint16_t low;
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uint16_t high;
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} icount_decr_u16;
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#endif
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2008-11-18 23:07:32 +03:00
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typedef struct CPUBreakpoint {
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target_ulong pc;
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int flags; /* BP_* */
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2009-09-12 11:36:22 +04:00
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QTAILQ_ENTRY(CPUBreakpoint) entry;
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2008-11-18 23:07:32 +03:00
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} CPUBreakpoint;
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typedef struct CPUWatchpoint {
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target_ulong vaddr;
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target_ulong len_mask;
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int flags; /* BP_* */
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2009-09-12 11:36:22 +04:00
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QTAILQ_ENTRY(CPUWatchpoint) entry;
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2008-11-18 23:07:32 +03:00
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} CPUWatchpoint;
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2008-04-08 23:29:54 +04:00
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#define CPU_TEMP_BUF_NLONGS 128
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2005-11-20 13:32:34 +03:00
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#define CPU_COMMON \
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/* soft mmu support */ \
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2008-06-29 05:03:05 +04:00
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/* in order to avoid passing too many arguments to the MMIO \
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helpers, we store some rarely used information in the CPU \
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2005-11-20 13:32:34 +03:00
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context) */ \
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2012-04-09 18:20:20 +04:00
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uintptr_t mem_io_pc; /* host pc at which the memory was \
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accessed */ \
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2008-06-29 05:03:05 +04:00
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target_ulong mem_io_vaddr; /* target virtual addr at which the \
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memory was accessed */ \
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2010-03-12 19:54:58 +03:00
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CPU_COMMON_TLB \
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2005-11-20 13:32:34 +03:00
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struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
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\
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2008-06-29 05:03:05 +04:00
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int64_t icount_extra; /* Instructions until next timer event. */ \
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/* Number of cycles left, with interrupt flag in high bit. \
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This allows a single read-compare-cbranch-write sequence to test \
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for both decrementer underflow and exceptions. */ \
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union { \
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uint32_t u32; \
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icount_decr_u16 u16; \
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} icount_decr; \
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uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
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\
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2005-11-20 13:32:34 +03:00
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/* from this point: preserved by CPU reset */ \
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/* ice debug support */ \
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2009-09-12 11:36:22 +04:00
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QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
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2005-11-20 13:32:34 +03:00
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\
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2009-09-12 11:36:22 +04:00
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QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
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2008-11-18 23:07:32 +03:00
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CPUWatchpoint *watchpoint_hit; \
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2008-10-11 21:55:29 +04:00
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\
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2008-05-29 14:08:06 +04:00
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/* Core interrupt code */ \
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2013-02-20 19:21:09 +04:00
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sigjmp_buf jmp_env; \
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2009-12-18 17:16:30 +03:00
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int exception_index; \
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2008-05-29 14:08:06 +04:00
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\
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2005-11-20 13:32:34 +03:00
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/* user data */ \
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2007-12-09 05:22:57 +03:00
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void *opaque; \
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\
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2012-12-01 09:18:14 +04:00
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const char *cpu_model_str;
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2005-11-20 13:32:34 +03:00
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2003-08-11 01:35:13 +04:00
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#endif
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