qemu/tcg/arm/tcg-target-con-str.h

/* SPDX-License-Identifier: MIT */
/*
 * Define Arm target-specific operand constraints.
 * Copyright (c) 2021 Linaro
 */

/*
 * Define constraint letters for register sets:
 * REGS(letter, register_mask)
 */
REGS('r', ALL_GENERAL_REGS)
REGS('l', ALL_QLOAD_REGS)
REGS('s', ALL_QSTORE_REGS)
REGS('w', ALL_VECTOR_REGS)

/*
 * Define constraint letters for constants:
 * CONST(letter, TCG_CT_CONST_* bit set)
 */
CONST('I', TCG_CT_CONST_ARM)
CONST('K', TCG_CT_CONST_INV)
CONST('N', TCG_CT_CONST_NEG)
CONST('O', TCG_CT_CONST_ORRI)
CONST('V', TCG_CT_CONST_ANDI)
CONST('Z', TCG_CT_CONST_ZERO)
tcg/arm: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-10-15 21:53:54 +03:00			`/* SPDX-License-Identifier: MIT */`
			`/*`
			`* Define Arm target-specific operand constraints.`
			`* Copyright (c) 2021 Linaro`
			`*/`

			`/*`
			`* Define constraint letters for register sets:`
			`* REGS(letter, register_mask)`
			`*/`
			`REGS('r', ALL_GENERAL_REGS)`
			`REGS('l', ALL_QLOAD_REGS)`
			`REGS('s', ALL_QSTORE_REGS)`
tcg/arm: Add host vector framework Add registers and function stubs. The functionality is disabled via use_neon_instructions defined to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2021-05-04 02:47:52 +03:00			`REGS('w', ALL_VECTOR_REGS)`
tcg/arm: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-10-15 21:53:54 +03:00
			`/*`
			`* Define constraint letters for constants:`
			`* CONST(letter, TCG_CT_CONST_* bit set)`
			`*/`
			`CONST('I', TCG_CT_CONST_ARM)`
			`CONST('K', TCG_CT_CONST_INV)`
			`CONST('N', TCG_CT_CONST_NEG)`
tcg/arm: Implement minimal vector operations Implementing dup2, add, sub, and, or, xor as the minimal set. This allows us to actually enable neon in the header file. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-09-06 01:54:33 +03:00			`CONST('O', TCG_CT_CONST_ORRI)`
			`CONST('V', TCG_CT_CONST_ANDI)`
tcg/arm: Split out target constraints to tcg-target-con-str.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-10-15 21:53:54 +03:00			`CONST('Z', TCG_CT_CONST_ZERO)`