2018-01-22 22:43:34 +03:00
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/*
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* QEMU model of Xilinx I/O Module Interrupt Controller
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*
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* Copyright (c) 2014 Xilinx Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2019-03-15 17:51:20 +03:00
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#ifndef HW_INTC_XLNX_PMU_IOMOD_INTC_H
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#define HW_INTC_XLNX_PMU_IOMOD_INTC_H
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2018-01-22 22:43:34 +03:00
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#define TYPE_XLNX_PMU_IO_INTC "xlnx.pmu_io_intc"
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#define XLNX_PMU_IO_INTC(obj) \
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OBJECT_CHECK(XlnxPMUIOIntc, (obj), TYPE_XLNX_PMU_IO_INTC)
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/* This is R_PIT3_CONTROL + 1 */
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#define XLNXPMUIOINTC_R_MAX (0x78 + 1)
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typedef struct XlnxPMUIOIntc {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq parent_irq;
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struct {
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uint32_t intr_size;
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uint32_t level_edge;
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uint32_t positive;
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} cfg;
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uint32_t irq_raw;
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uint32_t regs[XLNXPMUIOINTC_R_MAX];
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RegisterInfo regs_info[XLNXPMUIOINTC_R_MAX];
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} XlnxPMUIOIntc;
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2019-03-15 17:51:20 +03:00
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#endif /* HW_INTC_XLNX_PMU_IOMOD_INTC_H */
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