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qemu/tests/tcg/xtensa/vectors.S

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tests/tcg/xtensa: only generate defined exception handlers Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 11:48:26 +03:00
#include "core-isa.h"
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
.macro vector name
tests/tcg/xtensa: support configurations w/o vecbase Configurations w/o vecbase may have vectors not grouped together and not in fixed order. They may not always be grouped into single output sections by assigning next offset to dot, as it may sometimes move dot backwards and sometimes they may even belong to different memory region. Don't group vectors into single output section. Instead put each vector into its own section ant put it at its default virtual address. Reserve 4KBytes from the default vectors base and put rest of the code and data starting from there. Mark vectors sections as executable, otherwise their contents is discarded. There may be as little as 16 bytes reserved for some vectors, load handler address into a0 and use ret.n to jump there to make vector code fit into this 16 byte space. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:04:51 +03:00
.section .vector.\name, "ax"
.global vector_\name
vector_\name\():
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
j 1f
tests/tcg/xtensa: support configurations w/o vecbase Configurations w/o vecbase may have vectors not grouped together and not in fixed order. They may not always be grouped into single output sections by assigning next offset to dot, as it may sometimes move dot backwards and sometimes they may even belong to different memory region. Don't group vectors into single output section. Instead put each vector into its own section ant put it at its default virtual address. Reserve 4KBytes from the default vectors base and put rest of the code and data starting from there. Mark vectors sections as executable, otherwise their contents is discarded. There may be as little as 16 bytes reserved for some vectors, load handler address into a0 and use ret.n to jump there to make vector code fit into this 16 byte space. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:04:51 +03:00
.literal_position
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
1:
tests/tcg/xtensa: support configurations w/o vecbase Configurations w/o vecbase may have vectors not grouped together and not in fixed order. They may not always be grouped into single output sections by assigning next offset to dot, as it may sometimes move dot backwards and sometimes they may even belong to different memory region. Don't group vectors into single output section. Instead put each vector into its own section ant put it at its default virtual address. Reserve 4KBytes from the default vectors base and put rest of the code and data starting from there. Mark vectors sections as executable, otherwise their contents is discarded. There may be as little as 16 bytes reserved for some vectors, load handler address into a0 and use ret.n to jump there to make vector code fit into this 16 byte space. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:04:51 +03:00
wsr a0, excsave1
movi a0, 1f
ret.n
.section .vector.\name\().text, "ax"
.literal_position
1:
rsr a0, excsave1
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, excsave1
movi a2, handler_\name
l32i a2, a2, 0
beqz a2, 1f
jx a2
1:
movi a3, 1b
movi a2, 1
simcall
.align 4
.global handler_\name
handler_\name\(): .word 0
.endm
tests/tcg/xtensa: only generate defined exception handlers Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 11:48:26 +03:00
#if XCHAL_HAVE_WINDOWED
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
vector window_overflow_4
vector window_overflow_8
vector window_overflow_12
vector window_underflow_4
vector window_underflow_8
vector window_underflow_12
tests/tcg/xtensa: only generate defined exception handlers Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 11:48:26 +03:00
#endif
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
tests/tcg/xtensa: only generate defined exception handlers Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 11:48:26 +03:00
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
vector level2
tests/tcg/xtensa: only generate defined exception handlers Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 11:48:26 +03:00
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
vector level3
tests/tcg/xtensa: only generate defined exception handlers Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 11:48:26 +03:00
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
vector level4
tests/tcg/xtensa: only generate defined exception handlers Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 11:48:26 +03:00
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
vector level5
tests/tcg/xtensa: only generate defined exception handlers Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 11:48:26 +03:00
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
vector level6
tests/tcg/xtensa: only generate defined exception handlers Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 11:48:26 +03:00
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
vector level7
tests/tcg/xtensa: only generate defined exception handlers Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 11:48:26 +03:00
#endif
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
vector kernel
vector user
vector double
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