2017-01-19 01:01:41 +03:00
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/*
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* QEMU Nios II CPU
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*
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* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2017-01-19 01:01:41 +03:00
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#include "qapi/error.h"
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#include "cpu.h"
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#include "exec/log.h"
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#include "exec/gdbstub.h"
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#include "hw/qdev-properties.h"
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static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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env->regs[R_PC] = value;
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}
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static bool nios2_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
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}
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cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
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|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 13:05:11 +03:00
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static void nios2_cpu_reset(DeviceState *dev)
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2017-01-19 01:01:41 +03:00
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{
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cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
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|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 13:05:11 +03:00
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CPUState *cs = CPU(dev);
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2017-01-19 01:01:41 +03:00
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Nios2CPU *cpu = NIOS2_CPU(cs);
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Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu);
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CPUNios2State *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", cs->cpu_index);
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log_cpu_state(cs, 0);
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}
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cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
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|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 13:05:11 +03:00
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ncc->parent_reset(dev);
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2017-01-19 01:01:41 +03:00
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memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS);
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env->regs[R_PC] = cpu->reset_addr;
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#if defined(CONFIG_USER_ONLY)
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/* Start in user mode with interrupts enabled. */
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env->regs[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE;
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#else
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env->regs[CR_STATUS] = 0;
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#endif
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}
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2020-11-29 20:40:20 +03:00
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#ifndef CONFIG_USER_ONLY
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static void nios2_cpu_set_irq(void *opaque, int irq, int level)
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{
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Nios2CPU *cpu = opaque;
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CPUNios2State *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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2020-11-29 20:40:22 +03:00
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env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level);
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2020-11-29 20:40:20 +03:00
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env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE];
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if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
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env->irq_pending = 0;
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else if (!env->irq_pending) {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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#endif
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2017-01-19 01:01:41 +03:00
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static void nios2_cpu_initfn(Object *obj)
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{
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Nios2CPU *cpu = NIOS2_CPU(obj);
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2019-03-29 00:26:22 +03:00
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cpu_set_cpustate_pointers(cpu);
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2017-01-19 01:01:41 +03:00
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#if !defined(CONFIG_USER_ONLY)
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2019-03-29 00:26:22 +03:00
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mmu_init(&cpu->env);
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2020-11-29 20:40:20 +03:00
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/*
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* These interrupt lines model the IIC (internal interrupt
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* controller). QEMU does not currently support the EIC
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* (external interrupt controller) -- if we did it would be
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* a separate device in hw/intc with a custom interface to
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* the CPU, and boards using it would not wire up these IRQ lines.
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*/
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qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32);
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2017-01-19 01:01:41 +03:00
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#endif
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}
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2017-08-24 19:31:36 +03:00
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static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
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2017-01-19 01:01:41 +03:00
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{
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2017-08-24 19:31:36 +03:00
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return object_class_by_name(TYPE_NIOS2_CPU);
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2017-01-19 01:01:41 +03:00
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}
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static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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ncc->parent_realize(dev, errp);
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}
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2021-09-11 19:54:25 +03:00
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#ifndef CONFIG_USER_ONLY
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2017-01-19 01:01:41 +03:00
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static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->regs[CR_STATUS] & CR_STATUS_PIE)) {
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cs->exception_index = EXCP_IRQ;
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nios2_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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2021-09-11 19:54:25 +03:00
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#endif /* !CONFIG_USER_ONLY */
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2017-01-19 01:01:41 +03:00
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static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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/* NOTE: NiosII R2 is not supported yet. */
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info->mach = bfd_arch_nios2;
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#ifdef TARGET_WORDS_BIGENDIAN
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info->print_insn = print_insn_big_nios2;
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#else
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info->print_insn = print_insn_little_nios2;
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#endif
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}
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2020-03-16 20:21:41 +03:00
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static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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2017-01-19 01:01:41 +03:00
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUNios2State *env = &cpu->env;
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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if (n < 32) { /* GP regs */
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return gdb_get_reg32(mem_buf, env->regs[n]);
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} else if (n == 32) { /* PC */
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return gdb_get_reg32(mem_buf, env->regs[R_PC]);
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} else if (n < 49) { /* Status regs */
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return gdb_get_reg32(mem_buf, env->regs[n - 1]);
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}
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/* Invalid regs */
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return 0;
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}
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static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUNios2State *env = &cpu->env;
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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if (n < 32) { /* GP regs */
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env->regs[n] = ldl_p(mem_buf);
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} else if (n == 32) { /* PC */
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env->regs[R_PC] = ldl_p(mem_buf);
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} else if (n < 49) { /* Status regs */
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env->regs[n - 1] = ldl_p(mem_buf);
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}
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return 4;
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}
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static Property nios2_properties[] = {
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DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true),
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/* ALTR,pid-num-bits */
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DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8),
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/* ALTR,tlb-num-ways */
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DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16),
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/* ALTR,tlb-num-entries */
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DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256),
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DEFINE_PROP_END_OF_LIST(),
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};
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2021-05-17 13:51:31 +03:00
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#ifndef CONFIG_USER_ONLY
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#include "hw/core/sysemu-cpu-ops.h"
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static const struct SysemuCPUOps nios2_sysemu_ops = {
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2021-05-17 13:51:37 +03:00
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.get_phys_page_debug = nios2_cpu_get_phys_page_debug,
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2021-05-17 13:51:31 +03:00
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};
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#endif
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2021-02-04 19:39:23 +03:00
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#include "hw/core/tcg-cpu-ops.h"
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2021-02-28 02:21:17 +03:00
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static const struct TCGCPUOps nios2_tcg_ops = {
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2021-02-04 19:39:23 +03:00
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.initialize = nios2_tcg_init,
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.tlb_fill = nios2_cpu_tlb_fill,
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#ifndef CONFIG_USER_ONLY
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2021-09-11 19:54:25 +03:00
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.cpu_exec_interrupt = nios2_cpu_exec_interrupt,
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2021-02-04 19:39:23 +03:00
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.do_interrupt = nios2_cpu_do_interrupt,
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.do_unaligned_access = nios2_cpu_do_unaligned_access,
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#endif /* !CONFIG_USER_ONLY */
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};
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2017-01-19 01:01:41 +03:00
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static void nios2_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
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2018-01-14 05:04:12 +03:00
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device_class_set_parent_realize(dc, nios2_cpu_realizefn,
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&ncc->parent_realize);
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2020-01-10 18:30:32 +03:00
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device_class_set_props(dc, nios2_properties);
|
cpu: Use DeviceClass reset instead of a special CPUClass reset
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.
This change should not cause CPU objects to be reset more often
than they are at the moment, because:
* nobody is directly calling device_cold_reset() or
qdev_reset_all() on CPU objects
* no CPU object is on a qbus, so they will not be reset either
by somebody calling qbus_reset_all()/bus_cold_reset(), or
by the main "reset sysbus and everything in the qbus tree"
reset that most devices are reset by
Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.
All the changes to the files under target/ were made using the
included Coccinelle script, except:
(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c
(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:
| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
| S390CPU *cpu = S390_CPU(s);
| S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
| CPUS390XState *env = &cpu->env;
|+ DeviceState *dev = DEVICE(s);
|
|- scc->parent_reset(s);
|+ scc->parent_reset(dev);
| cpu->env.sigp_order = 0;
| s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-03-03 13:05:11 +03:00
|
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device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset);
|
2017-01-19 01:01:41 +03:00
|
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2017-08-24 19:31:36 +03:00
|
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cc->class_by_name = nios2_cpu_class_by_name;
|
2017-01-19 01:01:41 +03:00
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cc->has_work = nios2_cpu_has_work;
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cc->dump_state = nios2_cpu_dump_state;
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cc->set_pc = nios2_cpu_set_pc;
|
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cc->disas_set_info = nios2_cpu_disas_set_info;
|
2019-04-02 12:47:37 +03:00
|
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#ifndef CONFIG_USER_ONLY
|
2021-05-17 13:51:31 +03:00
|
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cc->sysemu_ops = &nios2_sysemu_ops;
|
2017-01-19 01:01:41 +03:00
|
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#endif
|
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cc->gdb_read_register = nios2_cpu_gdb_read_register;
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cc->gdb_write_register = nios2_cpu_gdb_write_register;
|
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cc->gdb_num_core_regs = 49;
|
2021-02-04 19:39:23 +03:00
|
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cc->tcg_ops = &nios2_tcg_ops;
|
2017-01-19 01:01:41 +03:00
|
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}
|
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static const TypeInfo nios2_cpu_type_info = {
|
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|
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.name = TYPE_NIOS2_CPU,
|
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|
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.parent = TYPE_CPU,
|
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.instance_size = sizeof(Nios2CPU),
|
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.instance_init = nios2_cpu_initfn,
|
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|
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.class_size = sizeof(Nios2CPUClass),
|
|
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.class_init = nios2_cpu_class_init,
|
|
|
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};
|
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static void nios2_cpu_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&nios2_cpu_type_info);
|
|
|
|
}
|
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|
|
|
|
type_init(nios2_cpu_register_types)
|