2022-06-24 11:49:11 +03:00
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/*
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* QEMU PowerPC PowerNV Proxy PHB model
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*
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* Copyright (c) 2022, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/visitor.h"
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#include "qapi/error.h"
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#include "hw/pci-host/pnv_phb.h"
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#include "hw/pci-host/pnv_phb3.h"
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#include "hw/pci-host/pnv_phb4.h"
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#include "hw/ppc/pnv.h"
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#include "hw/qdev-properties.h"
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#include "qom/object.h"
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2022-08-11 19:39:45 +03:00
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#include "sysemu/sysemu.h"
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2022-06-24 11:49:11 +03:00
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2022-08-11 19:39:43 +03:00
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/*
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2022-08-19 12:47:47 +03:00
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* Set the QOM parent and parent bus of an object child. If the device
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* state associated with the child has an id, use it as QOM id.
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* Otherwise use object_typename[index] as QOM id.
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*
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* This helper does both operations at the same time because seting
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* a new QOM child will erase the bus parent of the device. This happens
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* because object_unparent() will call object_property_del_child(),
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* which in turn calls the property release callback prop->release if
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* it's defined. In our case this callback is set to
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* object_finalize_child_property(), which was assigned during the
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* first object_property_add_child() call. This callback will end up
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* calling device_unparent(), and this function removes the device
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* from its parent bus.
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*
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* The QOM and parent bus to be set aren´t necessarily related, so
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* let's receive both as arguments.
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2022-08-11 19:39:43 +03:00
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*/
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2022-08-19 12:47:47 +03:00
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static bool pnv_parent_fixup(Object *parent, BusState *parent_bus,
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Object *child, int index,
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Error **errp)
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2022-08-11 19:39:43 +03:00
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{
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g_autofree char *default_id =
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g_strdup_printf("%s[%d]", object_get_typename(child), index);
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const char *dev_id = DEVICE(child)->id;
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if (child->parent == parent) {
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2022-08-19 12:47:47 +03:00
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return true;
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2022-08-11 19:39:43 +03:00
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}
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object_ref(child);
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object_unparent(child);
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object_property_add_child(parent, dev_id ? dev_id : default_id, child);
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object_unref(child);
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2022-08-19 12:47:47 +03:00
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if (!qdev_set_parent_bus(DEVICE(child), parent_bus, errp)) {
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return false;
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2022-08-11 19:39:43 +03:00
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}
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2022-08-19 12:47:47 +03:00
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return true;
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2022-08-11 19:39:43 +03:00
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}
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/*
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* User created devices won't have the initial setup that default
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* devices have. This setup consists of assigning a parent device
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* (chip for PHB3, PEC for PHB4/5) that will be the QOM/bus parent
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* of the PHB.
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*/
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static bool pnv_phb_user_device_init(PnvPHB *phb, Error **errp)
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{
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PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
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PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
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Object *parent = NULL;
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if (!chip) {
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error_setg(errp, "invalid chip id: %d", phb->chip_id);
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return false;
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}
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parent = pnv_chip_add_phb(chip, phb, errp);
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if (!parent) {
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return false;
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}
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/*
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* Reparent user created devices to the chip to build
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* correctly the device tree. pnv_xscom_dt() needs every
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* PHB to be a child of the chip to build the DT correctly.
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*/
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2022-08-19 12:47:47 +03:00
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if (!pnv_parent_fixup(parent, qdev_get_parent_bus(DEVICE(chip)),
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OBJECT(phb), phb->phb_id, errp)) {
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return false;
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}
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2022-08-11 19:39:43 +03:00
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return true;
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}
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2022-06-24 11:49:11 +03:00
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static void pnv_phb_realize(DeviceState *dev, Error **errp)
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{
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PnvPHB *phb = PNV_PHB(dev);
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PCIHostState *pci = PCI_HOST_BRIDGE(dev);
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g_autofree char *phb_typename = NULL;
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if (!phb->version) {
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error_setg(errp, "version not specified");
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return;
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}
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switch (phb->version) {
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case 3:
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phb_typename = g_strdup(TYPE_PNV_PHB3);
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break;
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case 4:
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phb_typename = g_strdup(TYPE_PNV_PHB4);
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break;
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case 5:
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phb_typename = g_strdup(TYPE_PNV_PHB5);
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break;
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default:
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g_assert_not_reached();
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}
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phb->backend = object_new(phb_typename);
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object_property_add_child(OBJECT(dev), "phb-backend", phb->backend);
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/* Passthrough child device properties to the proxy device */
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object_property_set_uint(phb->backend, "index", phb->phb_id, errp);
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object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp);
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object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp);
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2022-08-11 19:39:43 +03:00
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/*
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* Handle user created devices. User devices will not have a
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* pointer to a chip (PHB3) and a PEC (PHB4/5).
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*/
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if (!phb->chip && !phb->pec) {
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if (!pnv_phb_user_device_init(phb, errp)) {
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return;
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}
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}
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2022-06-24 11:49:11 +03:00
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if (phb->version == 3) {
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object_property_set_link(phb->backend, "chip",
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OBJECT(phb->chip), errp);
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} else {
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object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp);
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}
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if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) {
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return;
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}
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if (phb->version == 3) {
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pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend));
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2022-06-24 11:49:13 +03:00
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} else {
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pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend));
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2022-06-24 11:49:11 +03:00
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}
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2022-08-19 12:47:48 +03:00
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if (defaults_enabled()) {
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PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT);
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2022-08-11 19:39:45 +03:00
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2022-08-19 12:47:48 +03:00
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pci_realize_and_unref(root, pci->bus, errp);
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}
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2022-06-24 11:49:11 +03:00
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}
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static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
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PCIBus *rootbus)
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{
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PnvPHB *phb = PNV_PHB(host_bridge);
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snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
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phb->chip_id, phb->phb_id);
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return phb->bus_path;
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}
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static Property pnv_phb_properties[] = {
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DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0),
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DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0),
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DEFINE_PROP_UINT32("version", PnvPHB, version, 0),
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DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *),
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DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC,
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PnvPhb4PecState *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pnv_phb_class_init(ObjectClass *klass, void *data)
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{
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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hc->root_bus_path = pnv_phb_root_bus_path;
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dc->realize = pnv_phb_realize;
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device_class_set_props(dc, pnv_phb_properties);
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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2022-08-11 19:39:45 +03:00
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dc->user_creatable = true;
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2022-06-24 11:49:11 +03:00
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}
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2022-11-25 14:52:37 +03:00
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static void pnv_phb_root_port_reset_hold(Object *obj)
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2022-06-24 11:49:11 +03:00
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{
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2022-11-25 14:52:37 +03:00
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
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PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj);
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PCIDevice *d = PCI_DEVICE(obj);
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2022-06-24 11:49:15 +03:00
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uint8_t *conf = d->config;
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2022-06-24 11:49:11 +03:00
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2022-11-25 14:52:37 +03:00
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if (rpc->parent_phases.hold) {
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rpc->parent_phases.hold(obj);
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}
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2022-06-24 11:49:15 +03:00
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if (phb_rp->version == 3) {
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return;
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}
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/* PHB4 and later requires these extra reset steps */
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pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
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PCI_IO_RANGE_MASK & 0xff);
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pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
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PCI_IO_RANGE_MASK & 0xff);
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pci_set_word(conf + PCI_MEMORY_BASE, 0);
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pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0);
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pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1);
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pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
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pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
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pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
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pci_config_set_interrupt_pin(conf, 0);
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}
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static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp)
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{
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
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PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
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2022-08-11 19:39:42 +03:00
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PCIBus *bus = PCI_BUS(qdev_get_parent_bus(dev));
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2022-06-24 11:49:15 +03:00
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PCIDevice *pci = PCI_DEVICE(dev);
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uint16_t device_id = 0;
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Error *local_err = NULL;
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2022-08-11 19:39:42 +03:00
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int chip_id, index;
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2022-08-19 12:47:48 +03:00
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/*
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* 'index' will be used both as a PCIE slot value and to calculate
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* QOM id. 'chip_id' is going to be used as PCIE chassis for the
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* root port.
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*/
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2022-11-09 15:22:10 +03:00
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chip_id = object_property_get_int(OBJECT(bus), "chip-id", &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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index = object_property_get_int(OBJECT(bus), "phb-id", &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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2022-08-11 19:39:42 +03:00
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/* Set unique chassis/slot values for the root port */
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qdev_prop_set_uint8(dev, "chassis", chip_id);
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qdev_prop_set_uint16(dev, "slot", index);
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2022-06-24 11:49:15 +03:00
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2022-08-19 12:47:48 +03:00
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/*
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* User created root ports are QOM parented to one of
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* the peripheral containers but it's already at the right
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* parent bus. Change the QOM parent to be the same as the
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* parent bus it's already assigned to.
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*/
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if (!pnv_parent_fixup(OBJECT(bus), BUS(bus), OBJECT(dev),
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index, errp)) {
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return;
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}
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2022-06-24 11:49:15 +03:00
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rpc->parent_realize(dev, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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switch (phb_rp->version) {
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case 3:
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device_id = PNV_PHB3_DEVICE_ID;
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break;
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case 4:
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device_id = PNV_PHB4_DEVICE_ID;
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break;
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case 5:
|
|
|
|
|
device_id = PNV_PHB5_DEVICE_ID;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
g_assert_not_reached();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
pci_config_set_device_id(pci->config, device_id);
|
|
|
|
|
pci_config_set_interrupt_pin(pci->config, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static Property pnv_phb_root_port_properties[] = {
|
|
|
|
|
DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0),
|
|
|
|
|
|
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
|
|
|
|
|
{
|
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2022-11-25 14:52:37 +03:00
|
|
|
|
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
2022-06-24 11:49:15 +03:00
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
|
|
|
|
|
|
|
|
|
|
dc->desc = "IBM PHB PCIE Root Port";
|
|
|
|
|
|
|
|
|
|
device_class_set_props(dc, pnv_phb_root_port_properties);
|
|
|
|
|
device_class_set_parent_realize(dc, pnv_phb_root_port_realize,
|
|
|
|
|
&rpc->parent_realize);
|
2022-11-25 14:52:37 +03:00
|
|
|
|
resettable_class_set_parent_phases(rc, NULL, pnv_phb_root_port_reset_hold,
|
|
|
|
|
NULL, &rpc->parent_phases);
|
2022-08-11 19:39:45 +03:00
|
|
|
|
dc->user_creatable = true;
|
2022-06-24 11:49:15 +03:00
|
|
|
|
|
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_IBM;
|
|
|
|
|
/* device_id will be written during realize() */
|
|
|
|
|
k->device_id = 0;
|
|
|
|
|
k->revision = 0;
|
|
|
|
|
|
|
|
|
|
rpc->exp_offset = 0x48;
|
|
|
|
|
rpc->aer_offset = 0x100;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const TypeInfo pnv_phb_type_info = {
|
|
|
|
|
.name = TYPE_PNV_PHB,
|
|
|
|
|
.parent = TYPE_PCIE_HOST_BRIDGE,
|
|
|
|
|
.instance_size = sizeof(PnvPHB),
|
|
|
|
|
.class_init = pnv_phb_class_init,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const TypeInfo pnv_phb_root_port_info = {
|
|
|
|
|
.name = TYPE_PNV_PHB_ROOT_PORT,
|
|
|
|
|
.parent = TYPE_PCIE_ROOT_PORT,
|
|
|
|
|
.instance_size = sizeof(PnvPHBRootPort),
|
|
|
|
|
.class_init = pnv_phb_root_port_class_init,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void pnv_phb_register_types(void)
|
|
|
|
|
{
|
2022-06-24 11:49:11 +03:00
|
|
|
|
type_register_static(&pnv_phb_type_info);
|
2022-06-24 11:49:15 +03:00
|
|
|
|
type_register_static(&pnv_phb_root_port_info);
|
2022-06-24 11:49:11 +03:00
|
|
|
|
}
|
2022-06-24 11:49:15 +03:00
|
|
|
|
|
|
|
|
|
type_init(pnv_phb_register_types)
|