59 lines
2.3 KiB
C
59 lines
2.3 KiB
C
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/*
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* Copyright (c) 2020, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "qemu-common.h"
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#include "qemu/host-utils.h"
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#include "core-dsp3400/core-isa.h"
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#include "core-dsp3400/core-matmap.h"
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#include "overlay_tool.h"
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#define xtensa_modules xtensa_modules_dsp3400
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#include "core-dsp3400/xtensa-modules.c.inc"
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static XtensaConfig dsp3400 __attribute__((unused)) = {
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.name = "dsp3400",
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.gdb_regmap = {
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.reg = {
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#include "core-dsp3400/gdb-config.c.inc"
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}
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},
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.isa_internal = &xtensa_modules,
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.clock_freq_khz = 40000,
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.opcode_translators = (const XtensaOpcodeTranslators *[]){
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&xtensa_core_opcodes,
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&xtensa_fpu2000_opcodes,
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NULL,
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},
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DEFAULT_SECTIONS
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};
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REGISTER_CORE(dsp3400)
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