54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
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/*
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* Nuvoton Peripheral SPI Module
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*
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* Copyright 2023 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM_PSPI_H
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#define NPCM_PSPI_H
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#include "hw/ssi/ssi.h"
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#include "hw/sysbus.h"
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/*
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* Number of registers in our device state structure. Don't change this without
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* incrementing the version_id in the vmstate.
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*/
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#define NPCM_PSPI_NR_REGS 3
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/**
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* NPCMPSPIState - Device state for one Flash Interface Unit.
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* @parent: System bus device.
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* @mmio: Memory region for register access.
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* @spi: The SPI bus mastered by this controller.
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* @regs: Register contents.
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* @irq: The interrupt request queue for this module.
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*
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* Each PSPI has a shared bank of registers, and controls up to four chip
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* selects. Each chip select has a dedicated memory region which may be used to
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* read and write the flash connected to that chip select as if it were memory.
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*/
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typedef struct NPCMPSPIState {
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SysBusDevice parent;
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MemoryRegion mmio;
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SSIBus *spi;
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uint16_t regs[NPCM_PSPI_NR_REGS];
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qemu_irq irq;
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} NPCMPSPIState;
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#define TYPE_NPCM_PSPI "npcm-pspi"
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OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
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#endif /* NPCM_PSPI_H */
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