qemu/configs/targets/riscv64-linux-user.mak

TARGET_ARCH=riscv64
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
TARGET_SYSTBL_ABI=64
TARGET_SYSTBL_ABI=common,64,riscv,rlimit,memfd_secret
TARGET_SYSTBL=syscall.tbl
default-configs: use TARGET_ARCH key Replace the individual TARGET_*=y lines with TARGET_ARCH, similar to how TARGET_BASE_ARCH is handled already. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2020-09-21 12:11:01 +03:00			`TARGET_ARCH=riscv64`
configure: remove target configuration The config-target.mak files are small constant, we can therefore just write them down explicitly. This removes a pretty large part of the configure script, including the whole logic to detect which accelerators are supported by each target. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2020-09-21 11:37:49 +03:00			`TARGET_BASE_ARCH=riscv`
			`TARGET_ABI_DIR=riscv`
target/riscv: Remove built-in GDB XML files for CSRs Now that we have switched to generate the RISC-V CSR XML dynamically, remove the built-in hardcoded XML files. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210116054123.5457-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com> 2021-01-16 08:41:23 +03:00			`TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml`
semihosting: Split out guestfd.c In arm-compat-semi.c, we have more advanced treatment of guest file descriptors than we do in other implementations. Split out GuestFD and related functions to a new file so that they can be shared. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-04-28 07:38:02 +03:00			`CONFIG_SEMIHOSTING=y`
riscv: Add semihosting support Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org> 2021-01-09 01:42:52 +03:00			`CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y`
linux-user,riscv: move to syscalltbl file Since kernel v6.11 riscv has moved from syscall_nr.h file to syscall.tbl (3db80c999deb ("riscv: convert to generic syscall table")) Update linux-user scripts to be able to retrieve syscall numbers from linux syscall.tbl instead of syscall_nr.h. New syscall.tbl is imported from linux v6.11 using updated scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240920151034.859533-4-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2024-09-20 18:10:31 +03:00			`TARGET_SYSTBL_ABI=64`
			`TARGET_SYSTBL_ABI=common,64,riscv,rlimit,memfd_secret`
			`TARGET_SYSTBL=syscall.tbl`