2009-05-19 19:17:58 +04:00
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#ifndef CPU_COMMON_H
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2016-06-29 16:29:06 +03:00
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#define CPU_COMMON_H
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2009-05-19 19:17:58 +04:00
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2011-11-22 14:06:26 +04:00
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/* CPU interfaces that are target independent. */
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2009-05-19 19:17:58 +04:00
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2013-05-28 16:02:38 +04:00
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#ifndef CONFIG_USER_ONLY
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2012-12-17 21:19:49 +04:00
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#include "exec/hwaddr.h"
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2013-05-28 16:02:38 +04:00
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#endif
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2010-04-01 21:57:10 +04:00
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2012-12-17 21:20:00 +04:00
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#include "qemu/bswap.h"
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#include "qemu/queue.h"
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2012-12-16 05:17:02 +04:00
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2017-08-05 06:46:31 +03:00
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/* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
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2016-08-28 04:45:14 +03:00
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void qemu_init_cpu_list(void);
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void cpu_list_lock(void);
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void cpu_list_unlock(void);
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2017-06-26 08:22:55 +03:00
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void tcg_flush_softmmu_tlb(CPUState *cs);
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2010-03-12 19:54:58 +03:00
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#if !defined(CONFIG_USER_ONLY)
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2010-12-08 14:05:36 +03:00
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enum device_endian {
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DEVICE_NATIVE_ENDIAN,
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DEVICE_BIG_ENDIAN,
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DEVICE_LITTLE_ENDIAN,
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};
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2017-02-27 07:52:44 +03:00
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#if defined(HOST_WORDS_BIGENDIAN)
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#define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
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#else
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#define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
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#endif
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2009-05-19 19:17:58 +04:00
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/* address in the RAM (different from a physical address) */
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2012-10-04 14:36:04 +04:00
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#if defined(CONFIG_XEN_BACKEND)
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2011-07-20 12:17:42 +04:00
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typedef uint64_t ram_addr_t;
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# define RAM_ADDR_MAX UINT64_MAX
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# define RAM_ADDR_FMT "%" PRIx64
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#else
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2012-03-03 02:30:02 +04:00
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typedef uintptr_t ram_addr_t;
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# define RAM_ADDR_MAX UINTPTR_MAX
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# define RAM_ADDR_FMT "%" PRIxPTR
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2011-07-20 12:17:42 +04:00
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#endif
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2009-05-19 19:17:58 +04:00
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2014-05-14 13:43:05 +04:00
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extern ram_addr_t ram_size;
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2009-05-19 19:17:58 +04:00
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/* memory API */
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2012-10-23 14:30:10 +04:00
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typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
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typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
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2009-05-19 19:17:58 +04:00
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2011-03-02 10:56:19 +03:00
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void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
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2009-05-19 19:17:58 +04:00
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/* This should not be used by devices. */
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2016-03-25 14:55:08 +03:00
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ram_addr_t qemu_ram_addr_from_host(void *ptr);
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2015-11-05 21:10:33 +03:00
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RAMBlock *qemu_ram_block_by_name(const char *name);
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2015-11-05 21:10:32 +03:00
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RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
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2016-05-26 11:07:50 +03:00
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ram_addr_t *offset);
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2018-03-12 20:20:57 +03:00
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ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
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2016-05-10 05:04:59 +03:00
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void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
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void qemu_ram_unset_idstr(RAMBlock *block);
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2015-11-05 21:10:32 +03:00
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const char *qemu_ram_get_idstr(RAMBlock *rb);
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2019-02-15 20:45:44 +03:00
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void *qemu_ram_get_host_addr(RAMBlock *rb);
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ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
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ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
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2017-03-07 21:36:36 +03:00
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bool qemu_ram_is_shared(RAMBlock *rb);
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2018-03-12 20:20:58 +03:00
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bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
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void qemu_ram_set_uf_zeroable(RAMBlock *rb);
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2018-05-14 09:57:00 +03:00
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bool qemu_ram_is_migratable(RAMBlock *rb);
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void qemu_ram_set_migratable(RAMBlock *rb);
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void qemu_ram_unset_migratable(RAMBlock *rb);
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2018-03-12 20:20:58 +03:00
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2016-09-29 22:09:37 +03:00
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size_t qemu_ram_pagesize(RAMBlock *block);
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2017-02-24 21:28:34 +03:00
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size_t qemu_ram_pagesize_largest(void);
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2009-05-19 19:17:58 +04:00
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2012-10-23 14:30:10 +04:00
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void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
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2019-01-17 15:49:01 +03:00
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hwaddr len, int is_write);
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2012-10-23 14:30:10 +04:00
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static inline void cpu_physical_memory_read(hwaddr addr,
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2019-01-17 15:49:01 +03:00
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void *buf, hwaddr len)
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2009-05-19 19:17:58 +04:00
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{
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cpu_physical_memory_rw(addr, buf, len, 0);
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}
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2012-10-23 14:30:10 +04:00
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static inline void cpu_physical_memory_write(hwaddr addr,
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2019-01-17 15:49:01 +03:00
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const void *buf, hwaddr len)
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2009-05-19 19:17:58 +04:00
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{
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2011-04-10 19:28:56 +04:00
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cpu_physical_memory_rw(addr, (void *)buf, len, 1);
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2009-05-19 19:17:58 +04:00
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}
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2012-10-23 14:30:10 +04:00
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void *cpu_physical_memory_map(hwaddr addr,
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hwaddr *plen,
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2009-05-19 19:17:58 +04:00
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int is_write);
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2012-10-23 14:30:10 +04:00
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void cpu_physical_memory_unmap(void *buffer, hwaddr len,
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int is_write, hwaddr access_len);
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2015-03-16 12:03:37 +03:00
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void cpu_register_map_client(QEMUBH *bh);
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void cpu_unregister_map_client(QEMUBH *bh);
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2009-05-19 19:17:58 +04:00
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2012-10-23 14:30:10 +04:00
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bool cpu_physical_memory_is_io(hwaddr phys_addr);
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2012-05-07 08:04:18 +04:00
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2010-03-21 22:47:13 +03:00
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/* Coalesced MMIO regions are areas where write operations can be reordered.
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* This usually implies that write operations are side-effect free. This allows
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* batching which can make a major impact on performance when using
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* virtualization.
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*/
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void qemu_flush_coalesced_mmio_buffer(void);
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2019-01-17 15:49:01 +03:00
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void cpu_flush_icache_range(hwaddr start, hwaddr len);
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2009-05-19 19:17:58 +04:00
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2012-01-02 02:32:15 +04:00
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extern struct MemoryRegion io_mem_rom;
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extern struct MemoryRegion io_mem_notdirty;
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2009-05-19 19:17:58 +04:00
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2019-02-15 20:45:44 +03:00
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typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
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2013-06-26 05:35:34 +04:00
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2015-05-21 15:24:13 +03:00
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int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
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2017-02-24 21:28:32 +03:00
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int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
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2013-06-26 05:35:34 +04:00
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2010-03-12 19:54:58 +03:00
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#endif
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2016-06-29 16:29:06 +03:00
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#endif /* CPU_COMMON_H */
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