2011-08-26 01:38:59 +04:00
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/*
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* QEMU Alpha DP264/CLIPPER hardware system emulator.
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*
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* Choose CLIPPER IRQ mappings over, say, DP264, MONET, or WEBBRICK
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2011-11-29 12:52:39 +04:00
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* variants because CLIPPER doesn't have an SMC669 SuperIO controller
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2011-08-26 01:38:59 +04:00
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* that we need to emulate as well.
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*/
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2016-01-26 21:17:04 +03:00
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#include "qemu/osdep.h"
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2016-01-19 23:51:44 +03:00
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#include "cpu.h"
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2011-08-26 01:38:59 +04:00
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#include "elf.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/loader.h"
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2013-03-18 20:36:02 +04:00
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#include "alpha_sys.h"
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2015-12-17 19:35:09 +03:00
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#include "qemu/error-report.h"
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2019-10-04 02:03:53 +03:00
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#include "hw/rtc/mc146818rtc.h"
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2020-03-07 12:13:12 +03:00
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#include "hw/ide/pci.h"
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2018-03-09 01:39:45 +03:00
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#include "hw/isa/superio.h"
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2019-12-12 19:15:43 +03:00
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#include "net/net.h"
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2016-03-20 20:16:19 +03:00
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#include "qemu/cutils.h"
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2020-10-28 14:36:57 +03:00
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#include "qemu/datadir.h"
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2011-08-26 01:38:59 +04:00
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static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint64_t addr)
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{
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if (((addr >> 41) & 3) == 2) {
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addr &= 0xffffffffffull;
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}
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return addr;
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}
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/* Note that there are at least 3 viewpoints of IRQ numbers on Alpha systems.
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(0) The dev_irq_n lines into the cpu, which we totally ignore,
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(1) The DRIR lines in the typhoon chipset,
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(2) The "vector" aka mangled interrupt number reported by SRM PALcode,
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(3) The interrupt number assigned by the kernel.
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The following function is concerned with (1) only. */
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static int clipper_pci_map_irq(PCIDevice *d, int irq_num)
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{
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int slot = d->devfn >> 3;
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assert(irq_num >= 0 && irq_num <= 3);
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return (slot + 1) * 4 + irq_num;
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}
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2014-05-07 18:42:57 +04:00
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static void clipper_init(MachineState *machine)
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2011-08-26 01:38:59 +04:00
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{
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2014-05-07 18:42:57 +04:00
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ram_addr_t ram_size = machine->ram_size;
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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2012-10-16 04:45:53 +04:00
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AlphaCPU *cpus[4];
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2011-08-26 01:38:59 +04:00
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PCIBus *pci_bus;
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2020-03-17 18:05:37 +03:00
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PCIDevice *pci_dev;
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2021-06-16 17:15:38 +03:00
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DeviceState *i82378_dev;
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2011-12-16 01:09:51 +04:00
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ISABus *isa_bus;
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2011-08-26 01:38:59 +04:00
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qemu_irq rtc_irq;
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2021-06-16 17:15:38 +03:00
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qemu_irq isa_irq;
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2011-08-26 01:38:59 +04:00
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long size, i;
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2015-05-28 15:39:42 +03:00
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char *palcode_filename;
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2020-07-05 20:22:11 +03:00
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uint64_t palcode_entry;
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uint64_t kernel_entry, kernel_low;
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2019-05-18 23:54:27 +03:00
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unsigned int smp_cpus = machine->smp.cpus;
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2011-08-26 01:38:59 +04:00
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/* Create up to 4 cpus. */
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memset(cpus, 0, sizeof(cpus));
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for (i = 0; i < smp_cpus; ++i) {
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2017-10-05 16:50:39 +03:00
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cpus[i] = ALPHA_CPU(cpu_create(machine->cpu_type));
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2011-08-26 01:38:59 +04:00
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}
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2021-06-14 00:15:49 +03:00
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/*
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* arg0 -> memory size
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* arg1 -> kernel entry point
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* arg2 -> config word
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*
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* Config word: bits 0-5 -> ncpus
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* bit 6 -> nographics option (for HWRPB CTB)
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*
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* See init_hwrpb() in the PALcode.
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*/
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2012-10-16 04:45:53 +04:00
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cpus[0]->env.trap_arg0 = ram_size;
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cpus[0]->env.trap_arg1 = 0;
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2021-06-14 00:15:49 +03:00
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cpus[0]->env.trap_arg2 = smp_cpus | (!machine->enable_graphics << 6);
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2011-08-26 01:38:59 +04:00
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2021-06-14 00:15:47 +03:00
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/*
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* Init the chipset. Because we're using CLIPPER IRQ mappings,
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* the minimum PCI device IdSel is 1.
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*/
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2021-06-16 17:15:38 +03:00
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pci_bus = typhoon_init(machine->ram, &isa_irq, &rtc_irq, cpus,
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2021-06-14 00:15:47 +03:00
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clipper_pci_map_irq, PCI_DEVFN(1, 0));
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2011-08-26 01:38:59 +04:00
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2021-06-16 17:15:38 +03:00
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/*
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* Init the PCI -> ISA bridge.
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*
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* Technically, PCI-based Alphas shipped with one of three different
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* PCI-ISA bridges:
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*
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* - Intel i82378 SIO
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* - Cypress CY82c693UB
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* - ALI M1533
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*
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* (An Intel i82375 PCI-EISA bridge was also used on some models.)
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*
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* For simplicity, we model an i82378 here, even though it wouldn't
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* have been on any Tsunami/Typhoon systems; it's close enough, and
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* we don't want to deal with modelling the CY82c693UB (which has
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* incompatible edge/level control registers, plus other peripherals
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* like IDE and USB) or the M1533 (which also has IDE and USB).
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*
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* Importantly, we need to provide a PCI device node for it, otherwise
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* some operating systems won't notice there's an ISA bus to configure.
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*/
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i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(7, 0), "i82378"));
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isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
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/* Connect the ISA PIC to the Typhoon IRQ used for ISA interrupts. */
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qdev_connect_gpio_out(i82378_dev, 0, isa_irq);
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2013-07-14 04:23:37 +04:00
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/* Since we have an SRM-compatible PALcode, use the SRM epoch. */
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2017-10-17 19:44:16 +03:00
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mc146818_rtc_init(isa_bus, 1900, rtc_irq);
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2013-07-14 04:23:37 +04:00
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2011-08-26 01:38:59 +04:00
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/* VGA setup. Don't bother loading the bios. */
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2012-09-08 14:16:28 +04:00
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pci_vga_init(pci_bus);
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2011-08-26 01:38:59 +04:00
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/* Network setup. e1000 is good enough, failing Tulip support. */
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for (i = 0; i < nb_nics; i++) {
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2013-06-06 12:48:51 +04:00
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pci_nic_init_nofail(&nd_table[i], pci_bus, "e1000", NULL);
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2011-08-26 01:38:59 +04:00
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}
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2018-03-09 01:39:45 +03:00
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/* Super I/O */
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isa_create_simple(isa_bus, TYPE_SMC37C669_SUPERIO);
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2011-08-26 01:38:59 +04:00
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/* IDE disk setup. */
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2020-03-17 18:05:37 +03:00
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pci_dev = pci_create_simple(pci_bus, -1, "cmd646-ide");
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pci_ide_create_devs(pci_dev);
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2011-08-26 01:38:59 +04:00
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/* Load PALcode. Given that this is not "real" cpu palcode,
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but one explicitly written for the emulation, we might as
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well load it directly from and ELF image. */
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2015-05-28 15:39:42 +03:00
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palcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
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2020-10-26 17:30:14 +03:00
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machine->firmware ?: "palcode-clipper");
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2011-08-26 01:38:59 +04:00
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if (palcode_filename == NULL) {
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2015-12-17 19:35:09 +03:00
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error_report("no palcode provided");
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2011-08-26 01:38:59 +04:00
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exit(1);
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}
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2019-01-15 15:18:03 +03:00
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size = load_elf(palcode_filename, NULL, cpu_alpha_superpage_to_phys,
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2020-07-05 20:22:11 +03:00
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NULL, &palcode_entry, NULL, NULL, NULL,
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2016-03-04 14:30:21 +03:00
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0, EM_ALPHA, 0, 0);
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2011-08-26 01:38:59 +04:00
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if (size < 0) {
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2015-12-17 19:35:09 +03:00
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error_report("could not load palcode '%s'", palcode_filename);
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2011-08-26 01:38:59 +04:00
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exit(1);
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}
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2015-05-28 15:39:42 +03:00
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g_free(palcode_filename);
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2011-08-26 01:38:59 +04:00
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/* Start all cpus at the PALcode RESET entry point. */
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for (i = 0; i < smp_cpus; ++i) {
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2012-10-16 04:45:53 +04:00
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cpus[i]->env.pc = palcode_entry;
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cpus[i]->env.palbr = palcode_entry;
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2011-08-26 01:38:59 +04:00
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}
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/* Load a kernel. */
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if (kernel_filename) {
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uint64_t param_offset;
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2019-01-15 15:18:03 +03:00
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size = load_elf(kernel_filename, NULL, cpu_alpha_superpage_to_phys,
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2020-07-05 20:22:11 +03:00
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NULL, &kernel_entry, &kernel_low, NULL, NULL,
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2016-03-04 14:30:21 +03:00
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0, EM_ALPHA, 0, 0);
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2011-08-26 01:38:59 +04:00
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if (size < 0) {
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2015-12-17 19:35:09 +03:00
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error_report("could not load kernel '%s'", kernel_filename);
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2011-08-26 01:38:59 +04:00
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exit(1);
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}
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2012-10-16 04:45:53 +04:00
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cpus[0]->env.trap_arg1 = kernel_entry;
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2011-08-26 01:38:59 +04:00
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param_offset = kernel_low - 0x6000;
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if (kernel_cmdline) {
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pstrcpy_targphys("cmdline", param_offset, 0x100, kernel_cmdline);
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}
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if (initrd_filename) {
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2018-09-13 13:07:13 +03:00
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long initrd_base;
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int64_t initrd_size;
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2011-08-26 01:38:59 +04:00
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initrd_size = get_image_size(initrd_filename);
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if (initrd_size < 0) {
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2015-12-17 19:35:09 +03:00
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error_report("could not load initial ram disk '%s'",
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initrd_filename);
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2011-08-26 01:38:59 +04:00
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exit(1);
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}
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/* Put the initrd image as high in memory as possible. */
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initrd_base = (ram_size - initrd_size) & TARGET_PAGE_MASK;
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load_image_targphys(initrd_filename, initrd_base,
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ram_size - initrd_base);
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Switch non-CPU callers from ld/st*_phys to address_space_ld/st*
Switch all the uses of ld/st*_phys to address_space_ld/st*,
except for those cases where the address space is the CPU's
(ie cs->as). This was done with the following script which
generates a Coccinelle patch.
A few over-80-columns lines in the result were rewrapped by
hand where Coccinelle failed to do the wrapping automatically,
as well as one location where it didn't put a line-continuation
'\' when wrapping lines on a change made to a match inside
a macro definition.
===begin===
#!/bin/sh -e
# Usage:
# ./ldst-phys.spatch.sh > ldst-phys.spatch
# spatch -sp_file ldst-phys.spatch -dir . | sed -e '/^+/s/\t/ /g' > out.patch
# patch -p1 < out.patch
for FN in ub uw_le uw_be l_le l_be q_le q_be uw l q; do
cat <<EOF
@ cpu_matches_ld_${FN} @
expression E1,E2;
identifier as;
@@
ld${FN}_phys(E1->as,E2)
@ other_matches_ld_${FN} depends on !cpu_matches_ld_${FN} @
expression E1,E2;
@@
-ld${FN}_phys(E1,E2)
+address_space_ld${FN}(E1,E2, MEMTXATTRS_UNSPECIFIED, NULL)
EOF
done
for FN in b w_le w_be l_le l_be q_le q_be w l q; do
cat <<EOF
@ cpu_matches_st_${FN} @
expression E1,E2,E3;
identifier as;
@@
st${FN}_phys(E1->as,E2,E3)
@ other_matches_st_${FN} depends on !cpu_matches_st_${FN} @
expression E1,E2,E3;
@@
-st${FN}_phys(E1,E2,E3)
+address_space_st${FN}(E1,E2,E3, MEMTXATTRS_UNSPECIFIED, NULL)
EOF
done
===endit===
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2015-04-26 18:49:24 +03:00
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address_space_stq(&address_space_memory, param_offset + 0x100,
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initrd_base + 0xfffffc0000000000ULL,
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MEMTXATTRS_UNSPECIFIED,
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NULL);
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address_space_stq(&address_space_memory, param_offset + 0x108,
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initrd_size, MEMTXATTRS_UNSPECIFIED, NULL);
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2011-08-26 01:38:59 +04:00
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}
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}
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}
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2015-09-04 21:37:08 +03:00
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static void clipper_machine_init(MachineClass *mc)
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2011-08-26 01:38:59 +04:00
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{
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2015-09-04 21:37:08 +03:00
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mc->desc = "Alpha DP264/CLIPPER";
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mc->init = clipper_init;
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2017-02-15 13:05:40 +03:00
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mc->block_default_type = IF_IDE;
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2015-09-04 21:37:08 +03:00
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mc->max_cpus = 4;
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2020-02-07 19:19:47 +03:00
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mc->is_default = true;
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2017-10-05 16:50:39 +03:00
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mc->default_cpu_type = ALPHA_CPU_TYPE_NAME("ev67");
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2020-02-19 19:08:42 +03:00
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mc->default_ram_id = "ram";
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2011-08-26 01:38:59 +04:00
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}
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2015-09-04 21:37:08 +03:00
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DEFINE_MACHINE("clipper", clipper_machine_init)
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