2011-02-18 01:45:10 +03:00
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/*
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* QEMU model of the LatticeMico32 timer block.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* http://www.latticesemi.com/documents/mico32timer.pdf
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "trace.h"
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2012-12-17 21:20:00 +04:00
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#include "qemu/timer.h"
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2012-01-13 20:07:19 +04:00
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#include "ptimer.h"
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2012-12-17 21:20:00 +04:00
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#include "qemu/error-report.h"
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2011-02-18 01:45:10 +03:00
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#define DEFAULT_FREQUENCY (50*1000000)
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enum {
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R_SR = 0,
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R_CR,
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R_PERIOD,
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R_SNAPSHOT,
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R_MAX
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};
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enum {
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SR_TO = (1 << 0),
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SR_RUN = (1 << 1),
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};
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enum {
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CR_ITO = (1 << 0),
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CR_CONT = (1 << 1),
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CR_START = (1 << 2),
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CR_STOP = (1 << 3),
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};
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struct LM32TimerState {
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SysBusDevice busdev;
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2011-11-20 13:44:25 +04:00
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MemoryRegion iomem;
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2011-02-18 01:45:10 +03:00
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QEMUBH *bh;
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ptimer_state *ptimer;
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qemu_irq irq;
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uint32_t freq_hz;
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uint32_t regs[R_MAX];
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};
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typedef struct LM32TimerState LM32TimerState;
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static void timer_update_irq(LM32TimerState *s)
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{
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int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO);
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trace_lm32_timer_irq_state(state);
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qemu_set_irq(s->irq, state);
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}
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2012-10-23 14:30:10 +04:00
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static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
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2011-02-18 01:45:10 +03:00
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{
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LM32TimerState *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_SR:
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case R_CR:
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case R_PERIOD:
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r = s->regs[addr];
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break;
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case R_SNAPSHOT:
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r = (uint32_t)ptimer_get_count(s->ptimer);
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break;
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default:
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2011-06-22 16:03:56 +04:00
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error_report("lm32_timer: read access to unknown register 0x"
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2011-02-18 01:45:10 +03:00
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_lm32_timer_memory_read(addr << 2, r);
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return r;
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}
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2012-10-23 14:30:10 +04:00
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static void timer_write(void *opaque, hwaddr addr,
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2011-11-20 13:44:25 +04:00
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uint64_t value, unsigned size)
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2011-02-18 01:45:10 +03:00
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{
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LM32TimerState *s = opaque;
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trace_lm32_timer_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_SR:
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s->regs[R_SR] &= ~SR_TO;
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break;
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case R_CR:
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s->regs[R_CR] = value;
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if (s->regs[R_CR] & CR_START) {
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ptimer_run(s->ptimer, 1);
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}
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if (s->regs[R_CR] & CR_STOP) {
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ptimer_stop(s->ptimer);
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}
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break;
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case R_PERIOD:
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s->regs[R_PERIOD] = value;
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ptimer_set_count(s->ptimer, value);
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break;
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case R_SNAPSHOT:
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error_report("lm32_timer: write access to read only register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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default:
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2011-06-22 16:03:56 +04:00
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error_report("lm32_timer: write access to unknown register 0x"
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2011-02-18 01:45:10 +03:00
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TARGET_FMT_plx, addr << 2);
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break;
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}
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timer_update_irq(s);
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}
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2011-11-20 13:44:25 +04:00
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static const MemoryRegionOps timer_ops = {
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.read = timer_read,
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.write = timer_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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2011-02-18 01:45:10 +03:00
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};
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static void timer_hit(void *opaque)
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{
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LM32TimerState *s = opaque;
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trace_lm32_timer_hit();
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s->regs[R_SR] |= SR_TO;
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if (s->regs[R_CR] & CR_CONT) {
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ptimer_set_count(s->ptimer, s->regs[R_PERIOD]);
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ptimer_run(s->ptimer, 1);
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}
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timer_update_irq(s);
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}
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static void timer_reset(DeviceState *d)
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{
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LM32TimerState *s = container_of(d, LM32TimerState, busdev.qdev);
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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ptimer_stop(s->ptimer);
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}
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static int lm32_timer_init(SysBusDevice *dev)
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{
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LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev);
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sysbus_init_irq(dev, &s->irq);
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s->bh = qemu_bh_new(timer_hit, s);
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s->ptimer = ptimer_init(s->bh);
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ptimer_set_freq(s->ptimer, s->freq_hz);
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2011-11-20 13:44:25 +04:00
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memory_region_init_io(&s->iomem, &timer_ops, s, "timer", R_MAX * 4);
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2011-11-27 13:38:10 +04:00
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sysbus_init_mmio(dev, &s->iomem);
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2011-02-18 01:45:10 +03:00
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return 0;
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}
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static const VMStateDescription vmstate_lm32_timer = {
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.name = "lm32-timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PTIMER(ptimer, LM32TimerState),
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VMSTATE_UINT32(freq_hz, LM32TimerState),
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VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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2012-01-24 23:12:29 +04:00
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static Property lm32_timer_properties[] = {
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DEFINE_PROP_UINT32("frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void lm32_timer_class_init(ObjectClass *klass, void *data)
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{
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2011-12-08 07:34:16 +04:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2012-01-24 23:12:29 +04:00
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = lm32_timer_init;
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2011-12-08 07:34:16 +04:00
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dc->reset = timer_reset;
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dc->vmsd = &vmstate_lm32_timer;
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dc->props = lm32_timer_properties;
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2012-01-24 23:12:29 +04:00
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}
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2013-01-10 19:19:07 +04:00
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static const TypeInfo lm32_timer_info = {
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2011-12-08 07:34:16 +04:00
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.name = "lm32-timer",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(LM32TimerState),
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.class_init = lm32_timer_class_init,
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2011-02-18 01:45:10 +03:00
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};
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2012-02-09 18:20:55 +04:00
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static void lm32_timer_register_types(void)
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2011-02-18 01:45:10 +03:00
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{
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2011-12-08 07:34:16 +04:00
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type_register_static(&lm32_timer_info);
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2011-02-18 01:45:10 +03:00
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}
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2012-02-09 18:20:55 +04:00
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type_init(lm32_timer_register_types)
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