2018-04-11 21:56:33 +03:00
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/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "cpu_loop-common.h"
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2018-04-11 21:56:50 +03:00
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static abi_ulong hppa_lws(CPUHPPAState *env)
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{
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2021-02-12 21:48:43 +03:00
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CPUState *cs = env_cpu(env);
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2018-04-11 21:56:50 +03:00
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uint32_t which = env->gr[20];
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abi_ulong addr = env->gr[26];
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abi_ulong old = env->gr[25];
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abi_ulong new = env->gr[24];
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abi_ulong size, ret;
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switch (which) {
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default:
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return -TARGET_ENOSYS;
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case 0: /* elf32 atomic 32bit cmpxchg */
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2021-02-12 21:48:47 +03:00
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if ((addr & 3) || !access_ok(cs, VERIFY_WRITE, addr, 4)) {
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2018-04-11 21:56:50 +03:00
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return -TARGET_EFAULT;
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}
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old = tswap32(old);
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new = tswap32(new);
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2021-02-12 21:48:43 +03:00
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ret = qatomic_cmpxchg((uint32_t *)g2h(cs, addr), old, new);
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2018-04-11 21:56:50 +03:00
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ret = tswap32(ret);
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break;
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case 2: /* elf32 atomic "new" cmpxchg */
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size = env->gr[23];
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if (size >= 4) {
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return -TARGET_ENOSYS;
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}
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if (((addr | old | new) & ((1 << size) - 1))
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2021-02-12 21:48:47 +03:00
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|| !access_ok(cs, VERIFY_WRITE, addr, 1 << size)
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|| !access_ok(cs, VERIFY_READ, old, 1 << size)
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|| !access_ok(cs, VERIFY_READ, new, 1 << size)) {
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2018-04-11 21:56:50 +03:00
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return -TARGET_EFAULT;
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}
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/* Note that below we use host-endian loads so that the cmpxchg
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can be host-endian as well. */
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switch (size) {
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case 0:
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2021-02-12 21:48:43 +03:00
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old = *(uint8_t *)g2h(cs, old);
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new = *(uint8_t *)g2h(cs, new);
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ret = qatomic_cmpxchg((uint8_t *)g2h(cs, addr), old, new);
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2018-04-11 21:56:50 +03:00
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ret = ret != old;
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break;
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case 1:
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2021-02-12 21:48:43 +03:00
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old = *(uint16_t *)g2h(cs, old);
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new = *(uint16_t *)g2h(cs, new);
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ret = qatomic_cmpxchg((uint16_t *)g2h(cs, addr), old, new);
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2018-04-11 21:56:50 +03:00
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ret = ret != old;
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break;
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case 2:
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2021-02-12 21:48:43 +03:00
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old = *(uint32_t *)g2h(cs, old);
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new = *(uint32_t *)g2h(cs, new);
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ret = qatomic_cmpxchg((uint32_t *)g2h(cs, addr), old, new);
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2018-04-11 21:56:50 +03:00
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ret = ret != old;
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break;
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case 3:
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{
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uint64_t o64, n64, r64;
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2021-02-12 21:48:43 +03:00
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o64 = *(uint64_t *)g2h(cs, old);
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n64 = *(uint64_t *)g2h(cs, new);
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2018-04-11 21:56:50 +03:00
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#ifdef CONFIG_ATOMIC64
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2021-02-12 21:48:43 +03:00
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r64 = qatomic_cmpxchg__nocheck((uint64_t *)g2h(cs, addr),
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2020-09-23 13:56:46 +03:00
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o64, n64);
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2018-04-11 21:56:50 +03:00
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ret = r64 != o64;
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#else
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start_exclusive();
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2021-02-12 21:48:43 +03:00
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r64 = *(uint64_t *)g2h(cs, addr);
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2018-04-11 21:56:50 +03:00
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ret = 1;
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if (r64 == o64) {
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2021-02-12 21:48:43 +03:00
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*(uint64_t *)g2h(cs, addr) = n64;
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2018-04-11 21:56:50 +03:00
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ret = 0;
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}
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end_exclusive();
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#endif
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}
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break;
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}
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break;
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}
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env->gr[28] = ret;
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return 0;
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}
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void cpu_loop(CPUHPPAState *env)
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{
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2019-03-23 03:51:33 +03:00
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CPUState *cs = env_cpu(env);
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2018-04-11 21:56:50 +03:00
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target_siginfo_t info;
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abi_ulong ret;
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int trapnr;
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while (1) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch (trapnr) {
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case EXCP_SYSCALL:
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ret = do_syscall(env, env->gr[20],
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env->gr[26], env->gr[25],
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env->gr[24], env->gr[23],
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env->gr[22], env->gr[21], 0, 0);
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switch (ret) {
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default:
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env->gr[28] = ret;
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/* We arrived here by faking the gateway page. Return. */
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env->iaoq_f = env->gr[31];
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env->iaoq_b = env->gr[31] + 4;
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break;
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case -TARGET_ERESTARTSYS:
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case -TARGET_QEMU_ESIGRETURN:
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break;
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}
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break;
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case EXCP_SYSCALL_LWS:
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env->gr[21] = hppa_lws(env);
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/* We arrived here by faking the gateway page. Return. */
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env->iaoq_f = env->gr[31];
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env->iaoq_b = env->gr[31] + 4;
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break;
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case EXCP_ITLB_MISS:
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case EXCP_DTLB_MISS:
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case EXCP_NA_ITLB_MISS:
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case EXCP_NA_DTLB_MISS:
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case EXCP_IMP:
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case EXCP_DMP:
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case EXCP_DMB:
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case EXCP_PAGE_REF:
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case EXCP_DMAR:
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case EXCP_DMPI:
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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info.si_code = TARGET_SEGV_ACCERR;
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info._sifields._sigfault._addr = env->cr[CR_IOR];
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_UNALIGN:
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info.si_signo = TARGET_SIGBUS;
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info.si_errno = 0;
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info.si_code = 0;
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info._sifields._sigfault._addr = env->cr[CR_IOR];
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_ILL:
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case EXCP_PRIV_OPR:
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case EXCP_PRIV_REG:
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info.si_signo = TARGET_SIGILL;
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info.si_errno = 0;
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info.si_code = TARGET_ILL_ILLOPN;
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info._sifields._sigfault._addr = env->iaoq_f;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_OVERFLOW:
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case EXCP_COND:
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case EXCP_ASSIST:
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info.si_signo = TARGET_SIGFPE;
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info.si_errno = 0;
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info.si_code = 0;
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info._sifields._sigfault._addr = env->iaoq_f;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_DEBUG:
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2018-10-19 20:49:57 +03:00
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info.si_signo = TARGET_SIGTRAP;
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info.si_errno = 0;
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info.si_code = TARGET_TRAP_BRKPT;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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2018-04-11 21:56:50 +03:00
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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default:
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g_assert_not_reached();
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}
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process_pending_signals(env);
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}
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}
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2018-04-11 21:56:33 +03:00
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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2018-04-11 21:56:50 +03:00
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int i;
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for (i = 1; i < 32; i++) {
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env->gr[i] = regs->gr[i];
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}
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env->iaoq_f = regs->iaoq[0];
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env->iaoq_b = regs->iaoq[1];
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2018-04-11 21:56:33 +03:00
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}
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