2022-03-03 07:54:25 +03:00
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/*
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* QEMU model of the Ibex SPI Controller
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* SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/
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*
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* Copyright (C) 2022 Western Digital
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef IBEX_SPI_HOST_H
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#define IBEX_SPI_HOST_H
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#include "hw/sysbus.h"
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#include "hw/hw.h"
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#include "hw/ssi/ssi.h"
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#include "qemu/fifo8.h"
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#include "qom/object.h"
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#include "qemu/timer.h"
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#define TYPE_IBEX_SPI_HOST "ibex-spi"
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#define IBEX_SPI_HOST(obj) \
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OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST)
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/* SPI Registers */
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2022-09-30 06:32:44 +03:00
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#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw1c */
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2022-03-03 07:54:25 +03:00
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#define IBEX_SPI_HOST_INTR_ENABLE (0x04 / 4) /* rw */
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#define IBEX_SPI_HOST_INTR_TEST (0x08 / 4) /* wo */
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#define IBEX_SPI_HOST_ALERT_TEST (0x0c / 4) /* wo */
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#define IBEX_SPI_HOST_CONTROL (0x10 / 4) /* rw */
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#define IBEX_SPI_HOST_STATUS (0x14 / 4) /* ro */
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#define IBEX_SPI_HOST_CONFIGOPTS (0x18 / 4) /* rw */
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#define IBEX_SPI_HOST_CSID (0x1c / 4) /* rw */
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#define IBEX_SPI_HOST_COMMAND (0x20 / 4) /* wo */
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/* RX/TX Modelled by FIFO */
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#define IBEX_SPI_HOST_RXDATA (0x24 / 4)
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#define IBEX_SPI_HOST_TXDATA (0x28 / 4)
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#define IBEX_SPI_HOST_ERROR_ENABLE (0x2c / 4) /* rw */
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2022-09-30 06:32:44 +03:00
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#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw1c */
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2022-03-03 07:54:25 +03:00
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#define IBEX_SPI_HOST_EVENT_ENABLE (0x34 / 4) /* rw */
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/* FIFO Len in Bytes */
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#define IBEX_SPI_HOST_TXFIFO_LEN 288
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#define IBEX_SPI_HOST_RXFIFO_LEN 256
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/* Max Register (Based on addr) */
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#define IBEX_SPI_HOST_MAX_REGS (IBEX_SPI_HOST_EVENT_ENABLE + 1)
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/* MISC */
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#define TX_INTERRUPT_TRIGGER_DELAY_NS 100
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#define BIDIRECTIONAL_TRANSFER 3
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typedef struct {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion mmio;
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uint32_t regs[IBEX_SPI_HOST_MAX_REGS];
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/* Multi-reg that sets config opts per CS */
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uint32_t *config_opts;
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Fifo8 rx_fifo;
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Fifo8 tx_fifo;
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QEMUTimer *fifo_trigger_handle;
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qemu_irq event;
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qemu_irq host_err;
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uint32_t num_cs;
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qemu_irq *cs_lines;
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SSIBus *ssi;
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/* Used to track the init status, for replicating TXDATA ghost writes */
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bool init_status;
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} IbexSPIHostState;
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#endif
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