2019-10-28 18:12:18 +03:00
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/*
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* QEMU PIIX PCI ISA Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/range.h"
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#include "hw/southbridge/piix.h"
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#include "hw/irq.h"
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#include "hw/isa/isa.h"
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#include "hw/xen/xen.h"
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2020-05-08 13:02:22 +03:00
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#include "sysemu/xen.h"
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2019-10-28 18:12:18 +03:00
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#include "sysemu/sysemu.h"
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#include "sysemu/reset.h"
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#include "sysemu/runstate.h"
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#include "migration/vmstate.h"
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#define XEN_PIIX_NUM_PIRQS 128ULL
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#define TYPE_PIIX3_DEVICE "PIIX3"
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#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
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static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
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{
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qemu_set_irq(piix3->pic[pic_irq],
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!!(piix3->pic_levels &
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(((1ULL << PIIX_NUM_PIRQS) - 1) <<
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(pic_irq * PIIX_NUM_PIRQS))));
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}
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static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
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{
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int pic_irq;
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uint64_t mask;
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pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
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if (pic_irq >= PIIX_NUM_PIC_IRQS) {
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return;
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}
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mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
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piix3->pic_levels &= ~mask;
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piix3->pic_levels |= mask * !!level;
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}
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static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
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{
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int pic_irq;
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pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
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if (pic_irq >= PIIX_NUM_PIC_IRQS) {
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return;
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}
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piix3_set_irq_level_internal(piix3, pirq, level);
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piix3_set_irq_pic(piix3, pic_irq);
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}
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static void piix3_set_irq(void *opaque, int pirq, int level)
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{
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PIIX3State *piix3 = opaque;
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piix3_set_irq_level(piix3, pirq, level);
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}
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static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
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{
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PIIX3State *piix3 = opaque;
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int irq = piix3->dev.config[PIIX_PIRQCA + pin];
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PCIINTxRoute route;
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if (irq < PIIX_NUM_PIC_IRQS) {
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route.mode = PCI_INTX_ENABLED;
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route.irq = irq;
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} else {
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route.mode = PCI_INTX_DISABLED;
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route.irq = -1;
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}
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return route;
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}
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/* irq routing is changed. so rebuild bitmap */
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static void piix3_update_irq_levels(PIIX3State *piix3)
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{
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PCIBus *bus = pci_get_bus(&piix3->dev);
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int pirq;
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piix3->pic_levels = 0;
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for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
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piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
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}
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}
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static void piix3_write_config(PCIDevice *dev,
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uint32_t address, uint32_t val, int len)
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{
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pci_default_write_config(dev, address, val, len);
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if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
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PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
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int pic_irq;
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pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
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piix3_update_irq_levels(piix3);
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for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
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piix3_set_irq_pic(piix3, pic_irq);
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}
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}
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}
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static void piix3_write_config_xen(PCIDevice *dev,
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uint32_t address, uint32_t val, int len)
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{
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xen_piix_pci_write_config_client(address, val, len);
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piix3_write_config(dev, address, val, len);
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}
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static void piix3_reset(void *opaque)
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{
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PIIX3State *d = opaque;
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uint8_t *pci_conf = d->dev.config;
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pci_conf[0x04] = 0x07; /* master, memory and I/O */
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pci_conf[0x05] = 0x00;
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pci_conf[0x06] = 0x00;
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pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
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pci_conf[0x4c] = 0x4d;
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pci_conf[0x4e] = 0x03;
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pci_conf[0x4f] = 0x00;
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pci_conf[0x60] = 0x80;
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pci_conf[0x61] = 0x80;
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pci_conf[0x62] = 0x80;
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pci_conf[0x63] = 0x80;
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pci_conf[0x69] = 0x02;
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pci_conf[0x70] = 0x80;
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pci_conf[0x76] = 0x0c;
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pci_conf[0x77] = 0x0c;
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pci_conf[0x78] = 0x02;
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pci_conf[0x79] = 0x00;
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pci_conf[0x80] = 0x00;
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pci_conf[0x82] = 0x00;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa2] = 0x00;
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pci_conf[0xa3] = 0x00;
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pci_conf[0xa4] = 0x00;
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pci_conf[0xa5] = 0x00;
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pci_conf[0xa6] = 0x00;
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pci_conf[0xa7] = 0x00;
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pci_conf[0xa8] = 0x0f;
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pci_conf[0xaa] = 0x00;
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pci_conf[0xab] = 0x00;
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pci_conf[0xac] = 0x00;
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pci_conf[0xae] = 0x00;
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d->pic_levels = 0;
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d->rcr = 0;
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}
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static int piix3_post_load(void *opaque, int version_id)
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{
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PIIX3State *piix3 = opaque;
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int pirq;
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/*
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* Because the i8259 has not been deserialized yet, qemu_irq_raise
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* might bring the system to a different state than the saved one;
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* for example, the interrupt could be masked but the i8259 would
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* not know that yet and would trigger an interrupt in the CPU.
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*
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* Here, we update irq levels without raising the interrupt.
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* Interrupt state will be deserialized separately through the i8259.
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*/
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piix3->pic_levels = 0;
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for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
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piix3_set_irq_level_internal(piix3, pirq,
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pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
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}
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return 0;
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}
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static int piix3_pre_save(void *opaque)
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{
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int i;
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PIIX3State *piix3 = opaque;
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for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
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piix3->pci_irq_levels_vmstate[i] =
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pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
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}
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return 0;
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}
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static bool piix3_rcr_needed(void *opaque)
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{
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PIIX3State *piix3 = opaque;
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return (piix3->rcr != 0);
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}
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static const VMStateDescription vmstate_piix3_rcr = {
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.name = "PIIX3/rcr",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = piix3_rcr_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(rcr, PIIX3State),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_piix3 = {
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.name = "PIIX3",
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.version_id = 3,
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.minimum_version_id = 2,
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.post_load = piix3_post_load,
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.pre_save = piix3_pre_save,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, PIIX3State),
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VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
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PIIX_NUM_PIRQS, 3),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_piix3_rcr,
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NULL
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}
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};
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static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
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{
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PIIX3State *d = opaque;
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if (val & 4) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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return;
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}
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d->rcr = val & 2; /* keep System Reset type only */
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}
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static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
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{
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PIIX3State *d = opaque;
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return d->rcr;
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}
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static const MemoryRegionOps rcr_ops = {
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.read = rcr_read,
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.write = rcr_write,
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.endianness = DEVICE_LITTLE_ENDIAN
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};
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static void piix3_realize(PCIDevice *dev, Error **errp)
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{
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PIIX3State *d = PIIX3_PCI_DEVICE(dev);
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if (!isa_bus_new(DEVICE(d), get_system_memory(),
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pci_address_space_io(dev), errp)) {
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return;
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}
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memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
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"piix3-reset-control", 1);
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memory_region_add_subregion_overlap(pci_address_space_io(dev),
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PIIX_RCR_IOPORT, &d->rcr_mem, 1);
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qemu_register_reset(piix3_reset, d);
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}
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static void pci_piix3_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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dc->desc = "ISA bridge";
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dc->vmsd = &vmstate_piix3;
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dc->hotpluggable = false;
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k->realize = piix3_realize;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
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k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
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k->class_id = PCI_CLASS_BRIDGE_ISA;
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/*
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* Reason: part of PIIX3 southbridge, needs to be wired up by
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* pc_piix.c's pc_init1()
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo piix3_pci_type_info = {
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.name = TYPE_PIIX3_PCI_DEVICE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PIIX3State),
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.abstract = true,
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.class_init = pci_piix3_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void piix3_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->config_write = piix3_write_config;
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}
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static const TypeInfo piix3_info = {
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.name = TYPE_PIIX3_DEVICE,
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.parent = TYPE_PIIX3_PCI_DEVICE,
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.class_init = piix3_class_init,
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};
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static void piix3_xen_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->config_write = piix3_write_config_xen;
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};
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static const TypeInfo piix3_xen_info = {
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.name = TYPE_PIIX3_XEN_DEVICE,
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.parent = TYPE_PIIX3_PCI_DEVICE,
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.class_init = piix3_xen_class_init,
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};
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static void piix3_register_types(void)
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{
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type_register_static(&piix3_pci_type_info);
|
|
|
|
type_register_static(&piix3_info);
|
|
|
|
type_register_static(&piix3_xen_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(piix3_register_types)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Return the global irq number corresponding to a given device irq
|
|
|
|
* pin. We could also use the bus number to have a more precise mapping.
|
|
|
|
*/
|
|
|
|
static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
|
|
|
|
{
|
|
|
|
int slot_addend;
|
2020-10-11 18:04:23 +03:00
|
|
|
slot_addend = PCI_SLOT(pci_dev->devfn) - 1;
|
2019-10-28 18:12:18 +03:00
|
|
|
return (pci_intx + slot_addend) & 3;
|
|
|
|
}
|
|
|
|
|
|
|
|
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
|
|
|
|
{
|
|
|
|
PIIX3State *piix3;
|
|
|
|
PCIDevice *pci_dev;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Xen supports additional interrupt routes from the PCI devices to
|
|
|
|
* the IOAPIC: the four pins of each PCI device on the bus are also
|
|
|
|
* connected to the IOAPIC directly.
|
|
|
|
* These additional routes can be discovered through ACPI.
|
|
|
|
*/
|
|
|
|
if (xen_enabled()) {
|
|
|
|
pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
|
|
|
|
TYPE_PIIX3_XEN_DEVICE);
|
|
|
|
piix3 = PIIX3_PCI_DEVICE(pci_dev);
|
|
|
|
pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
|
|
|
|
piix3, XEN_PIIX_NUM_PIRQS);
|
|
|
|
} else {
|
|
|
|
pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
|
|
|
|
TYPE_PIIX3_DEVICE);
|
|
|
|
piix3 = PIIX3_PCI_DEVICE(pci_dev);
|
|
|
|
pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
|
|
|
|
piix3, PIIX_NUM_PIRQS);
|
|
|
|
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
|
|
|
|
}
|
|
|
|
*isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
|
|
|
|
|
|
|
|
return piix3;
|
|
|
|
}
|