377 lines
14 KiB
C
377 lines
14 KiB
C
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/*
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* QEMU RISC-V Spike Board
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This provides a RISC-V Board with the following devices:
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*
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* 0) HTIF Console and Poweroff
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* 1) CLINT (Timer and IPI)
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* 2) PLIC (Platform Level Interrupt Controller)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_htif.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/spike.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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#include "exec/address-spaces.h"
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#include "elf.h"
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} spike_memmap[] = {
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[SPIKE_MROM] = { 0x1000, 0x2000 },
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[SPIKE_CLINT] = { 0x2000000, 0x10000 },
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[SPIKE_DRAM] = { 0x80000000, 0x0 },
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};
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static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
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{
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int i;
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for (i = 0; i < (len >> 2); i++) {
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stl_phys(&address_space_memory, pa + (i << 2), rom[i]);
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}
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}
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static uint64_t identity_translate(void *opaque, uint64_t addr)
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{
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return addr;
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}
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static uint64_t load_kernel(const char *kernel_filename)
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{
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uint64_t kernel_entry, kernel_high;
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if (load_elf_ram_sym(kernel_filename, identity_translate, NULL,
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&kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0,
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NULL, true, htif_symbol_callback) < 0) {
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error_report("qemu: could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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return kernel_entry;
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}
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static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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void *fdt;
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int cpu;
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uint32_t *cells;
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char *nodename;
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/htif");
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qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc");
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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nodename = g_strdup_printf("/memory@%lx",
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(long)memmap[SPIKE_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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qemu_fdt_add_subnode(fdt, intc);
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qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
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qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
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qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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g_free(isa);
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g_free(intc);
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g_free(nodename);
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}
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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(long)memmap[SPIKE_CLINT].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SPIKE_CLINT].base,
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0x0, memmap[SPIKE_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/chosen");
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qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
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}
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static void spike_v1_10_0_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = spike_memmap;
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SpikeState *s = g_new0(SpikeState, 1);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
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/* Initialize SOC */
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object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
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object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
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&error_abort);
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object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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/* register system main memory (actual RAM) */
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memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
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main_mem);
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/* create device tree */
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create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
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/* boot rom */
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memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom",
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s->fdt_size + 0x2000, &error_fatal);
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memory_region_add_subregion(system_memory, 0x0, boot_rom);
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if (machine->kernel_filename) {
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load_kernel(machine->kernel_filename);
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}
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/* reset vector */
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uint32_t reset_vec[8] = {
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0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
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0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
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0xf1402573, /* csrr a0, mhartid */
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#if defined(TARGET_RISCV32)
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0x0182a283, /* lw t0, 24(t0) */
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#elif defined(TARGET_RISCV64)
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0x0182b283, /* ld t0, 24(t0) */
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#endif
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0x00028067, /* jr t0 */
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0x00000000,
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memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
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0x00000000,
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/* dtb: */
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};
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/* copy in the reset vector */
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copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec));
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/* copy in the device tree */
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qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
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cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec),
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s->fdt, s->fdt_size);
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/* initialize HTIF using symbols found in load_kernel */
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htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds[0]);
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/* Core Local Interruptor (timer and IPI) */
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sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
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smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
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}
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static void spike_v1_09_1_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = spike_memmap;
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SpikeState *s = g_new0(SpikeState, 1);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
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/* Initialize SOC */
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object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
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object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
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&error_abort);
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object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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/* register system main memory (actual RAM) */
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memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
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main_mem);
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/* boot rom */
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memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom",
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0x40000, &error_fatal);
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memory_region_add_subregion(system_memory, 0x0, boot_rom);
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if (machine->kernel_filename) {
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load_kernel(machine->kernel_filename);
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}
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/* reset vector */
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uint32_t reset_vec[8] = {
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0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
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0x00028067, /* jump to DRAM_BASE */
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0x00000000, /* reserved */
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memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
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0, 0, 0, 0 /* trap vector */
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};
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/* part one of config string - before memory size specified */
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const char *config_string_tmpl =
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"platform {\n"
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" vendor ucb;\n"
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" arch spike;\n"
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"};\n"
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"rtc {\n"
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" addr 0x%" PRIx64 "x;\n"
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"};\n"
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"ram {\n"
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" 0 {\n"
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" addr 0x%" PRIx64 "x;\n"
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" size 0x%" PRIx64 "x;\n"
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" };\n"
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"};\n"
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"core {\n"
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" 0" " {\n"
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" " "0 {\n"
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" isa %s;\n"
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" timecmp 0x%" PRIx64 "x;\n"
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" ipi 0x%" PRIx64 "x;\n"
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" };\n"
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" };\n"
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"};\n";
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/* build config string with supplied memory size */
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char *isa = riscv_isa_string(&s->soc.harts[0]);
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size_t config_string_size = strlen(config_string_tmpl) + 48;
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char *config_string = malloc(config_string_size);
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snprintf(config_string, config_string_size, config_string_tmpl,
|
||
|
|
(uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
|
||
|
|
(uint64_t)memmap[SPIKE_DRAM].base,
|
||
|
|
(uint64_t)ram_size, isa,
|
||
|
|
(uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
|
||
|
|
(uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
|
||
|
|
g_free(isa);
|
||
|
|
size_t config_string_len = strlen(config_string);
|
||
|
|
|
||
|
|
/* copy in the reset vector */
|
||
|
|
copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec));
|
||
|
|
|
||
|
|
/* copy in the config string */
|
||
|
|
cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec),
|
||
|
|
config_string, config_string_len);
|
||
|
|
|
||
|
|
/* initialize HTIF using symbols found in load_kernel */
|
||
|
|
htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds[0]);
|
||
|
|
|
||
|
|
/* Core Local Interruptor (timer and IPI) */
|
||
|
|
sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
|
||
|
|
smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo spike_v_1_09_1_device = {
|
||
|
|
.name = TYPE_RISCV_SPIKE_V1_09_1_BOARD,
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(SpikeState),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const TypeInfo spike_v_1_10_0_device = {
|
||
|
|
.name = TYPE_RISCV_SPIKE_V1_10_0_BOARD,
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(SpikeState),
|
||
|
|
};
|
||
|
|
|
||
|
|
static void spike_v1_09_1_machine_init(MachineClass *mc)
|
||
|
|
{
|
||
|
|
mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
|
||
|
|
mc->init = spike_v1_09_1_board_init;
|
||
|
|
mc->max_cpus = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void spike_v1_10_0_machine_init(MachineClass *mc)
|
||
|
|
{
|
||
|
|
mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
|
||
|
|
mc->init = spike_v1_10_0_board_init;
|
||
|
|
mc->max_cpus = 1;
|
||
|
|
mc->is_default = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
|
||
|
|
DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
|
||
|
|
|
||
|
|
static void riscv_spike_board_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&spike_v_1_09_1_device);
|
||
|
|
type_register_static(&spike_v_1_10_0_device);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(riscv_spike_board_register_types);
|