2021-12-10 10:43:20 +03:00
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/*
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* RISC-V translation routines for the RV64Zfh Standard Extension.
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*
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* Copyright (c) 2020 Chih-Min Chao, chihmin.chao@sifive.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_ZFH(ctx) do { \
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2022-02-02 03:52:45 +03:00
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if (!ctx->cfg_ptr->ext_zfh) { \
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2021-12-10 10:43:20 +03:00
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return false; \
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} \
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} while (0)
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2022-02-11 07:39:19 +03:00
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#define REQUIRE_ZHINX_OR_ZFH(ctx) do { \
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if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \
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return false; \
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} \
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} while (0)
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2021-12-10 10:43:26 +03:00
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#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \
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2022-02-02 03:52:45 +03:00
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if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
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2021-12-10 10:43:26 +03:00
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return false; \
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} \
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} while (0)
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2022-02-11 07:39:19 +03:00
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#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \
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if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin || \
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ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \
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return false; \
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} \
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} while (0)
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2021-12-10 10:43:20 +03:00
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static bool trans_flh(DisasContext *ctx, arg_flh *a)
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{
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TCGv_i64 dest;
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TCGv t0;
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REQUIRE_FPU;
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2021-12-10 10:43:26 +03:00
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REQUIRE_ZFH_OR_ZFHMIN(ctx);
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2021-12-10 10:43:20 +03:00
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t0 = get_gpr(ctx, a->rs1, EXT_NONE);
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if (a->imm) {
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TCGv temp = temp_new(ctx);
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tcg_gen_addi_tl(temp, t0, a->imm);
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t0 = temp;
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}
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dest = cpu_fpr[a->rd];
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tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TEUW);
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gen_nanbox_h(dest, dest);
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
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{
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TCGv t0;
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REQUIRE_FPU;
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2021-12-10 10:43:26 +03:00
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REQUIRE_ZFH_OR_ZFHMIN(ctx);
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2021-12-10 10:43:20 +03:00
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t0 = get_gpr(ctx, a->rs1, EXT_NONE);
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if (a->imm) {
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TCGv temp = tcg_temp_new();
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tcg_gen_addi_tl(temp, t0, a->imm);
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t0 = temp;
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}
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tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW);
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return true;
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}
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2021-12-10 10:43:21 +03:00
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static bool trans_fmadd_h(DisasContext *ctx, arg_fmadd_h *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
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2021-12-10 10:43:21 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:19 +03:00
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gen_helper_fmadd_h(dest, cpu_env, src1, src2, src3);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2021-12-10 10:43:21 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fmsub_h(DisasContext *ctx, arg_fmsub_h *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
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2021-12-10 10:43:21 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:19 +03:00
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gen_helper_fmsub_h(dest, cpu_env, src1, src2, src3);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2021-12-10 10:43:21 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fnmsub_h(DisasContext *ctx, arg_fnmsub_h *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
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2021-12-10 10:43:21 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:19 +03:00
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gen_helper_fnmsub_h(dest, cpu_env, src1, src2, src3);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2021-12-10 10:43:21 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fnmadd_h(DisasContext *ctx, arg_fnmadd_h *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
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2021-12-10 10:43:21 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:19 +03:00
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gen_helper_fnmadd_h(dest, cpu_env, src1, src2, src3);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2021-12-10 10:43:21 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fadd_h(DisasContext *ctx, arg_fadd_h *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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2021-12-10 10:43:21 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:19 +03:00
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gen_helper_fadd_h(dest, cpu_env, src1, src2);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2021-12-10 10:43:21 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fsub_h(DisasContext *ctx, arg_fsub_h *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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2021-12-10 10:43:21 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:19 +03:00
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gen_helper_fsub_h(dest, cpu_env, src1, src2);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2021-12-10 10:43:21 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fmul_h(DisasContext *ctx, arg_fmul_h *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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2021-12-10 10:43:21 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:19 +03:00
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gen_helper_fmul_h(dest, cpu_env, src1, src2);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2021-12-10 10:43:21 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fdiv_h(DisasContext *ctx, arg_fdiv_h *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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2021-12-10 10:43:21 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:19 +03:00
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gen_helper_fdiv_h(dest, cpu_env, src1, src2);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2021-12-10 10:43:21 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fsqrt_h(DisasContext *ctx, arg_fsqrt_h *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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2021-12-10 10:43:21 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:19 +03:00
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gen_helper_fsqrt_h(dest, cpu_env, src1);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2021-12-10 10:43:21 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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2021-12-10 10:43:22 +03:00
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static bool trans_fsgnj_h(DisasContext *ctx, arg_fsgnj_h *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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2021-12-10 10:43:22 +03:00
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if (a->rs1 == a->rs2) { /* FMOV */
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2022-02-11 07:39:19 +03:00
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if (!ctx->cfg_ptr->ext_zfinx) {
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gen_check_nanbox_h(dest, src1);
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} else {
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tcg_gen_ext16s_i64(dest, src1);
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}
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2021-12-10 10:43:22 +03:00
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} else {
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2022-02-11 07:39:19 +03:00
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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if (!ctx->cfg_ptr->ext_zfinx) {
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TCGv_i64 rs1 = tcg_temp_new_i64();
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TCGv_i64 rs2 = tcg_temp_new_i64();
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gen_check_nanbox_h(rs1, src1);
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gen_check_nanbox_h(rs2, src2);
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/* This formulation retains the nanboxing of rs2 in normal 'Zfh'. */
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tcg_gen_deposit_i64(dest, rs2, rs1, 0, 15);
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tcg_temp_free_i64(rs1);
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tcg_temp_free_i64(rs2);
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} else {
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tcg_gen_deposit_i64(dest, src2, src1, 0, 15);
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tcg_gen_ext16s_i64(dest, dest);
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}
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2021-12-10 10:43:22 +03:00
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}
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2022-02-11 07:39:19 +03:00
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gen_set_fpr_hs(ctx, a->rd, dest);
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2021-12-10 10:43:22 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsgnjn_h *a)
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{
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TCGv_i64 rs1, rs2, mask;
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REQUIRE_FPU;
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2022-02-11 07:39:19 +03:00
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REQUIRE_ZHINX_OR_ZFH(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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2021-12-10 10:43:22 +03:00
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rs1 = tcg_temp_new_i64();
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2022-02-11 07:39:19 +03:00
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if (!ctx->cfg_ptr->ext_zfinx) {
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gen_check_nanbox_h(rs1, src1);
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} else {
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tcg_gen_mov_i64(rs1, src1);
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}
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2021-12-10 10:43:22 +03:00
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if (a->rs1 == a->rs2) { /* FNEG */
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2022-02-11 07:39:19 +03:00
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tcg_gen_xori_i64(dest, rs1, MAKE_64BIT_MASK(15, 1));
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2021-12-10 10:43:22 +03:00
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} else {
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2022-02-11 07:39:19 +03:00
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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2021-12-10 10:43:22 +03:00
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|
rs2 = tcg_temp_new_i64();
|
2022-02-11 07:39:19 +03:00
|
|
|
|
|
|
|
if (!ctx->cfg_ptr->ext_zfinx) {
|
|
|
|
gen_check_nanbox_h(rs2, src2);
|
|
|
|
} else {
|
|
|
|
tcg_gen_mov_i64(rs2, src2);
|
|
|
|
}
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Replace bit 15 in rs1 with inverse in rs2.
|
|
|
|
* This formulation retains the nanboxing of rs1.
|
|
|
|
*/
|
|
|
|
mask = tcg_const_i64(~MAKE_64BIT_MASK(15, 1));
|
|
|
|
tcg_gen_not_i64(rs2, rs2);
|
|
|
|
tcg_gen_andc_i64(rs2, rs2, mask);
|
2022-02-11 07:39:19 +03:00
|
|
|
tcg_gen_and_i64(dest, mask, rs1);
|
|
|
|
tcg_gen_or_i64(dest, dest, rs2);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
tcg_temp_free_i64(mask);
|
|
|
|
tcg_temp_free_i64(rs2);
|
|
|
|
}
|
2022-02-11 07:39:19 +03:00
|
|
|
/* signed-extended intead of nanboxing for result if enable zfinx */
|
|
|
|
if (ctx->cfg_ptr->ext_zfinx) {
|
|
|
|
tcg_gen_ext16s_i64(dest, dest);
|
|
|
|
}
|
|
|
|
tcg_temp_free_i64(rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fsgnjx_h(DisasContext *ctx, arg_fsgnjx_h *a)
|
|
|
|
{
|
|
|
|
TCGv_i64 rs1, rs2;
|
|
|
|
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
|
|
|
|
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
rs1 = tcg_temp_new_i64();
|
2022-02-11 07:39:19 +03:00
|
|
|
if (!ctx->cfg_ptr->ext_zfinx) {
|
|
|
|
gen_check_nanbox_h(rs1, src1);
|
|
|
|
} else {
|
|
|
|
tcg_gen_mov_i64(rs1, src1);
|
|
|
|
}
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
if (a->rs1 == a->rs2) { /* FABS */
|
2022-02-11 07:39:19 +03:00
|
|
|
tcg_gen_andi_i64(dest, rs1, ~MAKE_64BIT_MASK(15, 1));
|
2021-12-10 10:43:22 +03:00
|
|
|
} else {
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2021-12-10 10:43:22 +03:00
|
|
|
rs2 = tcg_temp_new_i64();
|
2022-02-11 07:39:19 +03:00
|
|
|
|
|
|
|
if (!ctx->cfg_ptr->ext_zfinx) {
|
|
|
|
gen_check_nanbox_h(rs2, src2);
|
|
|
|
} else {
|
|
|
|
tcg_gen_mov_i64(rs2, src2);
|
|
|
|
}
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Xor bit 15 in rs1 with that in rs2.
|
|
|
|
* This formulation retains the nanboxing of rs1.
|
|
|
|
*/
|
2022-02-11 07:39:19 +03:00
|
|
|
tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(15, 1));
|
|
|
|
tcg_gen_xor_i64(dest, rs1, dest);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
tcg_temp_free_i64(rs2);
|
|
|
|
}
|
2022-02-11 07:39:19 +03:00
|
|
|
/* signed-extended intead of nanboxing for result if enable zfinx */
|
|
|
|
if (ctx->cfg_ptr->ext_zfinx) {
|
|
|
|
tcg_gen_ext16s_i64(dest, dest);
|
|
|
|
}
|
|
|
|
tcg_temp_free_i64(rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2021-12-10 10:43:21 +03:00
|
|
|
static bool trans_fmin_h(DisasContext *ctx, arg_fmin_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
|
|
|
|
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2021-12-10 10:43:21 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fmin_h(dest, cpu_env, src1, src2);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2021-12-10 10:43:21 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:21 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
|
|
|
|
|
|
|
gen_helper_fmax_h(dest, cpu_env, src1, src2);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2021-12-10 10:43:21 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
|
|
|
|
|
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fcvt_s_h(dest, cpu_env, src1);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
|
|
|
|
REQUIRE_ZDINX_OR_D(ctx);
|
|
|
|
|
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fcvt_d_h(dest, cpu_env, src1);
|
|
|
|
gen_set_fpr_d(ctx, a->rd, dest);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_set_rm(ctx, a->rm);
|
|
|
|
gen_helper_fcvt_h_s(dest, cpu_env, src1);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2021-12-10 10:43:22 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
|
|
|
|
REQUIRE_ZDINX_OR_D(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
|
|
|
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_set_rm(ctx, a->rm);
|
|
|
|
gen_helper_fcvt_h_d(dest, cpu_env, src1);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2021-12-10 10:43:22 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2021-12-10 10:43:23 +03:00
|
|
|
static bool trans_feq_h(DisasContext *ctx, arg_feq_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:23 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2021-12-10 10:43:23 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_feq_h(dest, cpu_env, src1, src2);
|
2021-12-10 10:43:23 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_flt_h(DisasContext *ctx, arg_flt_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:23 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2021-12-10 10:43:23 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_flt_h(dest, cpu_env, src1, src2);
|
2021-12-10 10:43:23 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:23 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2021-12-10 10:43:23 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fle_h(dest, cpu_env, src1, src2);
|
2021-12-10 10:43:23 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2021-12-10 10:43:24 +03:00
|
|
|
static bool trans_fclass_h(DisasContext *ctx, arg_fclass_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:24 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-12-10 10:43:24 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fclass_h(dest, cpu_env, src1);
|
2021-12-10 10:43:24 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2021-12-10 10:43:22 +03:00
|
|
|
static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fcvt_w_h(dest, cpu_env, src1);
|
2021-12-10 10:43:22 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_wu_h(DisasContext *ctx, arg_fcvt_wu_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fcvt_wu_h(dest, cpu_env, src1);
|
2021-12-10 10:43:22 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_h_w(DisasContext *ctx, arg_fcvt_h_w *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
2021-12-10 10:43:22 +03:00
|
|
|
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
|
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fcvt_h_w(dest, cpu_env, t0);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
2021-12-10 10:43:22 +03:00
|
|
|
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
|
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fcvt_h_wu(dest, cpu_env, t0);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2021-12-10 10:43:26 +03:00
|
|
|
REQUIRE_ZFH_OR_ZFHMIN(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
|
|
|
|
|
|
|
#if defined(TARGET_RISCV64)
|
|
|
|
/* 16 bits -> 64 bits */
|
|
|
|
tcg_gen_ext16s_tl(dest, cpu_fpr[a->rs1]);
|
|
|
|
#else
|
|
|
|
/* 16 bits -> 32 bits */
|
|
|
|
tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
|
|
|
|
tcg_gen_ext16s_tl(dest, dest);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2021-12-10 10:43:26 +03:00
|
|
|
REQUIRE_ZFH_OR_ZFHMIN(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
|
|
|
|
|
|
|
|
tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
|
|
|
|
gen_nanbox_h(cpu_fpr[a->rd], cpu_fpr[a->rd]);
|
|
|
|
|
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_l_h(DisasContext *ctx, arg_fcvt_l_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fcvt_l_h(dest, cpu_env, src1);
|
2021-12-10 10:43:22 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_lu_h(DisasContext *ctx, arg_fcvt_lu_h *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fcvt_lu_h(dest, cpu_env, src1);
|
2021-12-10 10:43:22 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_h_l(DisasContext *ctx, arg_fcvt_h_l *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
2021-12-10 10:43:22 +03:00
|
|
|
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
|
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fcvt_h_l(dest, cpu_env, t0);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_h_lu(DisasContext *ctx, arg_fcvt_h_lu *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:19 +03:00
|
|
|
REQUIRE_ZHINX_OR_ZFH(ctx);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
2022-02-11 07:39:19 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
2021-12-10 10:43:22 +03:00
|
|
|
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
|
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:19 +03:00
|
|
|
gen_helper_fcvt_h_lu(dest, cpu_env, t0);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2021-12-10 10:43:22 +03:00
|
|
|
|
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|