2019-02-13 18:53:51 +03:00
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/*
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* RISC-V translation routines for the RV64F Standard Extension.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_FPU do {\
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if (ctx->mstatus_fs == 0) \
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2022-02-11 07:39:17 +03:00
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if (!ctx->cfg_ptr->ext_zfinx) \
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return false; \
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} while (0)
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#define REQUIRE_ZFINX_OR_F(ctx) do {\
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if (!ctx->cfg_ptr->ext_zfinx) { \
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REQUIRE_EXT(ctx, RVF); \
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} \
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2019-02-13 18:53:51 +03:00
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} while (0)
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static bool trans_flw(DisasContext *ctx, arg_flw *a)
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{
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2021-08-23 22:55:26 +03:00
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TCGv_i64 dest;
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TCGv addr;
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2019-02-13 18:53:51 +03:00
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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2022-01-20 15:20:40 +03:00
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addr = get_address(ctx, a->rs1, a->imm);
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2021-08-23 22:55:26 +03:00
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dest = cpu_fpr[a->rd];
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tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
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gen_nanbox_s(dest, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
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{
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2021-08-23 22:55:26 +03:00
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TCGv addr;
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2020-07-24 03:28:07 +03:00
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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2019-02-13 18:53:51 +03:00
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2022-01-20 15:20:40 +03:00
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addr = get_address(ctx, a->rs1, a->imm);
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2021-08-23 22:55:26 +03:00
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tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
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2019-02-13 18:53:51 +03:00
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return true;
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}
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static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
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2019-02-13 18:53:51 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:17 +03:00
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gen_helper_fmadd_s(dest, cpu_env, src1, src2, src3);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
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2019-02-13 18:53:51 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:17 +03:00
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gen_helper_fmsub_s(dest, cpu_env, src1, src2, src3);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
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2019-02-13 18:53:51 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:17 +03:00
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gen_helper_fnmsub_s(dest, cpu_env, src1, src2, src3);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
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2019-02-13 18:53:51 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:17 +03:00
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gen_helper_fnmadd_s(dest, cpu_env, src1, src2, src3);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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2019-02-13 18:53:51 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:17 +03:00
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gen_helper_fadd_s(dest, cpu_env, src1, src2);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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2019-02-13 18:53:51 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:17 +03:00
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gen_helper_fsub_s(dest, cpu_env, src1, src2);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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2019-02-13 18:53:51 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:17 +03:00
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gen_helper_fmul_s(dest, cpu_env, src1, src2);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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2019-02-13 18:53:51 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:17 +03:00
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gen_helper_fdiv_s(dest, cpu_env, src1, src2);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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2019-02-13 18:53:51 +03:00
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gen_set_rm(ctx, a->rm);
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2022-02-11 07:39:17 +03:00
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gen_helper_fsqrt_s(dest, cpu_env, src1);
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gen_set_fpr_hs(ctx, a->rd, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
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{
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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2020-07-24 03:28:05 +03:00
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2019-02-13 18:53:51 +03:00
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if (a->rs1 == a->rs2) { /* FMOV */
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2022-02-11 07:39:17 +03:00
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if (!ctx->cfg_ptr->ext_zfinx) {
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gen_check_nanbox_s(dest, src1);
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} else {
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tcg_gen_ext32s_i64(dest, src1);
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}
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2019-02-13 18:53:51 +03:00
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} else { /* FSGNJ */
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2022-02-11 07:39:17 +03:00
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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if (!ctx->cfg_ptr->ext_zfinx) {
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TCGv_i64 rs1 = tcg_temp_new_i64();
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TCGv_i64 rs2 = tcg_temp_new_i64();
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gen_check_nanbox_s(rs1, src1);
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gen_check_nanbox_s(rs2, src2);
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/* This formulation retains the nanboxing of rs2 in normal 'F'. */
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tcg_gen_deposit_i64(dest, rs2, rs1, 0, 31);
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tcg_temp_free_i64(rs1);
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tcg_temp_free_i64(rs2);
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} else {
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tcg_gen_deposit_i64(dest, src2, src1, 0, 31);
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tcg_gen_ext32s_i64(dest, dest);
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}
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2019-02-13 18:53:51 +03:00
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}
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2022-02-11 07:39:17 +03:00
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gen_set_fpr_hs(ctx, a->rd, dest);
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2019-02-13 18:53:51 +03:00
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
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{
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2020-07-24 03:28:05 +03:00
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TCGv_i64 rs1, rs2, mask;
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2019-02-13 18:53:51 +03:00
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REQUIRE_FPU;
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2022-02-11 07:39:17 +03:00
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REQUIRE_ZFINX_OR_F(ctx);
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2020-07-24 03:28:05 +03:00
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2022-02-11 07:39:17 +03:00
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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2020-07-24 03:28:05 +03:00
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2022-02-11 07:39:17 +03:00
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rs1 = tcg_temp_new_i64();
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if (!ctx->cfg_ptr->ext_zfinx) {
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gen_check_nanbox_s(rs1, src1);
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} else {
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tcg_gen_mov_i64(rs1, src1);
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}
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2019-02-13 18:53:51 +03:00
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if (a->rs1 == a->rs2) { /* FNEG */
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2022-02-11 07:39:17 +03:00
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tcg_gen_xori_i64(dest, rs1, MAKE_64BIT_MASK(31, 1));
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2019-02-13 18:53:51 +03:00
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} else {
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2022-02-11 07:39:17 +03:00
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TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
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2020-07-24 03:28:05 +03:00
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rs2 = tcg_temp_new_i64();
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2022-02-11 07:39:17 +03:00
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if (!ctx->cfg_ptr->ext_zfinx) {
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gen_check_nanbox_s(rs2, src2);
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} else {
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tcg_gen_mov_i64(rs2, src2);
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}
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2020-07-24 03:28:05 +03:00
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/*
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* Replace bit 31 in rs1 with inverse in rs2.
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* This formulation retains the nanboxing of rs1.
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*/
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2021-08-23 22:55:06 +03:00
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mask = tcg_constant_i64(~MAKE_64BIT_MASK(31, 1));
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2020-07-24 03:28:05 +03:00
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tcg_gen_nor_i64(rs2, rs2, mask);
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2022-02-11 07:39:17 +03:00
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tcg_gen_and_i64(dest, mask, rs1);
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tcg_gen_or_i64(dest, dest, rs2);
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2020-07-24 03:28:05 +03:00
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tcg_temp_free_i64(rs2);
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2019-02-13 18:53:51 +03:00
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}
|
2022-02-11 07:39:17 +03:00
|
|
|
/* signed-extended intead of nanboxing for result if enable zfinx */
|
|
|
|
if (ctx->cfg_ptr->ext_zfinx) {
|
|
|
|
tcg_gen_ext32s_i64(dest, dest);
|
|
|
|
}
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2020-07-24 03:28:05 +03:00
|
|
|
tcg_temp_free_i64(rs1);
|
2019-02-13 18:53:51 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
|
|
|
|
{
|
2020-07-24 03:28:05 +03:00
|
|
|
TCGv_i64 rs1, rs2;
|
|
|
|
|
2019-02-13 18:53:51 +03:00
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2020-07-24 03:28:05 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2020-07-24 03:28:05 +03:00
|
|
|
rs1 = tcg_temp_new_i64();
|
2022-02-11 07:39:17 +03:00
|
|
|
|
|
|
|
if (!ctx->cfg_ptr->ext_zfinx) {
|
|
|
|
gen_check_nanbox_s(rs1, src1);
|
|
|
|
} else {
|
|
|
|
tcg_gen_mov_i64(rs1, src1);
|
|
|
|
}
|
2020-07-24 03:28:05 +03:00
|
|
|
|
2019-02-13 18:53:51 +03:00
|
|
|
if (a->rs1 == a->rs2) { /* FABS */
|
2022-02-11 07:39:17 +03:00
|
|
|
tcg_gen_andi_i64(dest, rs1, ~MAKE_64BIT_MASK(31, 1));
|
2019-02-13 18:53:51 +03:00
|
|
|
} else {
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2020-07-24 03:28:05 +03:00
|
|
|
rs2 = tcg_temp_new_i64();
|
2022-02-11 07:39:17 +03:00
|
|
|
|
|
|
|
if (!ctx->cfg_ptr->ext_zfinx) {
|
|
|
|
gen_check_nanbox_s(rs2, src2);
|
|
|
|
} else {
|
|
|
|
tcg_gen_mov_i64(rs2, src2);
|
|
|
|
}
|
2020-07-24 03:28:05 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Xor bit 31 in rs1 with that in rs2.
|
|
|
|
* This formulation retains the nanboxing of rs1.
|
|
|
|
*/
|
2022-02-11 07:39:17 +03:00
|
|
|
tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(31, 1));
|
|
|
|
tcg_gen_xor_i64(dest, rs1, dest);
|
2020-07-24 03:28:05 +03:00
|
|
|
|
|
|
|
tcg_temp_free_i64(rs2);
|
2019-02-13 18:53:51 +03:00
|
|
|
}
|
2022-02-11 07:39:17 +03:00
|
|
|
/* signed-extended intead of nanboxing for result if enable zfinx */
|
|
|
|
if (ctx->cfg_ptr->ext_zfinx) {
|
|
|
|
tcg_gen_ext32s_i64(dest, dest);
|
|
|
|
}
|
2020-07-24 03:28:05 +03:00
|
|
|
tcg_temp_free_i64(rs1);
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
|
|
|
|
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fmin_s(dest, cpu_env, src1, src2);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
|
|
|
|
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fmax_s(dest, cpu_env, src1, src2);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fcvt_w_s(dest, cpu_env, src1);
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fcvt_wu_s(dest, cpu_env, src1);
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
|
|
|
|
{
|
|
|
|
/* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2019-02-13 18:53:51 +03:00
|
|
|
#if defined(TARGET_RISCV64)
|
2022-02-11 07:39:17 +03:00
|
|
|
tcg_gen_ext32s_tl(dest, src1);
|
2019-02-13 18:53:51 +03:00
|
|
|
#else
|
2022-02-11 07:39:17 +03:00
|
|
|
tcg_gen_extrl_i64_i32(dest, src1);
|
2019-02-13 18:53:51 +03:00
|
|
|
#endif
|
|
|
|
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2021-08-23 22:55:26 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2021-08-23 22:55:26 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_feq_s(dest, cpu_env, src1, src2);
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2021-08-23 22:55:26 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2021-08-23 22:55:26 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_flt_s(dest, cpu_env, src1, src2);
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2021-08-23 22:55:26 +03:00
|
|
|
|
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
|
|
|
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
|
2021-08-23 22:55:26 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fle_s(dest, cpu_env, src1, src2);
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fclass_s(dest, cpu_env, src1);
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fcvt_s_w(dest, cpu_env, src);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
|
|
|
|
{
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fcvt_s_wu(dest, cpu_env, src);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
|
|
|
|
{
|
|
|
|
/* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
|
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
|
2019-02-13 18:53:51 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
tcg_gen_extu_tl_i64(dest, src);
|
|
|
|
gen_nanbox_s(dest, dest);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2019-02-13 18:53:51 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
2019-02-13 18:53:52 +03:00
|
|
|
|
|
|
|
static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
|
|
|
|
{
|
2021-04-24 06:34:12 +03:00
|
|
|
REQUIRE_64BIT(ctx);
|
2019-02-13 18:53:52 +03:00
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:52 +03:00
|
|
|
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-08-23 22:55:26 +03:00
|
|
|
|
2019-02-13 18:53:52 +03:00
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fcvt_l_s(dest, cpu_env, src1);
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
2019-02-13 18:53:52 +03:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
|
|
|
|
{
|
2021-04-24 06:34:12 +03:00
|
|
|
REQUIRE_64BIT(ctx);
|
2019-02-13 18:53:52 +03:00
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:52 +03:00
|
|
|
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
2021-08-23 22:55:26 +03:00
|
|
|
|
2019-02-13 18:53:52 +03:00
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fcvt_lu_s(dest, cpu_env, src1);
|
2021-08-23 22:55:26 +03:00
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
2019-02-13 18:53:52 +03:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
|
|
|
|
{
|
2021-04-24 06:34:12 +03:00
|
|
|
REQUIRE_64BIT(ctx);
|
2019-02-13 18:53:52 +03:00
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:52 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
|
2019-02-13 18:53:52 +03:00
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fcvt_s_l(dest, cpu_env, src);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2019-02-13 18:53:52 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
|
|
|
|
{
|
2021-04-24 06:34:12 +03:00
|
|
|
REQUIRE_64BIT(ctx);
|
2019-02-13 18:53:52 +03:00
|
|
|
REQUIRE_FPU;
|
2022-02-11 07:39:17 +03:00
|
|
|
REQUIRE_ZFINX_OR_F(ctx);
|
2019-02-13 18:53:52 +03:00
|
|
|
|
2022-02-11 07:39:17 +03:00
|
|
|
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
2021-08-23 22:55:26 +03:00
|
|
|
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
|
2019-02-13 18:53:52 +03:00
|
|
|
|
|
|
|
gen_set_rm(ctx, a->rm);
|
2022-02-11 07:39:17 +03:00
|
|
|
gen_helper_fcvt_s_lu(dest, cpu_env, src);
|
|
|
|
gen_set_fpr_hs(ctx, a->rd, dest);
|
2019-02-13 18:53:52 +03:00
|
|
|
mark_fs_dirty(ctx);
|
|
|
|
return true;
|
|
|
|
}
|