2007-09-17 01:08:06 +04:00
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/*
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2005-11-26 13:38:39 +03:00
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* ARM Integrator CP System emulation.
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*
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2007-04-06 20:49:48 +04:00
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* Copyright (c) 2005-2007 CodeSourcery.
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2005-11-26 13:38:39 +03:00
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* Written by Paul Brook
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*
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2011-06-26 06:21:35 +04:00
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* This code is licensed under the GPL
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2005-11-26 13:38:39 +03:00
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*/
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2015-12-07 19:23:45 +03:00
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#include "qemu/osdep.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
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#include "qapi/error.h"
|
2016-01-19 23:51:44 +03:00
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|
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#include "cpu.h"
|
2013-02-04 18:40:22 +04:00
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#include "hw/sysbus.h"
|
2019-08-12 08:23:45 +03:00
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|
#include "migration/vmstate.h"
|
2013-02-04 18:40:22 +04:00
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#include "hw/boards.h"
|
2019-05-23 16:47:43 +03:00
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#include "hw/arm/boot.h"
|
2013-10-22 18:16:06 +04:00
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#include "hw/misc/arm_integrator_debug.h"
|
2019-04-12 19:54:16 +03:00
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|
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#include "hw/net/smc91c111.h"
|
2012-10-24 10:43:34 +04:00
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#include "net/net.h"
|
2012-12-17 21:19:49 +04:00
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#include "exec/address-spaces.h"
|
2019-08-12 08:23:59 +03:00
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#include "sysemu/runstate.h"
|
2012-12-17 21:20:04 +04:00
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#include "sysemu/sysemu.h"
|
2020-05-18 17:03:06 +03:00
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#include "qemu/log.h"
|
2014-12-16 02:09:50 +03:00
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#include "qemu/error-report.h"
|
2016-06-06 18:59:31 +03:00
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#include "hw/char/pl011.h"
|
2019-08-12 08:23:48 +03:00
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#include "hw/hw.h"
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2019-08-12 08:23:42 +03:00
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#include "hw/irq.h"
|
2020-07-05 15:24:24 +03:00
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#include "hw/sd/sd.h"
|
2020-09-03 23:43:22 +03:00
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#include "qom/object.h"
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2023-09-22 18:21:39 +03:00
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#include "audio/audio.h"
|
2005-11-26 13:38:39 +03:00
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|
2013-07-24 03:00:27 +04:00
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#define TYPE_INTEGRATOR_CM "integrator_core"
|
2020-09-16 21:25:19 +03:00
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OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState, INTEGRATOR_CM)
|
2013-07-24 03:00:27 +04:00
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2020-09-03 23:43:22 +03:00
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struct IntegratorCMState {
|
2013-07-24 03:00:27 +04:00
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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|
2011-10-17 19:28:26 +04:00
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MemoryRegion iomem;
|
2009-07-15 15:43:31 +04:00
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uint32_t memsz;
|
2011-07-25 16:03:19 +04:00
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MemoryRegion flash;
|
2005-11-26 13:38:39 +03:00
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uint32_t cm_osc;
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uint32_t cm_ctrl;
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uint32_t cm_lock;
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uint32_t cm_auxosc;
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uint32_t cm_sdram;
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uint32_t cm_init;
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uint32_t cm_flags;
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uint32_t cm_nvflags;
|
2013-12-10 17:24:51 +04:00
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uint32_t cm_refcnt_offset;
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2005-11-26 13:38:39 +03:00
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uint32_t int_level;
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uint32_t irq_enabled;
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uint32_t fiq_enabled;
|
2020-09-03 23:43:22 +03:00
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};
|
2005-11-26 13:38:39 +03:00
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static uint8_t integrator_spd[128] = {
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128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
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0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
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};
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|
2017-02-07 21:29:58 +03:00
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static const VMStateDescription vmstate_integratorcm = {
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.name = "integratorcm",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cm_osc, IntegratorCMState),
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VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
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VMSTATE_UINT32(cm_lock, IntegratorCMState),
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VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
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VMSTATE_UINT32(cm_sdram, IntegratorCMState),
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VMSTATE_UINT32(cm_init, IntegratorCMState),
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VMSTATE_UINT32(cm_flags, IntegratorCMState),
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VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
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VMSTATE_UINT32(int_level, IntegratorCMState),
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VMSTATE_UINT32(irq_enabled, IntegratorCMState),
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VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
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VMSTATE_END_OF_LIST()
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}
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};
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|
2012-10-23 14:30:10 +04:00
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static uint64_t integratorcm_read(void *opaque, hwaddr offset,
|
2011-10-17 19:28:26 +04:00
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unsigned size)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
2013-07-24 03:00:27 +04:00
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IntegratorCMState *s = opaque;
|
2005-11-26 13:38:39 +03:00
|
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if (offset >= 0x100 && offset < 0x200) {
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|
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/* CM_SPD */
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if (offset >= 0x180)
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return 0;
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return integrator_spd[offset >> 2];
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|
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|
}
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switch (offset >> 2) {
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case 0: /* CM_ID */
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return 0x411a3001;
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case 1: /* CM_PROC */
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return 0;
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case 2: /* CM_OSC */
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return s->cm_osc;
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case 3: /* CM_CTRL */
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return s->cm_ctrl;
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case 4: /* CM_STAT */
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return 0x00100000;
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case 5: /* CM_LOCK */
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if (s->cm_lock == 0xa05f) {
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return 0x1a05f;
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} else {
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return s->cm_lock;
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}
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case 6: /* CM_LMBUSCNT */
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/* ??? High frequency timer. */
|
2009-05-08 05:35:15 +04:00
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hw_error("integratorcm_read: CM_LMBUSCNT");
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2005-11-26 13:38:39 +03:00
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case 7: /* CM_AUXOSC */
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return s->cm_auxosc;
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case 8: /* CM_SDRAM */
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return s->cm_sdram;
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case 9: /* CM_INIT */
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return s->cm_init;
|
2013-12-10 17:24:51 +04:00
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case 10: /* CM_REFCNT */
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/* This register, CM_REFCNT, provides a 32-bit count value.
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* The count increments at the fixed reference clock frequency of 24MHz
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* and can be used as a real-time counter.
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*/
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return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
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1000) - s->cm_refcnt_offset;
|
2005-11-26 13:38:39 +03:00
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case 12: /* CM_FLAGS */
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return s->cm_flags;
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case 14: /* CM_NVFLAGS */
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return s->cm_nvflags;
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case 16: /* CM_IRQ_STAT */
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return s->int_level & s->irq_enabled;
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case 17: /* CM_IRQ_RSTAT */
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return s->int_level;
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case 18: /* CM_IRQ_ENSET */
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return s->irq_enabled;
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case 20: /* CM_SOFT_INTSET */
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return s->int_level & 1;
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case 24: /* CM_FIQ_STAT */
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return s->int_level & s->fiq_enabled;
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case 25: /* CM_FIQ_RSTAT */
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return s->int_level;
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case 26: /* CM_FIQ_ENSET */
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return s->fiq_enabled;
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case 32: /* CM_VOLTAGE_CTL0 */
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case 33: /* CM_VOLTAGE_CTL1 */
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case 34: /* CM_VOLTAGE_CTL2 */
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case 35: /* CM_VOLTAGE_CTL3 */
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/* ??? Voltage control unimplemented. */
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return 0;
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default:
|
2020-05-18 17:03:06 +03:00
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qemu_log_mask(LOG_UNIMP,
|
|
|
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"%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
|
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__func__, offset);
|
2005-11-26 13:38:39 +03:00
|
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return 0;
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|
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}
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}
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|
2013-07-24 03:00:27 +04:00
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static void integratorcm_do_remap(IntegratorCMState *s)
|
2005-11-26 13:38:39 +03:00
|
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{
|
2012-01-06 22:58:28 +04:00
|
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/* Sync memory region state with CM_CTRL REMAP bit:
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* bit 0 => flash at address 0; bit 1 => RAM
|
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*/
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memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
|
2005-11-26 13:38:39 +03:00
|
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}
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|
2013-07-24 03:00:27 +04:00
|
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static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
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if (value & 8) {
|
2017-05-16 00:41:13 +03:00
|
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|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
2005-11-26 13:38:39 +03:00
|
|
|
}
|
2011-09-12 18:43:31 +04:00
|
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if ((s->cm_ctrl ^ value) & 1) {
|
|
|
|
/* (value & 1) != 0 means the green "MISC LED" is lit.
|
|
|
|
* We don't have any nice place to display LEDs. printf is a bad
|
|
|
|
* idea because Linux uses the LED as a heartbeat and the output
|
|
|
|
* will swamp anything else on the terminal.
|
|
|
|
*/
|
2005-11-26 13:38:39 +03:00
|
|
|
}
|
2011-09-12 18:43:31 +04:00
|
|
|
/* Note that the RESET bit [3] always reads as zero */
|
|
|
|
s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
|
2012-01-06 22:58:28 +04:00
|
|
|
integratorcm_do_remap(s);
|
2005-11-26 13:38:39 +03:00
|
|
|
}
|
|
|
|
|
2013-07-24 03:00:27 +04:00
|
|
|
static void integratorcm_update(IntegratorCMState *s)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
|
|
|
/* ??? The CPU irq/fiq is raised when either the core module or base PIC
|
|
|
|
are active. */
|
|
|
|
if (s->int_level & (s->irq_enabled | s->fiq_enabled))
|
2009-05-08 05:35:15 +04:00
|
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|
hw_error("Core module interrupt\n");
|
2005-11-26 13:38:39 +03:00
|
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}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static void integratorcm_write(void *opaque, hwaddr offset,
|
2011-10-17 19:28:26 +04:00
|
|
|
uint64_t value, unsigned size)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
2013-07-24 03:00:27 +04:00
|
|
|
IntegratorCMState *s = opaque;
|
2005-11-26 13:38:39 +03:00
|
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|
switch (offset >> 2) {
|
|
|
|
case 2: /* CM_OSC */
|
|
|
|
if (s->cm_lock == 0xa05f)
|
|
|
|
s->cm_osc = value;
|
|
|
|
break;
|
|
|
|
case 3: /* CM_CTRL */
|
|
|
|
integratorcm_set_ctrl(s, value);
|
|
|
|
break;
|
|
|
|
case 5: /* CM_LOCK */
|
|
|
|
s->cm_lock = value & 0xffff;
|
|
|
|
break;
|
|
|
|
case 7: /* CM_AUXOSC */
|
|
|
|
if (s->cm_lock == 0xa05f)
|
|
|
|
s->cm_auxosc = value;
|
|
|
|
break;
|
|
|
|
case 8: /* CM_SDRAM */
|
|
|
|
s->cm_sdram = value;
|
|
|
|
break;
|
|
|
|
case 9: /* CM_INIT */
|
|
|
|
/* ??? This can change the memory bus frequency. */
|
|
|
|
s->cm_init = value;
|
|
|
|
break;
|
|
|
|
case 12: /* CM_FLAGSS */
|
|
|
|
s->cm_flags |= value;
|
|
|
|
break;
|
|
|
|
case 13: /* CM_FLAGSC */
|
|
|
|
s->cm_flags &= ~value;
|
|
|
|
break;
|
|
|
|
case 14: /* CM_NVFLAGSS */
|
|
|
|
s->cm_nvflags |= value;
|
|
|
|
break;
|
|
|
|
case 15: /* CM_NVFLAGSS */
|
|
|
|
s->cm_nvflags &= ~value;
|
|
|
|
break;
|
|
|
|
case 18: /* CM_IRQ_ENSET */
|
|
|
|
s->irq_enabled |= value;
|
|
|
|
integratorcm_update(s);
|
|
|
|
break;
|
|
|
|
case 19: /* CM_IRQ_ENCLR */
|
|
|
|
s->irq_enabled &= ~value;
|
|
|
|
integratorcm_update(s);
|
|
|
|
break;
|
|
|
|
case 20: /* CM_SOFT_INTSET */
|
|
|
|
s->int_level |= (value & 1);
|
|
|
|
integratorcm_update(s);
|
|
|
|
break;
|
|
|
|
case 21: /* CM_SOFT_INTCLR */
|
|
|
|
s->int_level &= ~(value & 1);
|
|
|
|
integratorcm_update(s);
|
|
|
|
break;
|
|
|
|
case 26: /* CM_FIQ_ENSET */
|
|
|
|
s->fiq_enabled |= value;
|
|
|
|
integratorcm_update(s);
|
|
|
|
break;
|
|
|
|
case 27: /* CM_FIQ_ENCLR */
|
|
|
|
s->fiq_enabled &= ~value;
|
|
|
|
integratorcm_update(s);
|
|
|
|
break;
|
|
|
|
case 32: /* CM_VOLTAGE_CTL0 */
|
|
|
|
case 33: /* CM_VOLTAGE_CTL1 */
|
|
|
|
case 34: /* CM_VOLTAGE_CTL2 */
|
|
|
|
case 35: /* CM_VOLTAGE_CTL3 */
|
|
|
|
/* ??? Voltage control unimplemented. */
|
|
|
|
break;
|
|
|
|
default:
|
2020-05-18 17:03:06 +03:00
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
|
|
|
|
__func__, offset);
|
2005-11-26 13:38:39 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Integrator/CM control registers. */
|
|
|
|
|
2011-10-17 19:28:26 +04:00
|
|
|
static const MemoryRegionOps integratorcm_ops = {
|
|
|
|
.read = integratorcm_read,
|
|
|
|
.write = integratorcm_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2005-11-26 13:38:39 +03:00
|
|
|
};
|
|
|
|
|
2016-03-07 10:05:44 +03:00
|
|
|
static void integratorcm_init(Object *obj)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
2016-03-07 10:05:44 +03:00
|
|
|
IntegratorCMState *s = INTEGRATOR_CM(obj);
|
2005-11-26 13:38:39 +03:00
|
|
|
|
|
|
|
s->cm_osc = 0x01000048;
|
|
|
|
/* ??? What should the high bits of this value be? */
|
|
|
|
s->cm_auxosc = 0x0007feff;
|
|
|
|
s->cm_sdram = 0x00011122;
|
2016-10-04 15:28:08 +03:00
|
|
|
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
|
|
|
|
s->cm_init = 0x00000112;
|
|
|
|
s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
|
|
|
|
1000);
|
|
|
|
|
|
|
|
/* ??? Save/restore. */
|
|
|
|
}
|
|
|
|
|
|
|
|
static void integratorcm_realize(DeviceState *d, Error **errp)
|
|
|
|
{
|
|
|
|
IntegratorCMState *s = INTEGRATOR_CM(d);
|
2018-04-10 15:02:24 +03:00
|
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(d);
|
|
|
|
Error *local_err = NULL;
|
|
|
|
|
|
|
|
memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000,
|
|
|
|
&local_err);
|
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s,
|
|
|
|
"integratorcm", 0x00800000);
|
|
|
|
sysbus_init_mmio(dev, &s->iomem);
|
|
|
|
|
|
|
|
integratorcm_do_remap(s);
|
2016-10-04 15:28:08 +03:00
|
|
|
|
2009-07-15 15:43:31 +04:00
|
|
|
if (s->memsz >= 256) {
|
2005-11-26 13:38:39 +03:00
|
|
|
integrator_spd[31] = 64;
|
|
|
|
s->cm_sdram |= 0x10;
|
2009-07-15 15:43:31 +04:00
|
|
|
} else if (s->memsz >= 128) {
|
2005-11-26 13:38:39 +03:00
|
|
|
integrator_spd[31] = 32;
|
|
|
|
s->cm_sdram |= 0x0c;
|
2009-07-15 15:43:31 +04:00
|
|
|
} else if (s->memsz >= 64) {
|
2005-11-26 13:38:39 +03:00
|
|
|
integrator_spd[31] = 16;
|
|
|
|
s->cm_sdram |= 0x08;
|
2009-07-15 15:43:31 +04:00
|
|
|
} else if (s->memsz >= 32) {
|
2005-11-26 13:38:39 +03:00
|
|
|
integrator_spd[31] = 4;
|
|
|
|
s->cm_sdram |= 0x04;
|
|
|
|
} else {
|
|
|
|
integrator_spd[31] = 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Integrator/CP hardware emulation. */
|
|
|
|
/* Primary interrupt controller. */
|
|
|
|
|
2013-07-24 03:08:01 +04:00
|
|
|
#define TYPE_INTEGRATOR_PIC "integrator_pic"
|
2020-09-16 21:25:19 +03:00
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(icp_pic_state, INTEGRATOR_PIC)
|
2013-07-24 03:08:01 +04:00
|
|
|
|
2020-09-03 23:43:22 +03:00
|
|
|
struct icp_pic_state {
|
2013-07-24 03:08:01 +04:00
|
|
|
/*< private >*/
|
|
|
|
SysBusDevice parent_obj;
|
|
|
|
/*< public >*/
|
|
|
|
|
|
|
|
MemoryRegion iomem;
|
|
|
|
uint32_t level;
|
|
|
|
uint32_t irq_enabled;
|
|
|
|
uint32_t fiq_enabled;
|
|
|
|
qemu_irq parent_irq;
|
|
|
|
qemu_irq parent_fiq;
|
2020-09-03 23:43:22 +03:00
|
|
|
};
|
2005-11-26 13:38:39 +03:00
|
|
|
|
2017-02-07 21:29:58 +03:00
|
|
|
static const VMStateDescription vmstate_icp_pic = {
|
|
|
|
.name = "icp_pic",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32(level, icp_pic_state),
|
|
|
|
VMSTATE_UINT32(irq_enabled, icp_pic_state),
|
|
|
|
VMSTATE_UINT32(fiq_enabled, icp_pic_state),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2005-11-26 13:38:39 +03:00
|
|
|
static void icp_pic_update(icp_pic_state *s)
|
|
|
|
{
|
2006-04-09 05:32:52 +04:00
|
|
|
uint32_t flags;
|
2005-11-26 13:38:39 +03:00
|
|
|
|
2007-04-07 22:14:41 +04:00
|
|
|
flags = (s->level & s->irq_enabled);
|
|
|
|
qemu_set_irq(s->parent_irq, flags != 0);
|
|
|
|
flags = (s->level & s->fiq_enabled);
|
|
|
|
qemu_set_irq(s->parent_fiq, flags != 0);
|
2005-11-26 13:38:39 +03:00
|
|
|
}
|
|
|
|
|
2006-04-09 05:32:52 +04:00
|
|
|
static void icp_pic_set_irq(void *opaque, int irq, int level)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
2005-12-04 21:54:21 +03:00
|
|
|
icp_pic_state *s = (icp_pic_state *)opaque;
|
2005-11-26 13:38:39 +03:00
|
|
|
if (level)
|
2005-12-04 21:54:21 +03:00
|
|
|
s->level |= 1 << irq;
|
2005-11-26 13:38:39 +03:00
|
|
|
else
|
2005-12-04 21:54:21 +03:00
|
|
|
s->level &= ~(1 << irq);
|
2005-11-26 13:38:39 +03:00
|
|
|
icp_pic_update(s);
|
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint64_t icp_pic_read(void *opaque, hwaddr offset,
|
2011-10-17 19:28:27 +04:00
|
|
|
unsigned size)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
|
|
|
icp_pic_state *s = (icp_pic_state *)opaque;
|
|
|
|
|
|
|
|
switch (offset >> 2) {
|
|
|
|
case 0: /* IRQ_STATUS */
|
|
|
|
return s->level & s->irq_enabled;
|
|
|
|
case 1: /* IRQ_RAWSTAT */
|
|
|
|
return s->level;
|
|
|
|
case 2: /* IRQ_ENABLESET */
|
|
|
|
return s->irq_enabled;
|
|
|
|
case 4: /* INT_SOFTSET */
|
|
|
|
return s->level & 1;
|
|
|
|
case 8: /* FRQ_STATUS */
|
|
|
|
return s->level & s->fiq_enabled;
|
|
|
|
case 9: /* FRQ_RAWSTAT */
|
|
|
|
return s->level;
|
|
|
|
case 10: /* FRQ_ENABLESET */
|
|
|
|
return s->fiq_enabled;
|
|
|
|
case 3: /* IRQ_ENABLECLR */
|
|
|
|
case 5: /* INT_SOFTCLR */
|
|
|
|
case 11: /* FRQ_ENABLECLR */
|
|
|
|
default:
|
2020-05-18 17:03:06 +03:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
|
|
|
|
__func__, offset);
|
2005-11-26 13:38:39 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static void icp_pic_write(void *opaque, hwaddr offset,
|
2011-10-17 19:28:27 +04:00
|
|
|
uint64_t value, unsigned size)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
|
|
|
icp_pic_state *s = (icp_pic_state *)opaque;
|
|
|
|
|
|
|
|
switch (offset >> 2) {
|
|
|
|
case 2: /* IRQ_ENABLESET */
|
|
|
|
s->irq_enabled |= value;
|
|
|
|
break;
|
|
|
|
case 3: /* IRQ_ENABLECLR */
|
|
|
|
s->irq_enabled &= ~value;
|
|
|
|
break;
|
|
|
|
case 4: /* INT_SOFTSET */
|
|
|
|
if (value & 1)
|
2007-04-07 22:14:41 +04:00
|
|
|
icp_pic_set_irq(s, 0, 1);
|
2005-11-26 13:38:39 +03:00
|
|
|
break;
|
|
|
|
case 5: /* INT_SOFTCLR */
|
|
|
|
if (value & 1)
|
2007-04-07 22:14:41 +04:00
|
|
|
icp_pic_set_irq(s, 0, 0);
|
2005-11-26 13:38:39 +03:00
|
|
|
break;
|
|
|
|
case 10: /* FRQ_ENABLESET */
|
|
|
|
s->fiq_enabled |= value;
|
|
|
|
break;
|
|
|
|
case 11: /* FRQ_ENABLECLR */
|
|
|
|
s->fiq_enabled &= ~value;
|
|
|
|
break;
|
|
|
|
case 0: /* IRQ_STATUS */
|
|
|
|
case 1: /* IRQ_RAWSTAT */
|
|
|
|
case 8: /* FRQ_STATUS */
|
|
|
|
case 9: /* FRQ_RAWSTAT */
|
|
|
|
default:
|
2020-05-18 17:03:06 +03:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
|
|
|
|
__func__, offset);
|
2005-11-26 13:38:39 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
icp_pic_update(s);
|
|
|
|
}
|
|
|
|
|
2011-10-17 19:28:27 +04:00
|
|
|
static const MemoryRegionOps icp_pic_ops = {
|
|
|
|
.read = icp_pic_read,
|
|
|
|
.write = icp_pic_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2005-11-26 13:38:39 +03:00
|
|
|
};
|
|
|
|
|
2016-03-07 10:05:44 +03:00
|
|
|
static void icp_pic_init(Object *obj)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
2016-03-07 10:05:44 +03:00
|
|
|
DeviceState *dev = DEVICE(obj);
|
|
|
|
icp_pic_state *s = INTEGRATOR_PIC(obj);
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
2005-11-26 13:38:39 +03:00
|
|
|
|
2013-07-24 03:08:01 +04:00
|
|
|
qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
|
|
|
|
sysbus_init_irq(sbd, &s->parent_irq);
|
|
|
|
sysbus_init_irq(sbd, &s->parent_fiq);
|
2016-03-07 10:05:44 +03:00
|
|
|
memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s,
|
2013-06-07 05:25:08 +04:00
|
|
|
"icp-pic", 0x00800000);
|
2013-07-24 03:08:01 +04:00
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
2005-11-26 13:38:39 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* CP control registers. */
|
2011-10-17 19:28:28 +04:00
|
|
|
|
2015-03-11 16:21:06 +03:00
|
|
|
#define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
|
2020-09-16 21:25:19 +03:00
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(ICPCtrlRegsState, ICP_CONTROL_REGS)
|
2015-03-11 16:21:06 +03:00
|
|
|
|
2020-09-03 23:43:22 +03:00
|
|
|
struct ICPCtrlRegsState {
|
2015-03-11 16:21:06 +03:00
|
|
|
/*< private >*/
|
|
|
|
SysBusDevice parent_obj;
|
|
|
|
/*< public >*/
|
|
|
|
|
|
|
|
MemoryRegion iomem;
|
2015-03-11 16:21:06 +03:00
|
|
|
|
|
|
|
qemu_irq mmc_irq;
|
|
|
|
uint32_t intreg_state;
|
2020-09-03 23:43:22 +03:00
|
|
|
};
|
2015-03-11 16:21:06 +03:00
|
|
|
|
2015-03-11 16:21:06 +03:00
|
|
|
#define ICP_GPIO_MMC_WPROT "mmc-wprot"
|
|
|
|
#define ICP_GPIO_MMC_CARDIN "mmc-cardin"
|
|
|
|
|
|
|
|
#define ICP_INTREG_WPROT (1 << 0)
|
|
|
|
#define ICP_INTREG_CARDIN (1 << 3)
|
|
|
|
|
2017-02-07 21:29:58 +03:00
|
|
|
static const VMStateDescription vmstate_icp_control = {
|
|
|
|
.name = "icp_control",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint64_t icp_control_read(void *opaque, hwaddr offset,
|
2011-10-17 19:28:28 +04:00
|
|
|
unsigned size)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
2015-03-11 16:21:06 +03:00
|
|
|
ICPCtrlRegsState *s = opaque;
|
|
|
|
|
2005-11-26 13:38:39 +03:00
|
|
|
switch (offset >> 2) {
|
|
|
|
case 0: /* CP_IDFIELD */
|
|
|
|
return 0x41034003;
|
|
|
|
case 1: /* CP_FLASHPROG */
|
|
|
|
return 0;
|
|
|
|
case 2: /* CP_INTREG */
|
2015-03-11 16:21:06 +03:00
|
|
|
return s->intreg_state;
|
2005-11-26 13:38:39 +03:00
|
|
|
case 3: /* CP_DECODE */
|
|
|
|
return 0x11;
|
|
|
|
default:
|
2020-05-18 17:03:06 +03:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
|
|
|
|
__func__, offset);
|
2005-11-26 13:38:39 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static void icp_control_write(void *opaque, hwaddr offset,
|
2011-10-17 19:28:28 +04:00
|
|
|
uint64_t value, unsigned size)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
2015-03-11 16:21:06 +03:00
|
|
|
ICPCtrlRegsState *s = opaque;
|
|
|
|
|
2005-11-26 13:38:39 +03:00
|
|
|
switch (offset >> 2) {
|
|
|
|
case 2: /* CP_INTREG */
|
2015-03-11 16:21:06 +03:00
|
|
|
s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
|
|
|
|
qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
|
|
|
|
break;
|
|
|
|
case 1: /* CP_FLASHPROG */
|
2005-11-26 13:38:39 +03:00
|
|
|
case 3: /* CP_DECODE */
|
|
|
|
/* Nothing interesting implemented yet. */
|
|
|
|
break;
|
|
|
|
default:
|
2020-05-18 17:03:06 +03:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
|
|
|
|
__func__, offset);
|
2005-11-26 13:38:39 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-10-17 19:28:28 +04:00
|
|
|
static const MemoryRegionOps icp_control_ops = {
|
|
|
|
.read = icp_control_read,
|
|
|
|
.write = icp_control_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2005-11-26 13:38:39 +03:00
|
|
|
};
|
|
|
|
|
2015-03-11 16:21:06 +03:00
|
|
|
static void icp_control_mmc_wprot(void *opaque, int line, int level)
|
|
|
|
{
|
|
|
|
ICPCtrlRegsState *s = opaque;
|
|
|
|
|
|
|
|
s->intreg_state &= ~ICP_INTREG_WPROT;
|
|
|
|
if (level) {
|
|
|
|
s->intreg_state |= ICP_INTREG_WPROT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void icp_control_mmc_cardin(void *opaque, int line, int level)
|
|
|
|
{
|
|
|
|
ICPCtrlRegsState *s = opaque;
|
|
|
|
|
|
|
|
/* line is released by writing to CP_INTREG */
|
|
|
|
if (level) {
|
|
|
|
s->intreg_state |= ICP_INTREG_CARDIN;
|
|
|
|
qemu_set_irq(s->mmc_irq, 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-03-11 16:21:06 +03:00
|
|
|
static void icp_control_init(Object *obj)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
2015-03-11 16:21:06 +03:00
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
|
2015-03-11 16:21:06 +03:00
|
|
|
DeviceState *dev = DEVICE(obj);
|
2005-11-26 13:38:39 +03:00
|
|
|
|
2015-03-11 16:21:06 +03:00
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
|
|
|
|
"icp_ctrl_regs", 0x00800000);
|
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
2015-03-11 16:21:06 +03:00
|
|
|
|
|
|
|
qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
|
|
|
|
qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
|
|
|
|
ICP_GPIO_MMC_CARDIN, 1);
|
|
|
|
sysbus_init_irq(sbd, &s->mmc_irq);
|
2005-11-26 13:38:39 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Board init. */
|
|
|
|
|
2008-04-15 00:27:51 +04:00
|
|
|
static struct arm_boot_info integrator_binfo = {
|
|
|
|
.loader_start = 0x0,
|
|
|
|
.board_id = 0x113,
|
|
|
|
};
|
|
|
|
|
2014-05-07 18:42:57 +04:00
|
|
|
static void integratorcp_init(MachineState *machine)
|
2005-11-26 13:38:39 +03:00
|
|
|
{
|
2014-05-07 18:42:57 +04:00
|
|
|
ram_addr_t ram_size = machine->ram_size;
|
2014-12-16 02:09:50 +03:00
|
|
|
Object *cpuobj;
|
2012-05-14 03:51:01 +04:00
|
|
|
ARMCPU *cpu;
|
2011-07-25 16:03:19 +04:00
|
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
|
|
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
|
2009-05-15 01:35:07 +04:00
|
|
|
qemu_irq pic[32];
|
2015-03-11 16:21:06 +03:00
|
|
|
DeviceState *dev, *sic, *icp;
|
2020-07-05 15:24:24 +03:00
|
|
|
DriveInfo *dinfo;
|
2009-05-15 01:35:07 +04:00
|
|
|
int i;
|
2005-11-26 13:38:39 +03:00
|
|
|
|
2017-09-13 19:04:57 +03:00
|
|
|
cpuobj = object_new(machine->cpu_type);
|
2014-12-16 02:09:50 +03:00
|
|
|
|
2014-12-16 02:09:51 +03:00
|
|
|
/* By default ARM1176 CPUs have EL3 enabled. This board does not
|
|
|
|
* currently support EL3 so the CPU EL3 property is disabled before
|
|
|
|
* realization.
|
|
|
|
*/
|
2020-09-14 16:56:17 +03:00
|
|
|
if (object_property_find(cpuobj, "has_el3")) {
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 19:05:54 +03:00
|
|
|
object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
|
2014-12-16 02:09:51 +03:00
|
|
|
}
|
|
|
|
|
qdev: Convert bus-less devices to qdev_realize() with Coccinelle
All remaining conversions to qdev_realize() are for bus-less devices.
Coccinelle script:
// only correct for bus-less @dev!
@@
expression errp;
expression dev;
@@
- qdev_init_nofail(dev);
+ qdev_realize(dev, NULL, &error_fatal);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(dev, true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
2020-06-10 08:32:45 +03:00
|
|
|
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
|
2014-12-16 02:09:50 +03:00
|
|
|
|
|
|
|
cpu = ARM_CPU(cpuobj);
|
|
|
|
|
2005-11-26 13:38:39 +03:00
|
|
|
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
|
2008-06-03 23:51:57 +04:00
|
|
|
/* ??? RAM should repeat to fill physical memory space. */
|
2005-11-26 13:38:39 +03:00
|
|
|
/* SDRAM at address zero*/
|
2020-02-19 19:08:51 +03:00
|
|
|
memory_region_add_subregion(address_space_mem, 0, machine->ram);
|
2005-11-26 13:38:39 +03:00
|
|
|
/* And again at address 0x80000000 */
|
2020-02-19 19:08:51 +03:00
|
|
|
memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram,
|
|
|
|
0, ram_size);
|
2011-07-25 16:03:19 +04:00
|
|
|
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
|
2005-11-26 13:38:39 +03:00
|
|
|
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:31:58 +03:00
|
|
|
dev = qdev_new(TYPE_INTEGRATOR_CM);
|
2009-07-15 15:43:31 +04:00
|
|
|
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:32:34 +03:00
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
2009-05-15 01:35:07 +04:00
|
|
|
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
|
|
|
|
|
2013-07-24 03:08:01 +04:00
|
|
|
dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
|
2013-08-20 17:54:29 +04:00
|
|
|
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
|
|
|
|
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
|
|
|
|
NULL);
|
2009-05-15 01:35:07 +04:00
|
|
|
for (i = 0; i < 32; i++) {
|
2009-05-26 17:56:11 +04:00
|
|
|
pic[i] = qdev_get_gpio_in(dev, i);
|
2009-05-15 01:35:07 +04:00
|
|
|
}
|
2015-03-11 16:21:06 +03:00
|
|
|
sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
|
2009-05-15 01:35:07 +04:00
|
|
|
sysbus_create_varargs("integrator_pit", 0x13000000,
|
|
|
|
pic[5], pic[6], pic[7], NULL);
|
2009-05-15 01:35:07 +04:00
|
|
|
sysbus_create_simple("pl031", 0x15000000, pic[8]);
|
2018-04-20 17:52:43 +03:00
|
|
|
pl011_create(0x16000000, pic[1], serial_hd(0));
|
|
|
|
pl011_create(0x17000000, pic[2], serial_hd(1));
|
2015-03-11 16:21:06 +03:00
|
|
|
icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
|
|
|
|
qdev_get_gpio_in(sic, 3));
|
2009-05-15 01:35:07 +04:00
|
|
|
sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
|
|
|
|
sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
|
2013-10-22 18:16:06 +04:00
|
|
|
sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
|
2015-03-11 16:21:06 +03:00
|
|
|
|
|
|
|
dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
|
2020-07-05 14:39:53 +03:00
|
|
|
qdev_connect_gpio_out_named(dev, "card-read-only", 0,
|
2015-03-11 16:21:06 +03:00
|
|
|
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
|
2020-07-05 14:39:53 +03:00
|
|
|
qdev_connect_gpio_out_named(dev, "card-inserted", 0,
|
2015-03-11 16:21:06 +03:00
|
|
|
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
|
2021-11-17 19:33:58 +03:00
|
|
|
dinfo = drive_get(IF_SD, 0, 0);
|
2020-07-05 15:24:24 +03:00
|
|
|
if (dinfo) {
|
|
|
|
DeviceState *card;
|
|
|
|
|
|
|
|
card = qdev_new(TYPE_SD_CARD);
|
|
|
|
qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
|
|
|
|
&error_fatal);
|
|
|
|
qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
|
|
|
|
&error_fatal);
|
|
|
|
}
|
|
|
|
|
2023-09-22 18:21:39 +03:00
|
|
|
dev = qdev_new("pl041");
|
|
|
|
if (machine->audiodev) {
|
|
|
|
qdev_prop_set_string(dev, "audiodev", machine->audiodev);
|
|
|
|
}
|
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x1d000000);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[25]);
|
2015-03-11 16:21:06 +03:00
|
|
|
|
2012-07-24 19:35:11 +04:00
|
|
|
if (nd_table[0].used)
|
2009-01-13 22:39:36 +03:00
|
|
|
smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
|
2009-05-15 01:35:07 +04:00
|
|
|
|
|
|
|
sysbus_create_simple("pl110", 0xc0000000, pic[22]);
|
2005-11-26 13:38:39 +03:00
|
|
|
|
2008-04-15 00:27:51 +04:00
|
|
|
integrator_binfo.ram_size = ram_size;
|
2019-08-09 09:57:21 +03:00
|
|
|
arm_load_kernel(cpu, machine, &integrator_binfo);
|
2005-11-26 13:38:39 +03:00
|
|
|
}
|
|
|
|
|
2015-09-04 21:37:08 +03:00
|
|
|
static void integratorcp_machine_init(MachineClass *mc)
|
2009-05-21 03:38:09 +04:00
|
|
|
{
|
2015-09-04 21:37:08 +03:00
|
|
|
mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
|
|
|
|
mc->init = integratorcp_init;
|
2017-09-07 15:54:54 +03:00
|
|
|
mc->ignore_memory_transaction_failures = true;
|
2017-09-13 19:04:57 +03:00
|
|
|
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
|
2020-02-19 19:08:51 +03:00
|
|
|
mc->default_ram_id = "integrator.ram";
|
2023-09-22 18:21:39 +03:00
|
|
|
|
|
|
|
machine_add_audiodev_property(mc);
|
2009-05-21 03:38:09 +04:00
|
|
|
}
|
|
|
|
|
2015-09-04 21:37:08 +03:00
|
|
|
DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
|
2009-05-21 03:38:09 +04:00
|
|
|
|
2012-01-24 23:12:29 +04:00
|
|
|
static Property core_properties[] = {
|
2013-07-24 03:00:27 +04:00
|
|
|
DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
|
2012-01-24 23:12:29 +04:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void core_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 23:12:29 +04:00
|
|
|
|
2020-01-10 18:30:32 +03:00
|
|
|
device_class_set_props(dc, core_properties);
|
2016-10-04 15:28:08 +03:00
|
|
|
dc->realize = integratorcm_realize;
|
2017-02-07 21:29:58 +03:00
|
|
|
dc->vmsd = &vmstate_integratorcm;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void icp_pic_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->vmsd = &vmstate_icp_pic;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void icp_control_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->vmsd = &vmstate_icp_control;
|
2012-01-24 23:12:29 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo core_info = {
|
2013-07-24 03:00:27 +04:00
|
|
|
.name = TYPE_INTEGRATOR_CM,
|
2011-12-08 07:34:16 +04:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
2013-07-24 03:00:27 +04:00
|
|
|
.instance_size = sizeof(IntegratorCMState),
|
2016-03-07 10:05:44 +03:00
|
|
|
.instance_init = integratorcm_init,
|
2011-12-08 07:34:16 +04:00
|
|
|
.class_init = core_class_init,
|
2012-01-24 23:12:29 +04:00
|
|
|
};
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo icp_pic_info = {
|
2013-07-24 03:08:01 +04:00
|
|
|
.name = TYPE_INTEGRATOR_PIC,
|
2011-12-08 07:34:16 +04:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(icp_pic_state),
|
2016-03-07 10:05:44 +03:00
|
|
|
.instance_init = icp_pic_init,
|
2017-02-07 21:29:58 +03:00
|
|
|
.class_init = icp_pic_class_init,
|
2009-07-15 15:43:31 +04:00
|
|
|
};
|
|
|
|
|
2015-03-11 16:21:06 +03:00
|
|
|
static const TypeInfo icp_ctrl_regs_info = {
|
|
|
|
.name = TYPE_ICP_CONTROL_REGS,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(ICPCtrlRegsState),
|
|
|
|
.instance_init = icp_control_init,
|
2017-02-07 21:29:58 +03:00
|
|
|
.class_init = icp_control_class_init,
|
2015-03-11 16:21:06 +03:00
|
|
|
};
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
static void integratorcp_register_types(void)
|
2009-05-15 01:35:07 +04:00
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&icp_pic_info);
|
|
|
|
type_register_static(&core_info);
|
2015-03-11 16:21:06 +03:00
|
|
|
type_register_static(&icp_ctrl_regs_info);
|
2009-05-15 01:35:07 +04:00
|
|
|
}
|
|
|
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2012-02-09 18:20:55 +04:00
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type_init(integratorcp_register_types)
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