2021-02-08 08:46:17 +03:00
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/*
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2023-03-07 05:58:15 +03:00
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* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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2021-02-08 08:46:17 +03:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_GEN_TCG_H
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#define HEXAGON_GEN_TCG_H
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/*
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* Here is a primer to understand the tag names for load/store instructions
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*
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* Data types
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* b signed byte r0 = memb(r2+#0)
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* ub unsigned byte r0 = memub(r2+#0)
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* h signed half word (16 bits) r0 = memh(r2+#0)
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* uh unsigned half word r0 = memuh(r2+#0)
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* i integer (32 bits) r0 = memw(r2+#0)
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* d double word (64 bits) r1:0 = memd(r2+#0)
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*
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* Addressing modes
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* _io indirect with offset r0 = memw(r1+#4)
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* _ur absolute with register offset r0 = memw(r1<<#4+##variable)
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* _rr indirect with register offset r0 = memw(r1+r4<<#2)
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* gp global pointer relative r0 = memw(gp+#200)
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* _sp stack pointer relative r0 = memw(r29+#12)
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* _ap absolute set r0 = memw(r1=##variable)
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* _pr post increment register r0 = memw(r1++m1)
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2021-04-09 04:07:51 +03:00
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* _pbr post increment bit reverse r0 = memw(r1++m1:brev)
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2021-02-08 08:46:17 +03:00
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* _pi post increment immediate r0 = memb(r1++#1)
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2021-04-09 04:07:50 +03:00
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* _pci post increment circular immediate r0 = memw(r1++#4:circ(m0))
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* _pcr post increment circular register r0 = memw(r1++I:circ(m0))
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2021-02-08 08:46:17 +03:00
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*/
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/* Macros for complex addressing modes */
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#define GET_EA_ap \
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do { \
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fEA_IMM(UiV); \
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tcg_gen_movi_tl(ReV, UiV); \
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} while (0)
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#define GET_EA_pr \
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do { \
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fEA_REG(RxV); \
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fPM_M(RxV, MuV); \
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} while (0)
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2021-04-09 04:07:51 +03:00
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#define GET_EA_pbr \
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do { \
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gen_helper_fbrev(EA, RxV); \
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tcg_gen_add_tl(RxV, RxV, MuV); \
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} while (0)
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2021-02-08 08:46:17 +03:00
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#define GET_EA_pi \
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do { \
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fEA_REG(RxV); \
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fPM_I(RxV, siV); \
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} while (0)
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2021-04-09 04:07:50 +03:00
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#define GET_EA_pci \
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do { \
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2021-10-11 19:48:52 +03:00
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TCGv tcgv_siV = tcg_constant_tl(siV); \
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2021-04-09 04:07:50 +03:00
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tcg_gen_mov_tl(EA, RxV); \
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gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \
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hex_gpr[HEX_REG_CS0 + MuN]); \
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} while (0)
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#define GET_EA_pcr(SHIFT) \
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do { \
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TCGv ireg = tcg_temp_new(); \
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tcg_gen_mov_tl(EA, RxV); \
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gen_read_ireg(ireg, MuV, (SHIFT)); \
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gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
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} while (0)
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2021-02-08 08:46:17 +03:00
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/* Instructions with multiple definitions */
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#define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \
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do { \
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fMUST_IMMEXT(UiV); \
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fEA_IMM(UiV); \
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fLOAD(1, SIZE, SIGN, EA, RES); \
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tcg_gen_movi_tl(ReV, UiV); \
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} while (0)
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#define fGEN_TCG_L4_loadrub_ap(SHORTCODE) \
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fGEN_TCG_LOAD_AP(RdV, 1, u)
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#define fGEN_TCG_L4_loadrb_ap(SHORTCODE) \
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fGEN_TCG_LOAD_AP(RdV, 1, s)
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#define fGEN_TCG_L4_loadruh_ap(SHORTCODE) \
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fGEN_TCG_LOAD_AP(RdV, 2, u)
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#define fGEN_TCG_L4_loadrh_ap(SHORTCODE) \
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fGEN_TCG_LOAD_AP(RdV, 2, s)
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#define fGEN_TCG_L4_loadri_ap(SHORTCODE) \
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fGEN_TCG_LOAD_AP(RdV, 4, u)
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#define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \
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fGEN_TCG_LOAD_AP(RddV, 8, u)
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2021-04-09 04:07:50 +03:00
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#define fGEN_TCG_L2_loadrub_pci(SHORTCODE) SHORTCODE
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#define fGEN_TCG_L2_loadrb_pci(SHORTCODE) SHORTCODE
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#define fGEN_TCG_L2_loadruh_pci(SHORTCODE) SHORTCODE
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#define fGEN_TCG_L2_loadrh_pci(SHORTCODE) SHORTCODE
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#define fGEN_TCG_L2_loadri_pci(SHORTCODE) SHORTCODE
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#define fGEN_TCG_L2_loadrd_pci(SHORTCODE) SHORTCODE
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#define fGEN_TCG_LOAD_pcr(SHIFT, LOAD) \
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do { \
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TCGv ireg = tcg_temp_new(); \
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tcg_gen_mov_tl(EA, RxV); \
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gen_read_ireg(ireg, MuV, SHIFT); \
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gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
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LOAD; \
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} while (0)
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#define fGEN_TCG_L2_loadrub_pcr(SHORTCODE) \
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fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, u, EA, RdV))
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#define fGEN_TCG_L2_loadrb_pcr(SHORTCODE) \
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fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, s, EA, RdV))
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#define fGEN_TCG_L2_loadruh_pcr(SHORTCODE) \
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fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, u, EA, RdV))
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#define fGEN_TCG_L2_loadrh_pcr(SHORTCODE) \
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fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, s, EA, RdV))
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#define fGEN_TCG_L2_loadri_pcr(SHORTCODE) \
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fGEN_TCG_LOAD_pcr(2, fLOAD(1, 4, u, EA, RdV))
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#define fGEN_TCG_L2_loadrd_pcr(SHORTCODE) \
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fGEN_TCG_LOAD_pcr(3, fLOAD(1, 8, u, EA, RddV))
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2021-02-08 08:46:17 +03:00
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#define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE
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2021-04-09 04:07:51 +03:00
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#define fGEN_TCG_L2_loadrub_pbr(SHORTCODE) SHORTCODE
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2021-02-08 08:46:17 +03:00
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#define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE
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2021-04-09 04:07:51 +03:00
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#define fGEN_TCG_L2_loadrb_pbr(SHORTCODE) SHORTCODE
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2021-03-15 07:55:00 +03:00
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#define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE
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2021-02-08 08:46:17 +03:00
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#define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE
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2021-04-09 04:07:51 +03:00
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#define fGEN_TCG_L2_loadruh_pbr(SHORTCODE) SHORTCODE
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2021-03-15 07:55:00 +03:00
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#define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE
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2021-02-08 08:46:17 +03:00
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#define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE
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2021-04-09 04:07:51 +03:00
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#define fGEN_TCG_L2_loadrh_pbr(SHORTCODE) SHORTCODE
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2021-02-08 08:46:17 +03:00
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#define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE
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2021-04-09 04:07:51 +03:00
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#define fGEN_TCG_L2_loadri_pbr(SHORTCODE) SHORTCODE
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2021-02-08 08:46:17 +03:00
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#define fGEN_TCG_L2_loadri_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_L2_loadrd_pr(SHORTCODE) SHORTCODE
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2021-04-09 04:07:51 +03:00
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#define fGEN_TCG_L2_loadrd_pbr(SHORTCODE) SHORTCODE
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2021-02-08 08:46:17 +03:00
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#define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE
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2021-04-09 04:07:52 +03:00
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/*
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* These instructions load 2 bytes and places them in
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* two halves of the destination register.
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* The GET_EA macro determines the addressing mode.
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* The SIGN argument determines whether to zero-extend or
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* sign-extend.
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*/
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#define fGEN_TCG_loadbXw2(GET_EA, SIGN) \
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do { \
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TCGv tmp = tcg_temp_new(); \
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TCGv byte = tcg_temp_new(); \
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GET_EA; \
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fLOAD(1, 2, u, EA, tmp); \
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tcg_gen_movi_tl(RdV, 0); \
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for (int i = 0; i < 2; i++) { \
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gen_set_half(i, RdV, gen_get_byte(byte, i, tmp, (SIGN))); \
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} \
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} while (0)
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#define fGEN_TCG_L2_loadbzw2_io(SHORTCODE) \
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fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), false)
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#define fGEN_TCG_L4_loadbzw2_ur(SHORTCODE) \
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fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), false)
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#define fGEN_TCG_L2_loadbsw2_io(SHORTCODE) \
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fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), true)
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#define fGEN_TCG_L4_loadbsw2_ur(SHORTCODE) \
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fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), true)
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#define fGEN_TCG_L4_loadbzw2_ap(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_ap, false)
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#define fGEN_TCG_L2_loadbzw2_pr(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_pr, false)
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#define fGEN_TCG_L2_loadbzw2_pbr(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_pbr, false)
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#define fGEN_TCG_L2_loadbzw2_pi(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_pi, false)
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#define fGEN_TCG_L4_loadbsw2_ap(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_ap, true)
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#define fGEN_TCG_L2_loadbsw2_pr(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_pr, true)
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#define fGEN_TCG_L2_loadbsw2_pbr(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_pbr, true)
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#define fGEN_TCG_L2_loadbsw2_pi(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_pi, true)
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#define fGEN_TCG_L2_loadbzw2_pci(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_pci, false)
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#define fGEN_TCG_L2_loadbsw2_pci(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_pci, true)
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#define fGEN_TCG_L2_loadbzw2_pcr(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_pcr(1), false)
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#define fGEN_TCG_L2_loadbsw2_pcr(SHORTCODE) \
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fGEN_TCG_loadbXw2(GET_EA_pcr(1), true)
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/*
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* These instructions load 4 bytes and places them in
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* four halves of the destination register pair.
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* The GET_EA macro determines the addressing mode.
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* The SIGN argument determines whether to zero-extend or
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* sign-extend.
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*/
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#define fGEN_TCG_loadbXw4(GET_EA, SIGN) \
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do { \
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TCGv tmp = tcg_temp_new(); \
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TCGv byte = tcg_temp_new(); \
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GET_EA; \
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fLOAD(1, 4, u, EA, tmp); \
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tcg_gen_movi_i64(RddV, 0); \
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for (int i = 0; i < 4; i++) { \
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gen_set_half_i64(i, RddV, gen_get_byte(byte, i, tmp, (SIGN))); \
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} \
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} while (0)
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#define fGEN_TCG_L2_loadbzw4_io(SHORTCODE) \
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fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), false)
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#define fGEN_TCG_L4_loadbzw4_ur(SHORTCODE) \
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fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), false)
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#define fGEN_TCG_L2_loadbsw4_io(SHORTCODE) \
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fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), true)
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#define fGEN_TCG_L4_loadbsw4_ur(SHORTCODE) \
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fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), true)
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#define fGEN_TCG_L2_loadbzw4_pci(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pci, false)
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#define fGEN_TCG_L2_loadbsw4_pci(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pci, true)
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#define fGEN_TCG_L2_loadbzw4_pcr(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pcr(2), false)
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#define fGEN_TCG_L2_loadbsw4_pcr(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pcr(2), true)
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#define fGEN_TCG_L4_loadbzw4_ap(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_ap, false)
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#define fGEN_TCG_L2_loadbzw4_pr(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pr, false)
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|
|
#define fGEN_TCG_L2_loadbzw4_pbr(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pbr, false)
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|
#define fGEN_TCG_L2_loadbzw4_pi(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pi, false)
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|
#define fGEN_TCG_L4_loadbsw4_ap(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_ap, true)
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|
#define fGEN_TCG_L2_loadbsw4_pr(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pr, true)
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|
#define fGEN_TCG_L2_loadbsw4_pbr(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pbr, true)
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#define fGEN_TCG_L2_loadbsw4_pi(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pi, true)
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|
|
2021-04-09 04:07:53 +03:00
|
|
|
/*
|
|
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* These instructions load a half word, shift the destination right by 16 bits
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|
* and place the loaded value in the high half word of the destination pair.
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* The GET_EA macro determines the addressing mode.
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|
*/
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|
#define fGEN_TCG_loadalignh(GET_EA) \
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do { \
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TCGv tmp = tcg_temp_new(); \
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|
TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \
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|
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GET_EA; \
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fLOAD(1, 2, u, EA, tmp); \
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tcg_gen_extu_i32_i64(tmp_i64, tmp); \
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|
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tcg_gen_shri_i64(RyyV, RyyV, 16); \
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tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 48, 16); \
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|
} while (0)
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|
|
#define fGEN_TCG_L4_loadalignh_ur(SHORTCODE) \
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fGEN_TCG_loadalignh(fEA_IRs(UiV, RtV, uiV))
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#define fGEN_TCG_L2_loadalignh_io(SHORTCODE) \
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fGEN_TCG_loadalignh(fEA_RI(RsV, siV))
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|
|
#define fGEN_TCG_L2_loadalignh_pci(SHORTCODE) \
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fGEN_TCG_loadalignh(GET_EA_pci)
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|
|
#define fGEN_TCG_L2_loadalignh_pcr(SHORTCODE) \
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|
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fGEN_TCG_loadalignh(GET_EA_pcr(1))
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|
|
#define fGEN_TCG_L4_loadalignh_ap(SHORTCODE) \
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|
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fGEN_TCG_loadalignh(GET_EA_ap)
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|
|
#define fGEN_TCG_L2_loadalignh_pr(SHORTCODE) \
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|
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fGEN_TCG_loadalignh(GET_EA_pr)
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|
|
#define fGEN_TCG_L2_loadalignh_pbr(SHORTCODE) \
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|
|
fGEN_TCG_loadalignh(GET_EA_pbr)
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|
|
#define fGEN_TCG_L2_loadalignh_pi(SHORTCODE) \
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|
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fGEN_TCG_loadalignh(GET_EA_pi)
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|
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|
|
/* Same as above, but loads a byte instead of half word */
|
|
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|
|
#define fGEN_TCG_loadalignb(GET_EA) \
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|
do { \
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|
|
TCGv tmp = tcg_temp_new(); \
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|
|
TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \
|
|
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|
|
GET_EA; \
|
|
|
|
|
fLOAD(1, 1, u, EA, tmp); \
|
|
|
|
|
tcg_gen_extu_i32_i64(tmp_i64, tmp); \
|
|
|
|
|
tcg_gen_shri_i64(RyyV, RyyV, 8); \
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|
|
|
|
tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 56, 8); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_L2_loadalignb_io(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_loadalignb(fEA_RI(RsV, siV))
|
|
|
|
|
#define fGEN_TCG_L4_loadalignb_ur(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_loadalignb(fEA_IRs(UiV, RtV, uiV))
|
|
|
|
|
#define fGEN_TCG_L2_loadalignb_pci(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_loadalignb(GET_EA_pci)
|
|
|
|
|
#define fGEN_TCG_L2_loadalignb_pcr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_loadalignb(GET_EA_pcr(0))
|
|
|
|
|
#define fGEN_TCG_L4_loadalignb_ap(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_loadalignb(GET_EA_ap)
|
|
|
|
|
#define fGEN_TCG_L2_loadalignb_pr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_loadalignb(GET_EA_pr)
|
|
|
|
|
#define fGEN_TCG_L2_loadalignb_pbr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_loadalignb(GET_EA_pbr)
|
|
|
|
|
#define fGEN_TCG_L2_loadalignb_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_loadalignb(GET_EA_pi)
|
|
|
|
|
|
2021-02-08 08:46:17 +03:00
|
|
|
/*
|
|
|
|
|
* Predicated loads
|
|
|
|
|
* Here is a primer to understand the tag names
|
|
|
|
|
*
|
|
|
|
|
* Predicate used
|
|
|
|
|
* t true "old" value if (p0) r0 = memb(r2+#0)
|
|
|
|
|
* f false "old" value if (!p0) r0 = memb(r2+#0)
|
|
|
|
|
* tnew true "new" value if (p0.new) r0 = memb(r2+#0)
|
|
|
|
|
* fnew false "new" value if (!p0.new) r0 = memb(r2+#0)
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \
|
|
|
|
|
do { \
|
2023-01-30 03:41:33 +03:00
|
|
|
TCGv LSB = tcg_temp_new(); \
|
2021-02-08 08:46:17 +03:00
|
|
|
TCGLabel *label = gen_new_label(); \
|
2022-07-08 00:05:46 +03:00
|
|
|
tcg_gen_movi_tl(EA, 0); \
|
2021-02-08 08:46:17 +03:00
|
|
|
PRED; \
|
2022-07-08 00:05:46 +03:00
|
|
|
CHECK_NOSHUF_PRED(GET_EA, SIZE, LSB); \
|
2021-02-08 08:46:17 +03:00
|
|
|
tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
|
2022-07-08 00:05:46 +03:00
|
|
|
fLOAD(1, SIZE, SIGN, EA, RdV); \
|
2021-02-08 08:46:17 +03:00
|
|
|
gen_set_label(label); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrubf_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrubtnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrubfnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 1, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrbt_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, s)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrbf_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, s)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrbtnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, s)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrbfnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD({ fEA_REG(RxV); fPM_I(RxV, siV); }, \
|
|
|
|
|
fLSBNEWNOT(PtN), 1, s)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_L2_ploadruht_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadruhf_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadruhtnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadruhfnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrht_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, s)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrhf_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, s)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrhtnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, s)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrhfnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, s)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_L2_ploadrit_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 4, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrif_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 4, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadritnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 4, u)
|
|
|
|
|
#define fGEN_TCG_L2_ploadrifnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 4, u)
|
|
|
|
|
|
|
|
|
|
/* Predicated loads into a register pair */
|
|
|
|
|
#define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \
|
|
|
|
|
do { \
|
2023-01-30 03:41:33 +03:00
|
|
|
TCGv LSB = tcg_temp_new(); \
|
2021-02-08 08:46:17 +03:00
|
|
|
TCGLabel *label = gen_new_label(); \
|
2022-07-08 00:05:46 +03:00
|
|
|
tcg_gen_movi_tl(EA, 0); \
|
2021-02-08 08:46:17 +03:00
|
|
|
PRED; \
|
2022-07-08 00:05:46 +03:00
|
|
|
CHECK_NOSHUF_PRED(GET_EA, 8, LSB); \
|
2021-02-08 08:46:17 +03:00
|
|
|
tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
|
2022-07-08 00:05:46 +03:00
|
|
|
fLOAD(1, 8, u, EA, RddV); \
|
2021-02-08 08:46:17 +03:00
|
|
|
gen_set_label(label); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLD(PtV))
|
|
|
|
|
#define fGEN_TCG_L2_ploadrdf_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLDNOT(PtV))
|
|
|
|
|
#define fGEN_TCG_L2_ploadrdtnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEW(PtN))
|
|
|
|
|
#define fGEN_TCG_L2_ploadrdfnew_pi(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEWNOT(PtN))
|
|
|
|
|
|
|
|
|
|
/* load-locked and store-locked */
|
|
|
|
|
#define fGEN_TCG_L2_loadw_locked(SHORTCODE) \
|
|
|
|
|
SHORTCODE
|
|
|
|
|
#define fGEN_TCG_L4_loadd_locked(SHORTCODE) \
|
|
|
|
|
SHORTCODE
|
|
|
|
|
#define fGEN_TCG_S2_storew_locked(SHORTCODE) \
|
2021-06-02 02:19:43 +03:00
|
|
|
SHORTCODE
|
2021-02-08 08:46:17 +03:00
|
|
|
#define fGEN_TCG_S4_stored_locked(SHORTCODE) \
|
2021-06-02 02:19:43 +03:00
|
|
|
SHORTCODE
|
2021-02-08 08:46:17 +03:00
|
|
|
|
2021-04-09 04:07:50 +03:00
|
|
|
#define fGEN_TCG_STORE(SHORTCODE) \
|
|
|
|
|
do { \
|
2023-03-06 20:25:15 +03:00
|
|
|
TCGv HALF G_GNUC_UNUSED = tcg_temp_new(); \
|
|
|
|
|
TCGv BYTE G_GNUC_UNUSED = tcg_temp_new(); \
|
2021-04-09 04:07:50 +03:00
|
|
|
SHORTCODE; \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_STORE_pcr(SHIFT, STORE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv ireg = tcg_temp_new(); \
|
2023-03-06 20:25:15 +03:00
|
|
|
TCGv HALF G_GNUC_UNUSED = tcg_temp_new(); \
|
|
|
|
|
TCGv BYTE G_GNUC_UNUSED = tcg_temp_new(); \
|
2021-04-09 04:07:50 +03:00
|
|
|
tcg_gen_mov_tl(EA, RxV); \
|
|
|
|
|
gen_read_ireg(ireg, MuV, SHIFT); \
|
|
|
|
|
gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
|
|
|
|
|
STORE; \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2021-04-09 04:07:51 +03:00
|
|
|
#define fGEN_TCG_S2_storerb_pbr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
2021-04-09 04:07:50 +03:00
|
|
|
#define fGEN_TCG_S2_storerb_pci(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
|
|
|
|
#define fGEN_TCG_S2_storerb_pcr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, RtV)))
|
|
|
|
|
|
2021-04-09 04:07:51 +03:00
|
|
|
#define fGEN_TCG_S2_storerh_pbr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
2021-04-09 04:07:50 +03:00
|
|
|
#define fGEN_TCG_S2_storerh_pci(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
|
|
|
|
#define fGEN_TCG_S2_storerh_pcr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, RtV)))
|
|
|
|
|
|
2021-04-09 04:07:51 +03:00
|
|
|
#define fGEN_TCG_S2_storerf_pbr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
2021-04-09 04:07:50 +03:00
|
|
|
#define fGEN_TCG_S2_storerf_pci(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
|
|
|
|
#define fGEN_TCG_S2_storerf_pcr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(1, RtV)))
|
|
|
|
|
|
2021-04-09 04:07:51 +03:00
|
|
|
#define fGEN_TCG_S2_storeri_pbr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
2021-04-09 04:07:50 +03:00
|
|
|
#define fGEN_TCG_S2_storeri_pci(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
|
|
|
|
#define fGEN_TCG_S2_storeri_pcr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, RtV))
|
|
|
|
|
|
2021-04-09 04:07:51 +03:00
|
|
|
#define fGEN_TCG_S2_storerd_pbr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
2021-04-09 04:07:50 +03:00
|
|
|
#define fGEN_TCG_S2_storerd_pci(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
|
|
|
|
#define fGEN_TCG_S2_storerd_pcr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE_pcr(3, fSTORE(1, 8, EA, RttV))
|
|
|
|
|
|
2021-04-09 04:07:51 +03:00
|
|
|
#define fGEN_TCG_S2_storerbnew_pbr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
2021-04-09 04:07:50 +03:00
|
|
|
#define fGEN_TCG_S2_storerbnew_pci(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
|
|
|
|
#define fGEN_TCG_S2_storerbnew_pcr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, NtN)))
|
|
|
|
|
|
2021-04-09 04:07:51 +03:00
|
|
|
#define fGEN_TCG_S2_storerhnew_pbr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
2021-04-09 04:07:50 +03:00
|
|
|
#define fGEN_TCG_S2_storerhnew_pci(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
|
|
|
|
#define fGEN_TCG_S2_storerhnew_pcr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, NtN)))
|
|
|
|
|
|
2021-04-09 04:07:51 +03:00
|
|
|
#define fGEN_TCG_S2_storerinew_pbr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
2021-04-09 04:07:50 +03:00
|
|
|
#define fGEN_TCG_S2_storerinew_pci(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE(SHORTCODE)
|
|
|
|
|
#define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \
|
|
|
|
|
fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN))
|
|
|
|
|
|
2023-04-10 19:09:41 +03:00
|
|
|
/* dczeroa clears the 32 byte cache line at the address given */
|
|
|
|
|
#define fGEN_TCG_Y2_dczeroa(SHORTCODE) SHORTCODE
|
|
|
|
|
|
|
|
|
|
/* In linux-user mode, these are not modelled, suppress compiler warning */
|
|
|
|
|
#define fGEN_TCG_Y2_dcinva(SHORTCODE) \
|
|
|
|
|
do { RsV = RsV; } while (0)
|
|
|
|
|
#define fGEN_TCG_Y2_dccleaninva(SHORTCODE) \
|
|
|
|
|
do { RsV = RsV; } while (0)
|
|
|
|
|
#define fGEN_TCG_Y2_dccleana(SHORTCODE) \
|
|
|
|
|
do { RsV = RsV; } while (0)
|
|
|
|
|
#define fGEN_TCG_Y2_icinva(SHORTCODE) \
|
|
|
|
|
do { RsV = RsV; } while (0)
|
|
|
|
|
|
2023-04-28 01:59:55 +03:00
|
|
|
/*
|
|
|
|
|
* allocframe(#uiV)
|
|
|
|
|
* RxV == r29
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_S2_allocframe(SHORTCODE) \
|
|
|
|
|
gen_allocframe(ctx, RxV, uiV)
|
|
|
|
|
|
|
|
|
|
/* sub-instruction version (no RxV, so handle it manually) */
|
|
|
|
|
#define fGEN_TCG_SS2_allocframe(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv r29 = tcg_temp_new(); \
|
|
|
|
|
tcg_gen_mov_tl(r29, hex_gpr[HEX_REG_SP]); \
|
|
|
|
|
gen_allocframe(ctx, r29, uiV); \
|
|
|
|
|
gen_log_reg_write(ctx, HEX_REG_SP, r29); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Rdd32 = deallocframe(Rs32):raw
|
|
|
|
|
* RddV == r31:30
|
|
|
|
|
* RsV == r30
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_L2_deallocframe(SHORTCODE) \
|
|
|
|
|
gen_deallocframe(ctx, RddV, RsV)
|
|
|
|
|
|
|
|
|
|
/* sub-instruction version (no RddV/RsV, so handle it manually) */
|
|
|
|
|
#define fGEN_TCG_SL2_deallocframe(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv_i64 r31_30 = tcg_temp_new_i64(); \
|
|
|
|
|
gen_deallocframe(ctx, r31_30, hex_gpr[HEX_REG_FP]); \
|
|
|
|
|
gen_log_reg_write_pair(ctx, HEX_REG_FP, r31_30); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2023-03-07 05:58:18 +03:00
|
|
|
/*
|
|
|
|
|
* dealloc_return
|
|
|
|
|
* Assembler mapped to
|
|
|
|
|
* r31:30 = dealloc_return(r30):raw
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_L4_return(SHORTCODE) \
|
|
|
|
|
gen_return(ctx, RddV, RsV)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* sub-instruction version (no RddV, so handle it manually)
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_SL2_return(SHORTCODE) \
|
|
|
|
|
do { \
|
Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
|
|
|
TCGv_i64 RddV = get_result_gpr_pair(ctx, HEX_REG_FP); \
|
2023-03-07 05:58:18 +03:00
|
|
|
gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]); \
|
2023-04-28 01:59:53 +03:00
|
|
|
gen_log_reg_write_pair(ctx, HEX_REG_FP, RddV); \
|
2023-03-07 05:58:18 +03:00
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Conditional returns follow this naming convention
|
|
|
|
|
* _t predicate true
|
|
|
|
|
* _f predicate false
|
|
|
|
|
* _tnew_pt predicate.new true predict taken
|
|
|
|
|
* _fnew_pt predicate.new false predict taken
|
|
|
|
|
* _tnew_pnt predicate.new true predict not taken
|
|
|
|
|
* _fnew_pnt predicate.new false predict not taken
|
|
|
|
|
* Predictions are not modelled in QEMU
|
|
|
|
|
*
|
|
|
|
|
* Example:
|
|
|
|
|
* if (p1) r31:30 = dealloc_return(r30):raw
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_L4_return_t(SHORTCODE) \
|
|
|
|
|
gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_EQ);
|
|
|
|
|
#define fGEN_TCG_L4_return_f(SHORTCODE) \
|
|
|
|
|
gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_NE)
|
|
|
|
|
#define fGEN_TCG_L4_return_tnew_pt(SHORTCODE) \
|
|
|
|
|
gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ)
|
|
|
|
|
#define fGEN_TCG_L4_return_fnew_pt(SHORTCODE) \
|
|
|
|
|
gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE)
|
|
|
|
|
#define fGEN_TCG_L4_return_tnew_pnt(SHORTCODE) \
|
|
|
|
|
gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ)
|
|
|
|
|
#define fGEN_TCG_L4_return_fnew_pnt(SHORTCODE) \
|
|
|
|
|
gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_SL2_return_t(SHORTCODE) \
|
|
|
|
|
gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_pred[0])
|
|
|
|
|
#define fGEN_TCG_SL2_return_f(SHORTCODE) \
|
|
|
|
|
gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_pred[0])
|
|
|
|
|
#define fGEN_TCG_SL2_return_tnew(SHORTCODE) \
|
2023-04-28 02:00:09 +03:00
|
|
|
gen_cond_return_subinsn(ctx, TCG_COND_EQ, ctx->new_pred_value[0])
|
2023-03-07 05:58:18 +03:00
|
|
|
#define fGEN_TCG_SL2_return_fnew(SHORTCODE) \
|
2023-04-28 02:00:09 +03:00
|
|
|
gen_cond_return_subinsn(ctx, TCG_COND_NE, ctx->new_pred_value[0])
|
2023-03-07 05:58:18 +03:00
|
|
|
|
2021-04-09 04:07:45 +03:00
|
|
|
/*
|
|
|
|
|
* Mathematical operations with more than one definition require
|
|
|
|
|
* special handling
|
|
|
|
|
*/
|
2021-04-09 04:07:47 +03:00
|
|
|
#define fGEN_TCG_A5_ACS(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \
|
Hexagon (target/hexagon) Short-circuit packet register writes
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->need_commit to helpers when needed.
Finally, we can early-exit from gen_reg_writes during packet commit.
There are a few instructions whose semantics write to the result before
reading all the inputs. Therefore, the idef-parser generated code is
incompatible with short-circuit. We tell idef-parser to skip them.
For debugging purposes, we add a cpu property to turn off short-circuit.
When the short-circuit property is false, we skip the analysis and force
the end-of-packet commit.
Here's a simple example of the TCG generated for
0x004000b4: 0x7800c020 { R0 = #0x1 }
BEFORE:
---- 004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
---- 004000b4
movi_i32 r0,$0x1
This patch reintroduces a use of check_for_attrib, so we remove the
G_GNUC_UNUSED added earlier in this series.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com>
2023-04-28 02:00:02 +03:00
|
|
|
gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV, \
|
|
|
|
|
tcg_constant_tl(ctx->need_commit)); \
|
2021-04-09 04:07:47 +03:00
|
|
|
} while (0)
|
2021-04-09 04:07:45 +03:00
|
|
|
|
2023-04-28 01:59:58 +03:00
|
|
|
#define fGEN_TCG_S2_cabacdecbin(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv p0 = tcg_temp_new(); \
|
|
|
|
|
gen_helper_cabacdecbin_pred(p0, RssV, RttV); \
|
|
|
|
|
gen_helper_cabacdecbin_val(RddV, RssV, RttV); \
|
|
|
|
|
gen_log_pred_write(ctx, 0, p0); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2021-04-09 04:07:45 +03:00
|
|
|
/*
|
|
|
|
|
* Approximate reciprocal
|
|
|
|
|
* r3,p1 = sfrecipa(r0, r1)
|
|
|
|
|
*
|
|
|
|
|
* The helper packs the 2 32-bit results into a 64-bit value,
|
|
|
|
|
* so unpack them into the proper results.
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_F2_sfrecipa(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv_i64 tmp = tcg_temp_new_i64(); \
|
|
|
|
|
gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \
|
|
|
|
|
tcg_gen_extrh_i64_i32(RdV, tmp); \
|
|
|
|
|
tcg_gen_extrl_i64_i32(PeV, tmp); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2021-04-09 04:07:46 +03:00
|
|
|
/*
|
|
|
|
|
* Approximation of the reciprocal square root
|
|
|
|
|
* r1,p0 = sfinvsqrta(r0)
|
|
|
|
|
*
|
|
|
|
|
* The helper packs the 2 32-bit results into a 64-bit value,
|
|
|
|
|
* so unpack them into the proper results.
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv_i64 tmp = tcg_temp_new_i64(); \
|
|
|
|
|
gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \
|
|
|
|
|
tcg_gen_extrh_i64_i32(RdV, tmp); \
|
|
|
|
|
tcg_gen_extrl_i64_i32(PeV, tmp); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2021-04-09 04:07:49 +03:00
|
|
|
/*
|
|
|
|
|
* Add or subtract with carry.
|
|
|
|
|
* Predicate register is used as an extra input and output.
|
|
|
|
|
* r5:4 = add(r1:0, r3:2, p1):carry
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_A4_addp_c(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv_i64 carry = tcg_temp_new_i64(); \
|
2021-10-11 19:48:52 +03:00
|
|
|
TCGv_i64 zero = tcg_constant_i64(0); \
|
2021-04-09 04:07:49 +03:00
|
|
|
tcg_gen_extu_i32_i64(carry, PxV); \
|
|
|
|
|
tcg_gen_andi_i64(carry, carry, 1); \
|
|
|
|
|
tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
|
|
|
|
|
tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \
|
|
|
|
|
tcg_gen_extrl_i64_i32(PxV, carry); \
|
|
|
|
|
gen_8bitsof(PxV, PxV); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
/* r5:4 = sub(r1:0, r3:2, p1):carry */
|
|
|
|
|
#define fGEN_TCG_A4_subp_c(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv_i64 carry = tcg_temp_new_i64(); \
|
2021-10-11 19:48:52 +03:00
|
|
|
TCGv_i64 zero = tcg_constant_i64(0); \
|
2021-04-09 04:07:49 +03:00
|
|
|
TCGv_i64 not_RttV = tcg_temp_new_i64(); \
|
|
|
|
|
tcg_gen_extu_i32_i64(carry, PxV); \
|
|
|
|
|
tcg_gen_andi_i64(carry, carry, 1); \
|
|
|
|
|
tcg_gen_not_i64(not_RttV, RttV); \
|
|
|
|
|
tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
|
|
|
|
|
tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \
|
|
|
|
|
tcg_gen_extrl_i64_i32(PxV, carry); \
|
|
|
|
|
gen_8bitsof(PxV, PxV); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2021-04-09 04:07:48 +03:00
|
|
|
/*
|
|
|
|
|
* Compare each of the 8 unsigned bytes
|
|
|
|
|
* The minimum is placed in each byte of the destination.
|
|
|
|
|
* Each bit of the predicate is set true if the bit from the first operand
|
|
|
|
|
* is greater than the bit from the second operand.
|
|
|
|
|
* r5:4,p1 = vminub(r1:0, r3:2)
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_A6_vminub_RdP(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv left = tcg_temp_new(); \
|
|
|
|
|
TCGv right = tcg_temp_new(); \
|
|
|
|
|
TCGv tmp = tcg_temp_new(); \
|
|
|
|
|
tcg_gen_movi_tl(PeV, 0); \
|
|
|
|
|
tcg_gen_movi_i64(RddV, 0); \
|
|
|
|
|
for (int i = 0; i < 8; i++) { \
|
|
|
|
|
gen_get_byte_i64(left, i, RttV, false); \
|
|
|
|
|
gen_get_byte_i64(right, i, RssV, false); \
|
|
|
|
|
tcg_gen_setcond_tl(TCG_COND_GT, tmp, left, right); \
|
|
|
|
|
tcg_gen_deposit_tl(PeV, PeV, tmp, i, 1); \
|
|
|
|
|
tcg_gen_umin_tl(tmp, left, right); \
|
|
|
|
|
gen_set_byte_i64(i, RddV, tmp); \
|
|
|
|
|
} \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2022-11-08 19:29:02 +03:00
|
|
|
#define fGEN_TCG_J2_call(SHORTCODE) \
|
|
|
|
|
gen_call(ctx, riV)
|
2023-03-07 05:58:16 +03:00
|
|
|
#define fGEN_TCG_J2_callr(SHORTCODE) \
|
|
|
|
|
gen_callr(ctx, RsV)
|
2023-04-28 01:40:56 +03:00
|
|
|
#define fGEN_TCG_J2_callrh(SHORTCODE) \
|
|
|
|
|
gen_callr(ctx, RsV)
|
2022-11-08 19:29:02 +03:00
|
|
|
|
|
|
|
|
#define fGEN_TCG_J2_callt(SHORTCODE) \
|
|
|
|
|
gen_cond_call(ctx, PuV, TCG_COND_EQ, riV)
|
|
|
|
|
#define fGEN_TCG_J2_callf(SHORTCODE) \
|
|
|
|
|
gen_cond_call(ctx, PuV, TCG_COND_NE, riV)
|
2023-03-07 05:58:16 +03:00
|
|
|
#define fGEN_TCG_J2_callrt(SHORTCODE) \
|
|
|
|
|
gen_cond_callr(ctx, TCG_COND_EQ, PuV, RsV)
|
|
|
|
|
#define fGEN_TCG_J2_callrf(SHORTCODE) \
|
|
|
|
|
gen_cond_callr(ctx, TCG_COND_NE, PuV, RsV)
|
2022-11-08 19:29:02 +03:00
|
|
|
|
2023-04-28 01:59:54 +03:00
|
|
|
#define fGEN_TCG_J2_loop0r(SHORTCODE) \
|
|
|
|
|
gen_loop0r(ctx, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J2_loop1r(SHORTCODE) \
|
|
|
|
|
gen_loop1r(ctx, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J2_loop0i(SHORTCODE) \
|
|
|
|
|
gen_loop0i(ctx, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J2_loop1i(SHORTCODE) \
|
|
|
|
|
gen_loop1i(ctx, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J2_ploop1sr(SHORTCODE) \
|
|
|
|
|
gen_ploopNsr(ctx, 1, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J2_ploop1si(SHORTCODE) \
|
|
|
|
|
gen_ploopNsi(ctx, 1, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J2_ploop2sr(SHORTCODE) \
|
|
|
|
|
gen_ploopNsr(ctx, 2, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J2_ploop2si(SHORTCODE) \
|
|
|
|
|
gen_ploopNsi(ctx, 2, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J2_ploop3sr(SHORTCODE) \
|
|
|
|
|
gen_ploopNsr(ctx, 3, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J2_ploop3si(SHORTCODE) \
|
|
|
|
|
gen_ploopNsi(ctx, 3, UiV, riV)
|
|
|
|
|
|
2022-11-10 20:49:35 +03:00
|
|
|
#define fGEN_TCG_J2_endloop0(SHORTCODE) \
|
|
|
|
|
gen_endloop0(ctx)
|
2023-03-07 05:58:17 +03:00
|
|
|
#define fGEN_TCG_J2_endloop1(SHORTCODE) \
|
|
|
|
|
gen_endloop1(ctx)
|
|
|
|
|
#define fGEN_TCG_J2_endloop01(SHORTCODE) \
|
|
|
|
|
gen_endloop01(ctx)
|
2022-11-10 20:49:35 +03:00
|
|
|
|
2022-11-08 19:29:03 +03:00
|
|
|
/*
|
|
|
|
|
* Compound compare and jump instructions
|
|
|
|
|
* Here is a primer to understand the tag names
|
|
|
|
|
*
|
|
|
|
|
* Comparison
|
|
|
|
|
* cmpeqi compare equal to an immediate
|
|
|
|
|
* cmpgti compare greater than an immediate
|
|
|
|
|
* cmpgtiu compare greater than an unsigned immediate
|
|
|
|
|
* cmpeqn1 compare equal to negative 1
|
|
|
|
|
* cmpgtn1 compare greater than negative 1
|
|
|
|
|
* cmpeq compare equal (two registers)
|
|
|
|
|
* cmpgtu compare greater than unsigned (two registers)
|
|
|
|
|
* tstbit0 test bit zero
|
|
|
|
|
*
|
|
|
|
|
* Condition
|
|
|
|
|
* tp0 p0 is true p0 = cmp.eq(r0,#5); if (p0.new) jump:nt address
|
|
|
|
|
* fp0 p0 is false p0 = cmp.eq(r0,#5); if (!p0.new) jump:nt address
|
|
|
|
|
* tp1 p1 is true p1 = cmp.eq(r0,#5); if (p1.new) jump:nt address
|
|
|
|
|
* fp1 p1 is false p1 = cmp.eq(r0,#5); if (!p1.new) jump:nt address
|
|
|
|
|
*
|
|
|
|
|
* Prediction (not modelled in qemu)
|
|
|
|
|
* _nt not taken
|
|
|
|
|
* _t taken
|
|
|
|
|
*/
|
|
|
|
|
#define fGEN_TCG_J4_cmpeq_tp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_EQ, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeq_tp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_EQ, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeq_fp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_EQ, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeq_fp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_EQ, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeq_tp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_EQ, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeq_tp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_EQ, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeq_fp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_EQ, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeq_fp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_EQ, RsV, RtV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpgt_tp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgt_tp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgt_fp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgt_fp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GT, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgt_tp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgt_tp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgt_fp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgt_fp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GT, RsV, RtV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_tp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GTU, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_tp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GTU, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_fp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GTU, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_fp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GTU, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_tp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GTU, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_tp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GTU, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_fp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GTU, RsV, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_fp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GTU, RsV, RtV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqi_tp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_EQ, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqi_tp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_EQ, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqi_fp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_EQ, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqi_fp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_EQ, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqi_tp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_EQ, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqi_tp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_EQ, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqi_fp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_EQ, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqi_fp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_EQ, RsV, UiV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_tp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GT, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_tp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GT, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_fp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GT, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_fp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GT, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_tp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GT, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_tp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GT, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_fp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GT, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_fp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GT, RsV, UiV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_tp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GTU, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_tp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GTU, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_fp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GTU, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_fp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GTU, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_tp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GTU, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_tp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GTU, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_fp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GTU, RsV, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_fp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GTU, RsV, UiV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_tp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_EQ, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_tp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_EQ, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_fp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_EQ, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_fp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_EQ, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_tp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_EQ, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_tp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_EQ, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_fp1_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_EQ, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_fp1_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_EQ, RsV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtn1_tp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_GT, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtn1_tp0_jump_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_GT, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtn1_fp0_jump_t(SHORTCODE) \
|
|
|
|
|
gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_GT, RsV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtn1_fp0_jump_nt(SHORTCODE) \
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gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_GT, RsV, riV)
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#define fGEN_TCG_J4_cmpgtn1_tp1_jump_t(SHORTCODE) \
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gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_GT, RsV, riV)
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#define fGEN_TCG_J4_cmpgtn1_tp1_jump_nt(SHORTCODE) \
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gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_GT, RsV, riV)
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#define fGEN_TCG_J4_cmpgtn1_fp1_jump_t(SHORTCODE) \
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gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_GT, RsV, riV)
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#define fGEN_TCG_J4_cmpgtn1_fp1_jump_nt(SHORTCODE) \
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gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_GT, RsV, riV)
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#define fGEN_TCG_J4_tstbit0_tp0_jump_nt(SHORTCODE) \
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gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_EQ, riV)
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#define fGEN_TCG_J4_tstbit0_tp0_jump_t(SHORTCODE) \
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gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_EQ, riV)
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#define fGEN_TCG_J4_tstbit0_fp0_jump_nt(SHORTCODE) \
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gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_NE, riV)
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#define fGEN_TCG_J4_tstbit0_fp0_jump_t(SHORTCODE) \
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gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_NE, riV)
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#define fGEN_TCG_J4_tstbit0_tp1_jump_nt(SHORTCODE) \
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gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_EQ, riV)
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#define fGEN_TCG_J4_tstbit0_tp1_jump_t(SHORTCODE) \
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gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_EQ, riV)
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#define fGEN_TCG_J4_tstbit0_fp1_jump_nt(SHORTCODE) \
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gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_NE, riV)
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#define fGEN_TCG_J4_tstbit0_fp1_jump_t(SHORTCODE) \
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gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_NE, riV)
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2023-04-28 01:59:58 +03:00
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/* p0 = cmp.eq(r0, #7) */
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#define fGEN_TCG_SA1_cmpeqi(SHORTCODE) \
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do { \
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TCGv p0 = tcg_temp_new(); \
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gen_comparei(TCG_COND_EQ, p0, RsV, uiV); \
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gen_log_pred_write(ctx, 0, p0); \
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} while (0)
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2022-11-08 19:29:04 +03:00
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#define fGEN_TCG_J2_jump(SHORTCODE) \
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gen_jump(ctx, riV)
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#define fGEN_TCG_J2_jumpr(SHORTCODE) \
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gen_jumpr(ctx, RsV)
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2023-04-28 01:40:56 +03:00
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#define fGEN_TCG_J2_jumprh(SHORTCODE) \
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gen_jumpr(ctx, RsV)
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2022-11-08 19:29:04 +03:00
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#define fGEN_TCG_J4_jumpseti(SHORTCODE) \
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do { \
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tcg_gen_movi_tl(RdV, UiV); \
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gen_jump(ctx, riV); \
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} while (0)
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#define fGEN_TCG_cond_jumpt(COND) \
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do { \
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TCGv LSB = tcg_temp_new(); \
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COND; \
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gen_cond_jump(ctx, TCG_COND_EQ, LSB, riV); \
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} while (0)
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#define fGEN_TCG_cond_jumpf(COND) \
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do { \
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TCGv LSB = tcg_temp_new(); \
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COND; \
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gen_cond_jump(ctx, TCG_COND_NE, LSB, riV); \
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} while (0)
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#define fGEN_TCG_J2_jumpt(SHORTCODE) \
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fGEN_TCG_cond_jumpt(fLSBOLD(PuV))
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#define fGEN_TCG_J2_jumptpt(SHORTCODE) \
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fGEN_TCG_cond_jumpt(fLSBOLD(PuV))
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#define fGEN_TCG_J2_jumpf(SHORTCODE) \
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fGEN_TCG_cond_jumpf(fLSBOLD(PuV))
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#define fGEN_TCG_J2_jumpfpt(SHORTCODE) \
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fGEN_TCG_cond_jumpf(fLSBOLD(PuV))
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#define fGEN_TCG_J2_jumptnew(SHORTCODE) \
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gen_cond_jump(ctx, TCG_COND_EQ, PuN, riV)
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#define fGEN_TCG_J2_jumptnewpt(SHORTCODE) \
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gen_cond_jump(ctx, TCG_COND_EQ, PuN, riV)
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#define fGEN_TCG_J2_jumpfnewpt(SHORTCODE) \
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fGEN_TCG_cond_jumpf(fLSBNEW(PuN))
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#define fGEN_TCG_J2_jumpfnew(SHORTCODE) \
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fGEN_TCG_cond_jumpf(fLSBNEW(PuN))
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#define fGEN_TCG_J2_jumprz(SHORTCODE) \
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fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_NE, LSB, RsV, 0))
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#define fGEN_TCG_J2_jumprzpt(SHORTCODE) \
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fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_NE, LSB, RsV, 0))
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#define fGEN_TCG_J2_jumprnz(SHORTCODE) \
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fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_EQ, LSB, RsV, 0))
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#define fGEN_TCG_J2_jumprnzpt(SHORTCODE) \
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fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_EQ, LSB, RsV, 0))
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#define fGEN_TCG_J2_jumprgtez(SHORTCODE) \
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fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_GE, LSB, RsV, 0))
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#define fGEN_TCG_J2_jumprgtezpt(SHORTCODE) \
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fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_GE, LSB, RsV, 0))
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#define fGEN_TCG_J2_jumprltez(SHORTCODE) \
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fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_LE, LSB, RsV, 0))
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#define fGEN_TCG_J2_jumprltezpt(SHORTCODE) \
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fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_LE, LSB, RsV, 0))
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|
|
#define fGEN_TCG_cond_jumprt(COND) \
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|
do { \
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|
TCGv LSB = tcg_temp_new(); \
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COND; \
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gen_cond_jumpr(ctx, RsV, TCG_COND_EQ, LSB); \
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|
} while (0)
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|
|
#define fGEN_TCG_cond_jumprf(COND) \
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|
do { \
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|
|
TCGv LSB = tcg_temp_new(); \
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|
COND; \
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|
gen_cond_jumpr(ctx, RsV, TCG_COND_NE, LSB); \
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|
|
} while (0)
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|
|
#define fGEN_TCG_J2_jumprt(SHORTCODE) \
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|
|
fGEN_TCG_cond_jumprt(fLSBOLD(PuV))
|
|
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|
|
#define fGEN_TCG_J2_jumprtpt(SHORTCODE) \
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|
|
fGEN_TCG_cond_jumprt(fLSBOLD(PuV))
|
|
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|
|
#define fGEN_TCG_J2_jumprf(SHORTCODE) \
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|
|
fGEN_TCG_cond_jumprf(fLSBOLD(PuV))
|
|
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|
|
#define fGEN_TCG_J2_jumprfpt(SHORTCODE) \
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|
|
fGEN_TCG_cond_jumprf(fLSBOLD(PuV))
|
|
|
|
|
#define fGEN_TCG_J2_jumprtnew(SHORTCODE) \
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|
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fGEN_TCG_cond_jumprt(fLSBNEW(PuN))
|
|
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|
|
#define fGEN_TCG_J2_jumprtnewpt(SHORTCODE) \
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|
|
fGEN_TCG_cond_jumprt(fLSBNEW(PuN))
|
|
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|
|
#define fGEN_TCG_J2_jumprfnew(SHORTCODE) \
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|
|
fGEN_TCG_cond_jumprf(fLSBNEW(PuN))
|
|
|
|
|
#define fGEN_TCG_J2_jumprfnewpt(SHORTCODE) \
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|
|
fGEN_TCG_cond_jumprf(fLSBNEW(PuN))
|
|
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|
|
|
|
|
|
|
/*
|
|
|
|
|
* New value compare & jump instructions
|
|
|
|
|
* if ([!]COND(r0.new, r1) jump:t address
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|
|
* if ([!]COND(r0.new, #7) jump:t address
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|
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|
|
*/
|
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|
|
#define fGEN_TCG_J4_cmpgt_t_jumpnv_t(SHORTCODE) \
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|
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_GT, NsN, RtV, riV)
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|
|
#define fGEN_TCG_J4_cmpgt_t_jumpnv_nt(SHORTCODE) \
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_GT, NsN, RtV, riV)
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|
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|
|
#define fGEN_TCG_J4_cmpgt_f_jumpnv_t(SHORTCODE) \
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_LE, NsN, RtV, riV)
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|
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|
|
#define fGEN_TCG_J4_cmpgt_f_jumpnv_nt(SHORTCODE) \
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_LE, NsN, RtV, riV)
|
|
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|
|
|
#define fGEN_TCG_J4_cmpeq_t_jumpnv_t(SHORTCODE) \
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|
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_EQ, NsN, RtV, riV)
|
|
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|
|
#define fGEN_TCG_J4_cmpeq_t_jumpnv_nt(SHORTCODE) \
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_EQ, NsN, RtV, riV)
|
|
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|
|
#define fGEN_TCG_J4_cmpeq_f_jumpnv_t(SHORTCODE) \
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_NE, NsN, RtV, riV)
|
|
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|
|
#define fGEN_TCG_J4_cmpeq_f_jumpnv_nt(SHORTCODE) \
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_NE, NsN, RtV, riV)
|
|
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|
|
#define fGEN_TCG_J4_cmplt_t_jumpnv_t(SHORTCODE) \
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|
|
|
|
gen_cmp_jumpnv(ctx, TCG_COND_LT, NsN, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmplt_t_jumpnv_nt(SHORTCODE) \
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|
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_LT, NsN, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmplt_f_jumpnv_t(SHORTCODE) \
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|
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_GE, NsN, RtV, riV)
|
|
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|
|
#define fGEN_TCG_J4_cmplt_f_jumpnv_nt(SHORTCODE) \
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|
|
gen_cmp_jumpnv(ctx, TCG_COND_GE, NsN, RtV, riV)
|
|
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|
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|
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|
|
|
#define fGEN_TCG_J4_cmpeqi_t_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqi_t_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, UiV, riV)
|
|
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|
|
#define fGEN_TCG_J4_cmpeqi_f_jumpnv_t(SHORTCODE) \
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|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, UiV, riV)
|
|
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|
|
#define fGEN_TCG_J4_cmpeqi_f_jumpnv_nt(SHORTCODE) \
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|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, UiV, riV)
|
|
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|
|
|
#define fGEN_TCG_J4_cmpgti_t_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_t_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_f_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgti_f_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, UiV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpltu_t_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpltu_t_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpltu_f_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmp_jumpnv(ctx, TCG_COND_GEU, NsN, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpltu_f_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmp_jumpnv(ctx, TCG_COND_GEU, NsN, RtV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_t_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_GTU, NsN, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_t_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_GTU, NsN, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_f_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_LEU, NsN, UiV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtui_f_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_LEU, NsN, UiV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_t_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmp_jumpnv(ctx, TCG_COND_GTU, NsN, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_t_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmp_jumpnv(ctx, TCG_COND_GTU, NsN, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_f_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmp_jumpnv(ctx, TCG_COND_LEU, NsN, RtV, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtu_f_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmp_jumpnv(ctx, TCG_COND_LEU, NsN, RtV, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_t_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, -1, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_t_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, -1, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_f_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, -1, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpeqn1_f_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, -1, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtn1_t_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, -1, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtn1_t_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, -1, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtn1_f_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, -1, riV)
|
|
|
|
|
#define fGEN_TCG_J4_cmpgtn1_f_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, -1, riV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_J4_tstbit0_t_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_testbit0_jumpnv(ctx, NsN, TCG_COND_EQ, riV)
|
|
|
|
|
#define fGEN_TCG_J4_tstbit0_t_jumpnv_nt(SHORTCODE) \
|
|
|
|
|
gen_testbit0_jumpnv(ctx, NsN, TCG_COND_EQ, riV)
|
|
|
|
|
#define fGEN_TCG_J4_tstbit0_f_jumpnv_t(SHORTCODE) \
|
|
|
|
|
gen_testbit0_jumpnv(ctx, NsN, TCG_COND_NE, riV)
|
|
|
|
|
#define fGEN_TCG_J4_tstbit0_f_jumpnv_nt(SHORTCODE) \
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|
|
|
|
gen_testbit0_jumpnv(ctx, NsN, TCG_COND_NE, riV)
|
|
|
|
|
|
|
|
|
|
/* r0 = r1 ; jump address */
|
|
|
|
|
#define fGEN_TCG_J4_jumpsetr(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
tcg_gen_mov_tl(RdV, RsV); \
|
|
|
|
|
gen_jump(ctx, riV); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2023-04-28 01:59:56 +03:00
|
|
|
/* if (p0.new) r0 = #0 */
|
|
|
|
|
#define fGEN_TCG_SA1_clrtnew(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
tcg_gen_movcond_tl(TCG_COND_EQ, RdV, \
|
2023-04-28 02:00:09 +03:00
|
|
|
ctx->new_pred_value[0], tcg_constant_tl(0), \
|
2023-04-28 01:59:56 +03:00
|
|
|
RdV, tcg_constant_tl(0)); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
/* if (!p0.new) r0 = #0 */
|
|
|
|
|
#define fGEN_TCG_SA1_clrfnew(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
tcg_gen_movcond_tl(TCG_COND_NE, RdV, \
|
2023-04-28 02:00:09 +03:00
|
|
|
ctx->new_pred_value[0], tcg_constant_tl(0), \
|
2023-04-28 01:59:56 +03:00
|
|
|
RdV, tcg_constant_tl(0)); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2022-11-08 19:29:01 +03:00
|
|
|
#define fGEN_TCG_J2_pause(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
uiV = uiV; \
|
|
|
|
|
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2022-11-08 19:28:58 +03:00
|
|
|
/* r0 = asr(r1, r2):sat */
|
|
|
|
|
#define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \
|
2023-04-05 19:42:11 +03:00
|
|
|
gen_asr_r_r_sat(ctx, RdV, RsV, RtV)
|
2022-11-08 19:28:58 +03:00
|
|
|
|
|
|
|
|
/* r0 = asl(r1, r2):sat */
|
|
|
|
|
#define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \
|
2023-04-05 19:42:11 +03:00
|
|
|
gen_asl_r_r_sat(ctx, RdV, RsV, RtV)
|
2022-11-08 19:28:58 +03:00
|
|
|
|
2023-03-07 05:58:15 +03:00
|
|
|
#define fGEN_TCG_SL2_jumpr31(SHORTCODE) \
|
|
|
|
|
gen_jumpr(ctx, hex_gpr[HEX_REG_LR])
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_SL2_jumpr31_t(SHORTCODE) \
|
|
|
|
|
gen_cond_jumpr31(ctx, TCG_COND_EQ, hex_pred[0])
|
|
|
|
|
#define fGEN_TCG_SL2_jumpr31_f(SHORTCODE) \
|
|
|
|
|
gen_cond_jumpr31(ctx, TCG_COND_NE, hex_pred[0])
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_SL2_jumpr31_tnew(SHORTCODE) \
|
2023-04-28 02:00:09 +03:00
|
|
|
gen_cond_jumpr31(ctx, TCG_COND_EQ, ctx->new_pred_value[0])
|
2023-03-07 05:58:15 +03:00
|
|
|
#define fGEN_TCG_SL2_jumpr31_fnew(SHORTCODE) \
|
2023-04-28 02:00:09 +03:00
|
|
|
gen_cond_jumpr31(ctx, TCG_COND_NE, ctx->new_pred_value[0])
|
2023-03-07 05:58:15 +03:00
|
|
|
|
2023-03-08 01:40:58 +03:00
|
|
|
/* Count trailing zeros/ones */
|
|
|
|
|
#define fGEN_TCG_S2_ct0(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
tcg_gen_ctzi_tl(RdV, RsV, 32); \
|
|
|
|
|
} while (0)
|
|
|
|
|
#define fGEN_TCG_S2_ct1(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
tcg_gen_not_tl(RdV, RsV); \
|
|
|
|
|
tcg_gen_ctzi_tl(RdV, RdV, 32); \
|
|
|
|
|
} while (0)
|
|
|
|
|
#define fGEN_TCG_S2_ct0p(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv_i64 tmp = tcg_temp_new_i64(); \
|
|
|
|
|
tcg_gen_ctzi_i64(tmp, RssV, 64); \
|
|
|
|
|
tcg_gen_extrl_i64_i32(RdV, tmp); \
|
|
|
|
|
} while (0)
|
|
|
|
|
#define fGEN_TCG_S2_ct1p(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
TCGv_i64 tmp = tcg_temp_new_i64(); \
|
|
|
|
|
tcg_gen_not_i64(tmp, RssV); \
|
|
|
|
|
tcg_gen_ctzi_i64(tmp, tmp, 64); \
|
|
|
|
|
tcg_gen_extrl_i64_i32(RdV, tmp); \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
2023-04-28 02:00:06 +03:00
|
|
|
#define fGEN_TCG_S2_insert(SHORTCODE) \
|
|
|
|
|
do { \
|
|
|
|
|
int width = uiV; \
|
|
|
|
|
int offset = UiV; \
|
|
|
|
|
if (width != 0) { \
|
|
|
|
|
if (offset + width > 32) { \
|
|
|
|
|
width = 32 - offset; \
|
|
|
|
|
} \
|
|
|
|
|
tcg_gen_deposit_tl(RxV, RxV, RsV, offset, width); \
|
|
|
|
|
} \
|
|
|
|
|
} while (0)
|
|
|
|
|
#define fGEN_TCG_S2_insert_rp(SHORTCODE) \
|
|
|
|
|
gen_insert_rp(ctx, RxV, RsV, RttV)
|
|
|
|
|
#define fGEN_TCG_S2_asr_r_svw_trun(SHORTCODE) \
|
|
|
|
|
gen_asr_r_svw_trun(ctx, RdV, RssV, RtV)
|
|
|
|
|
#define fGEN_TCG_A2_swiz(SHORTCODE) \
|
|
|
|
|
tcg_gen_bswap_tl(RdV, RsV)
|
|
|
|
|
|
2021-02-08 08:46:18 +03:00
|
|
|
/* Floating point */
|
|
|
|
|
#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_sf2df(RddV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_df2sf(RdV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_uw2sf(RdV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_uw2df(RddV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_w2sf(RdV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_w2df(RddV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_ud2sf(RdV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_ud2df(RddV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_d2sf(RdV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_d2df(RddV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_sf2uw(RdV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_sf2w(RdV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_sf2ud(RddV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_sf2d(RddV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_df2uw(RdV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_df2w(RdV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_df2ud(RddV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_df2d(RddV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_df2w_chop(RdV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \
|
|
|
|
|
gen_helper_conv_df2d_chop(RddV, cpu_env, RssV)
|
|
|
|
|
#define fGEN_TCG_F2_sfadd(SHORTCODE) \
|
|
|
|
|
gen_helper_sfadd(RdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sfsub(SHORTCODE) \
|
|
|
|
|
gen_helper_sfsub(RdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \
|
|
|
|
|
gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \
|
|
|
|
|
gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \
|
|
|
|
|
gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \
|
|
|
|
|
gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sfmax(SHORTCODE) \
|
|
|
|
|
gen_helper_sfmax(RdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sfmin(SHORTCODE) \
|
|
|
|
|
gen_helper_sfmin(RdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sfclass(SHORTCODE) \
|
|
|
|
|
do { \
|
2021-10-03 03:47:50 +03:00
|
|
|
TCGv imm = tcg_constant_tl(uiV); \
|
2021-02-08 08:46:18 +03:00
|
|
|
gen_helper_sfclass(PdV, cpu_env, RsV, imm); \
|
|
|
|
|
} while (0)
|
|
|
|
|
#define fGEN_TCG_F2_sffixupn(SHORTCODE) \
|
|
|
|
|
gen_helper_sffixupn(RdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sffixupd(SHORTCODE) \
|
|
|
|
|
gen_helper_sffixupd(RdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sffixupr(SHORTCODE) \
|
|
|
|
|
gen_helper_sffixupr(RdV, cpu_env, RsV)
|
|
|
|
|
#define fGEN_TCG_F2_dfadd(SHORTCODE) \
|
|
|
|
|
gen_helper_dfadd(RddV, cpu_env, RssV, RttV)
|
|
|
|
|
#define fGEN_TCG_F2_dfsub(SHORTCODE) \
|
|
|
|
|
gen_helper_dfsub(RddV, cpu_env, RssV, RttV)
|
|
|
|
|
#define fGEN_TCG_F2_dfmax(SHORTCODE) \
|
|
|
|
|
gen_helper_dfmax(RddV, cpu_env, RssV, RttV)
|
|
|
|
|
#define fGEN_TCG_F2_dfmin(SHORTCODE) \
|
|
|
|
|
gen_helper_dfmin(RddV, cpu_env, RssV, RttV)
|
|
|
|
|
#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \
|
|
|
|
|
gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV)
|
|
|
|
|
#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \
|
|
|
|
|
gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV)
|
|
|
|
|
#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \
|
|
|
|
|
gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV)
|
|
|
|
|
#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \
|
|
|
|
|
gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV)
|
|
|
|
|
#define fGEN_TCG_F2_dfclass(SHORTCODE) \
|
|
|
|
|
do { \
|
2021-10-03 03:47:50 +03:00
|
|
|
TCGv imm = tcg_constant_tl(uiV); \
|
2021-02-08 08:46:18 +03:00
|
|
|
gen_helper_dfclass(PdV, cpu_env, RssV, imm); \
|
|
|
|
|
} while (0)
|
|
|
|
|
#define fGEN_TCG_F2_sfmpy(SHORTCODE) \
|
|
|
|
|
gen_helper_sfmpy(RdV, cpu_env, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sffma(SHORTCODE) \
|
|
|
|
|
gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \
|
|
|
|
|
gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV)
|
|
|
|
|
#define fGEN_TCG_F2_sffms(SHORTCODE) \
|
|
|
|
|
gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \
|
|
|
|
|
gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV)
|
|
|
|
|
#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \
|
|
|
|
|
gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV)
|
|
|
|
|
|
|
|
|
|
#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \
|
|
|
|
|
gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV)
|
|
|
|
|
#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
|
|
|
|
|
gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
|
|
|
|
|
|
2021-06-02 02:19:42 +03:00
|
|
|
/* Nothing to do for these in qemu, need to suppress compiler warnings */
|
|
|
|
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#define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
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do { \
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RsV = RsV; \
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RtV = RtV; \
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} while (0)
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#define fGEN_TCG_Y5_l2fetch(SHORTCODE) \
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do { \
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RsV = RsV; \
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} while (0)
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2023-04-10 19:09:41 +03:00
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#define fGEN_TCG_Y2_isync(SHORTCODE) \
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do { } while (0)
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#define fGEN_TCG_Y2_barrier(SHORTCODE) \
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do { } while (0)
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#define fGEN_TCG_Y2_syncht(SHORTCODE) \
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do { } while (0)
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#define fGEN_TCG_Y2_dcfetchbo(SHORTCODE) \
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do { \
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RsV = RsV; \
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uiV = uiV; \
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} while (0)
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2021-06-02 02:19:42 +03:00
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2023-04-28 01:40:50 +03:00
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#define fGEN_TCG_L2_loadw_aq(SHORTCODE) SHORTCODE
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#define fGEN_TCG_L4_loadd_aq(SHORTCODE) SHORTCODE
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/* Nothing to do for these in qemu, need to suppress compiler warnings */
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#define fGEN_TCG_R6_release_at_vi(SHORTCODE) \
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do { \
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RsV = RsV; \
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} while (0)
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#define fGEN_TCG_R6_release_st_vi(SHORTCODE) \
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do { \
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RsV = RsV; \
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} while (0)
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#define fGEN_TCG_S2_storew_rl_at_vi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_S4_stored_rl_at_vi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_S2_storew_rl_st_vi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_S4_stored_rl_st_vi(SHORTCODE) SHORTCODE
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2022-11-08 19:29:00 +03:00
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#define fGEN_TCG_J2_trap0(SHORTCODE) \
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do { \
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uiV = uiV; \
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \
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TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \
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gen_helper_raise_exception(cpu_env, excp); \
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} while (0)
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2021-02-08 08:46:17 +03:00
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#endif
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