2018-01-27 20:11:01 +03:00
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/*
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* MIOe-3680 PCI CAN device (SJA1000 based) emulation
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*
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* Copyright (c) 2016 Deniz Eren (deniz.eren@icloud.com)
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*
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* Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by
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* Jin Yang and Pavel Pisa
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/event_notifier.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2018-01-27 20:11:01 +03:00
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#include "qemu/thread.h"
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#include "qemu/sockets.h"
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#include "qapi/error.h"
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#include "chardev/char.h"
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2019-08-12 08:23:42 +03:00
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#include "hw/irq.h"
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2018-01-27 20:11:01 +03:00
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#include "hw/pci/pci.h"
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2019-08-12 08:23:51 +03:00
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#include "hw/qdev-properties.h"
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2019-08-12 08:23:45 +03:00
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#include "migration/vmstate.h"
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2018-01-27 20:11:01 +03:00
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#include "net/can_emu.h"
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#include "can_sja1000.h"
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#define TYPE_CAN_PCI_DEV "mioe3680_pci"
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#define MIOe3680_PCI_DEV(obj) \
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OBJECT_CHECK(Mioe3680PCIState, (obj), TYPE_CAN_PCI_DEV)
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/* the PCI device and vendor IDs */
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#ifndef MIOe3680_PCI_VENDOR_ID1
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#define MIOe3680_PCI_VENDOR_ID1 0x13fe
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#endif
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#ifndef MIOe3680_PCI_DEVICE_ID1
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#define MIOe3680_PCI_DEVICE_ID1 0xc302
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#endif
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#define MIOe3680_PCI_SJA_COUNT 2
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#define MIOe3680_PCI_SJA_RANGE 0x400
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#define MIOe3680_PCI_BYTES_PER_SJA 0x80
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typedef struct Mioe3680PCIState {
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/*< private >*/
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PCIDevice dev;
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/*< public >*/
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MemoryRegion sja_io[MIOe3680_PCI_SJA_COUNT];
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CanSJA1000State sja_state[MIOe3680_PCI_SJA_COUNT];
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qemu_irq irq;
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char *model; /* The model that support, only SJA1000 now. */
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CanBusState *canbus[MIOe3680_PCI_SJA_COUNT];
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} Mioe3680PCIState;
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static void mioe3680_pci_reset(DeviceState *dev)
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{
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Mioe3680PCIState *d = MIOe3680_PCI_DEV(dev);
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int i;
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for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) {
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can_sja_hardware_reset(&d->sja_state[i]);
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}
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}
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static uint64_t mioe3680_pci_sja1_io_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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Mioe3680PCIState *d = opaque;
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CanSJA1000State *s = &d->sja_state[0];
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if (addr >= MIOe3680_PCI_BYTES_PER_SJA) {
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return 0;
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}
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return can_sja_mem_read(s, addr >> 2, size);
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}
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static void mioe3680_pci_sja1_io_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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Mioe3680PCIState *d = opaque;
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CanSJA1000State *s = &d->sja_state[0];
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if (addr >= MIOe3680_PCI_BYTES_PER_SJA) {
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return;
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}
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can_sja_mem_write(s, addr >> 2, data, size);
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}
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static uint64_t mioe3680_pci_sja2_io_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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Mioe3680PCIState *d = opaque;
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CanSJA1000State *s = &d->sja_state[1];
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if (addr >= MIOe3680_PCI_BYTES_PER_SJA) {
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return 0;
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}
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return can_sja_mem_read(s, addr >> 2, size);
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}
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static void mioe3680_pci_sja2_io_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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Mioe3680PCIState *d = opaque;
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CanSJA1000State *s = &d->sja_state[1];
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if (addr >= MIOe3680_PCI_BYTES_PER_SJA) {
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return;
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}
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can_sja_mem_write(s, addr >> 2, data, size);
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}
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static const MemoryRegionOps mioe3680_pci_sja1_io_ops = {
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.read = mioe3680_pci_sja1_io_read,
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.write = mioe3680_pci_sja1_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.max_access_size = 1,
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},
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};
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static const MemoryRegionOps mioe3680_pci_sja2_io_ops = {
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.read = mioe3680_pci_sja2_io_read,
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.write = mioe3680_pci_sja2_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.max_access_size = 1,
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},
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};
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static void mioe3680_pci_realize(PCIDevice *pci_dev, Error **errp)
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{
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Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev);
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uint8_t *pci_conf;
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int i;
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pci_conf = pci_dev->config;
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pci_conf[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
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d->irq = pci_allocate_irq(&d->dev);
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for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) {
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can_sja_init(&d->sja_state[i], d->irq);
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}
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for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) {
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if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) {
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error_setg(errp, "can_sja_connect_to_bus failed");
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return;
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}
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}
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memory_region_init_io(&d->sja_io[0], OBJECT(d), &mioe3680_pci_sja1_io_ops,
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d, "mioe3680_pci-sja1", MIOe3680_PCI_SJA_RANGE);
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memory_region_init_io(&d->sja_io[1], OBJECT(d), &mioe3680_pci_sja2_io_ops,
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d, "mioe3680_pci-sja2", MIOe3680_PCI_SJA_RANGE);
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for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) {
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pci_register_bar(&d->dev, /*BAR*/ i, PCI_BASE_ADDRESS_SPACE_IO,
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&d->sja_io[i]);
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}
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}
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static void mioe3680_pci_exit(PCIDevice *pci_dev)
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{
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Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev);
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int i;
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for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) {
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can_sja_disconnect(&d->sja_state[i]);
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}
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qemu_free_irq(d->irq);
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}
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static const VMStateDescription vmstate_mioe3680_pci = {
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.name = "mioe3680_pci",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, Mioe3680PCIState),
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VMSTATE_STRUCT(sja_state[0], Mioe3680PCIState, 0, vmstate_can_sja,
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CanSJA1000State),
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VMSTATE_STRUCT(sja_state[1], Mioe3680PCIState, 0, vmstate_can_sja,
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CanSJA1000State),
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VMSTATE_END_OF_LIST()
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}
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};
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static void mioe3680_pci_instance_init(Object *obj)
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{
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Mioe3680PCIState *d = MIOe3680_PCI_DEV(obj);
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object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
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(Object **)&d->canbus[0],
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qdev_prop_allow_set_link_before_realize,
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0, &error_abort);
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object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
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(Object **)&d->canbus[1],
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qdev_prop_allow_set_link_before_realize,
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0, &error_abort);
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}
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static void mioe3680_pci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = mioe3680_pci_realize;
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k->exit = mioe3680_pci_exit;
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k->vendor_id = MIOe3680_PCI_VENDOR_ID1;
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k->device_id = MIOe3680_PCI_DEVICE_ID1;
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k->revision = 0x00;
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k->class_id = 0x000c09;
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k->subsystem_vendor_id = MIOe3680_PCI_VENDOR_ID1;
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k->subsystem_id = MIOe3680_PCI_DEVICE_ID1;
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dc->desc = "Mioe3680 PCICANx";
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dc->vmsd = &vmstate_mioe3680_pci;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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dc->reset = mioe3680_pci_reset;
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}
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static const TypeInfo mioe3680_pci_info = {
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.name = TYPE_CAN_PCI_DEV,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(Mioe3680PCIState),
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.class_init = mioe3680_pci_class_init,
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.instance_init = mioe3680_pci_instance_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void mioe3680_pci_register_types(void)
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{
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type_register_static(&mioe3680_pci_info);
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}
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type_init(mioe3680_pci_register_types)
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