2011-03-08 01:32:41 +03:00
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/*
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* QEMU model of the Milkymist UART block.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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2016-06-20 19:08:41 +03:00
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* http://milkymist.walle.cc/socdoc/uart.pdf
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2011-03-08 01:32:41 +03:00
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*/
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2016-01-26 21:16:57 +03:00
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#include "qemu/osdep.h"
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2019-08-12 08:23:42 +03:00
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#include "hw/irq.h"
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2019-08-12 08:23:51 +03:00
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#include "hw/qdev-properties.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/sysbus.h"
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2019-08-12 08:23:45 +03:00
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#include "migration/vmstate.h"
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2011-03-08 01:32:41 +03:00
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#include "trace.h"
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2017-01-26 17:26:44 +03:00
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#include "chardev/char-fe.h"
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2012-12-17 21:20:00 +04:00
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#include "qemu/error-report.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2011-03-08 01:32:41 +03:00
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enum {
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R_RXTX = 0,
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R_DIV,
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2011-08-11 02:13:23 +04:00
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R_STAT,
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R_CTRL,
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R_DBG,
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2011-03-08 01:32:41 +03:00
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R_MAX
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};
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2011-08-11 02:13:23 +04:00
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enum {
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STAT_THRE = (1<<0),
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STAT_RX_EVT = (1<<1),
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STAT_TX_EVT = (1<<2),
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};
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enum {
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CTRL_RX_IRQ_EN = (1<<0),
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CTRL_TX_IRQ_EN = (1<<1),
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CTRL_THRU_EN = (1<<2),
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};
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enum {
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DBG_BREAK_EN = (1<<0),
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};
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2013-07-25 01:08:14 +04:00
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#define TYPE_MILKYMIST_UART "milkymist-uart"
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#define MILKYMIST_UART(obj) \
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OBJECT_CHECK(MilkymistUartState, (obj), TYPE_MILKYMIST_UART)
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2011-03-08 01:32:41 +03:00
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struct MilkymistUartState {
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2013-07-25 01:08:14 +04:00
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SysBusDevice parent_obj;
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2011-08-31 18:48:45 +04:00
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MemoryRegion regs_region;
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2016-10-22 12:52:51 +03:00
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CharBackend chr;
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2011-08-11 02:13:23 +04:00
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qemu_irq irq;
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2011-03-08 01:32:41 +03:00
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uint32_t regs[R_MAX];
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};
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typedef struct MilkymistUartState MilkymistUartState;
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2011-08-11 02:13:23 +04:00
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static void uart_update_irq(MilkymistUartState *s)
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{
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int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
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int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
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int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
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int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
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if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
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trace_milkymist_uart_raise_irq();
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qemu_irq_raise(s->irq);
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} else {
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trace_milkymist_uart_lower_irq();
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qemu_irq_lower(s->irq);
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}
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}
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2012-10-23 14:30:10 +04:00
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static uint64_t uart_read(void *opaque, hwaddr addr,
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2011-08-31 18:48:45 +04:00
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unsigned size)
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2011-03-08 01:32:41 +03:00
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{
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MilkymistUartState *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_RXTX:
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2011-08-11 02:13:23 +04:00
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r = s->regs[addr];
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break;
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2011-03-08 01:32:41 +03:00
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case R_DIV:
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2011-08-11 02:13:23 +04:00
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case R_STAT:
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case R_CTRL:
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case R_DBG:
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2011-03-08 01:32:41 +03:00
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r = s->regs[addr];
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break;
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default:
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error_report("milkymist_uart: read access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_milkymist_uart_memory_read(addr << 2, r);
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return r;
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}
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2012-10-23 14:30:10 +04:00
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static void uart_write(void *opaque, hwaddr addr, uint64_t value,
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2011-08-31 18:48:45 +04:00
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unsigned size)
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2011-03-08 01:32:41 +03:00
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{
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MilkymistUartState *s = opaque;
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unsigned char ch = value;
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trace_milkymist_uart_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_RXTX:
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2016-10-22 12:52:59 +03:00
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qemu_chr_fe_write_all(&s->chr, &ch, 1);
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2011-08-11 02:13:23 +04:00
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s->regs[R_STAT] |= STAT_TX_EVT;
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2011-03-08 01:32:41 +03:00
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break;
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case R_DIV:
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2011-08-11 02:13:23 +04:00
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case R_CTRL:
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case R_DBG:
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2011-03-08 01:32:41 +03:00
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s->regs[addr] = value;
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break;
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2011-08-11 02:13:23 +04:00
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case R_STAT:
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/* write one to clear bits */
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s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
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2016-10-22 12:52:55 +03:00
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qemu_chr_fe_accept_input(&s->chr);
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2011-08-11 02:13:23 +04:00
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break;
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2011-03-08 01:32:41 +03:00
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default:
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error_report("milkymist_uart: write access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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2011-08-11 02:13:23 +04:00
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uart_update_irq(s);
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2011-03-08 01:32:41 +03:00
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}
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2011-08-31 18:48:45 +04:00
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static const MemoryRegionOps uart_mmio_ops = {
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.read = uart_read,
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.write = uart_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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2011-03-08 01:32:41 +03:00
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};
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static void uart_rx(void *opaque, const uint8_t *buf, int size)
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{
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MilkymistUartState *s = opaque;
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2011-08-11 02:13:23 +04:00
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assert(!(s->regs[R_STAT] & STAT_RX_EVT));
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s->regs[R_STAT] |= STAT_RX_EVT;
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2011-03-08 01:32:41 +03:00
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s->regs[R_RXTX] = *buf;
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2011-08-11 02:13:23 +04:00
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uart_update_irq(s);
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2011-03-08 01:32:41 +03:00
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}
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static int uart_can_rx(void *opaque)
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{
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2011-08-11 02:13:23 +04:00
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MilkymistUartState *s = opaque;
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return !(s->regs[R_STAT] & STAT_RX_EVT);
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2011-03-08 01:32:41 +03:00
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}
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chardev: Use QEMUChrEvent enum in IOEventHandler typedef
The Chardev events are listed in the QEMUChrEvent enum.
By using the enum in the IOEventHandler typedef we:
- make the IOEventHandler type more explicit (this handler
process out-of-band information, while the IOReadHandler
is in-band),
- help static code analyzers.
This patch was produced with the following spatch script:
@match@
expression backend, opaque, context, set_open;
identifier fd_can_read, fd_read, fd_event, be_change;
@@
qemu_chr_fe_set_handlers(backend, fd_can_read, fd_read, fd_event,
be_change, opaque, context, set_open);
@depends on match@
identifier opaque, event;
identifier match.fd_event;
@@
static
-void fd_event(void *opaque, int event)
+void fd_event(void *opaque, QEMUChrEvent event)
{
...
}
Then the typedef was modified manually in
include/chardev/char-fe.h.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20191218172009.8868-15-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-18 20:20:09 +03:00
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static void uart_event(void *opaque, QEMUChrEvent event)
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2011-03-08 01:32:41 +03:00
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{
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}
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static void milkymist_uart_reset(DeviceState *d)
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{
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2013-07-25 01:08:14 +04:00
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MilkymistUartState *s = MILKYMIST_UART(d);
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2011-03-08 01:32:41 +03:00
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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2011-08-11 02:13:23 +04:00
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/* THRE is always set */
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s->regs[R_STAT] = STAT_THRE;
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2011-03-08 01:32:41 +03:00
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}
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2013-08-31 21:22:40 +04:00
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static void milkymist_uart_realize(DeviceState *dev, Error **errp)
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2011-03-08 01:32:41 +03:00
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{
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2013-07-25 01:08:14 +04:00
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MilkymistUartState *s = MILKYMIST_UART(dev);
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2011-03-08 01:32:41 +03:00
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2016-10-22 12:52:59 +03:00
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qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
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2017-07-06 15:08:49 +03:00
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uart_event, NULL, s, NULL, true);
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2013-08-31 21:22:40 +04:00
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}
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2011-03-08 01:32:41 +03:00
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2013-08-31 21:22:40 +04:00
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static void milkymist_uart_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MilkymistUartState *s = MILKYMIST_UART(obj);
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
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"milkymist-uart", R_MAX * 4);
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sysbus_init_mmio(sbd, &s->regs_region);
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2011-03-08 01:32:41 +03:00
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}
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static const VMStateDescription vmstate_milkymist_uart = {
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.name = "milkymist-uart",
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.version_id = 1,
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.minimum_version_id = 1,
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2014-04-16 18:01:33 +04:00
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.fields = (VMStateField[]) {
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2011-03-08 01:32:41 +03:00
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VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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2016-05-25 09:39:04 +03:00
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static Property milkymist_uart_properties[] = {
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DEFINE_PROP_CHR("chardev", MilkymistUartState, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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2012-01-24 23:12:29 +04:00
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static void milkymist_uart_class_init(ObjectClass *klass, void *data)
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{
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2011-12-08 07:34:16 +04:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2012-01-24 23:12:29 +04:00
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2013-08-31 21:22:40 +04:00
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dc->realize = milkymist_uart_realize;
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2011-12-08 07:34:16 +04:00
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dc->reset = milkymist_uart_reset;
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dc->vmsd = &vmstate_milkymist_uart;
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2016-05-25 09:39:04 +03:00
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dc->props = milkymist_uart_properties;
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2012-01-24 23:12:29 +04:00
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}
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2013-01-10 19:19:07 +04:00
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static const TypeInfo milkymist_uart_info = {
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2013-07-25 01:08:14 +04:00
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.name = TYPE_MILKYMIST_UART,
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2011-12-08 07:34:16 +04:00
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MilkymistUartState),
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2013-08-31 21:22:40 +04:00
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.instance_init = milkymist_uart_init,
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2011-12-08 07:34:16 +04:00
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.class_init = milkymist_uart_class_init,
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2011-03-08 01:32:41 +03:00
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};
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2012-02-09 18:20:55 +04:00
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static void milkymist_uart_register_types(void)
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2011-03-08 01:32:41 +03:00
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{
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2011-12-08 07:34:16 +04:00
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type_register_static(&milkymist_uart_info);
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2011-03-08 01:32:41 +03:00
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}
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2012-02-09 18:20:55 +04:00
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type_init(milkymist_uart_register_types)
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