529 lines
15 KiB
C
529 lines
15 KiB
C
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/*
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* Emulation of the ibm,plb-pcix PCI controller
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* This is found in some 440 SoCs e.g. the 460EX.
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*
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* Copyright (c) 2016-2018 BALATON Zoltan
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*
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* Derived from ppc4xx_pci.c and pci-host/ppce500.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "hw/hw.h"
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#include "hw/ppc/ppc.h"
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#include "hw/ppc/ppc4xx.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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struct PLBOutMap {
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uint64_t la;
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uint64_t pcia;
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uint32_t sa;
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MemoryRegion mr;
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};
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struct PLBInMap {
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uint64_t sa;
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uint64_t la;
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MemoryRegion mr;
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};
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#define TYPE_PPC440_PCIX_HOST_BRIDGE "ppc440-pcix-host"
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#define PPC440_PCIX_HOST_BRIDGE(obj) \
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OBJECT_CHECK(PPC440PCIXState, (obj), TYPE_PPC440_PCIX_HOST_BRIDGE)
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#define PPC440_PCIX_NR_POMS 3
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#define PPC440_PCIX_NR_PIMS 3
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typedef struct PPC440PCIXState {
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PCIHostState parent_obj;
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PCIDevice *dev;
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struct PLBOutMap pom[PPC440_PCIX_NR_POMS];
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struct PLBInMap pim[PPC440_PCIX_NR_PIMS];
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uint32_t sts;
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qemu_irq irq[PCI_NUM_PINS];
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AddressSpace bm_as;
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MemoryRegion bm;
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MemoryRegion container;
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MemoryRegion iomem;
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MemoryRegion busmem;
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} PPC440PCIXState;
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#define PPC440_REG_BASE 0x80000
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#define PPC440_REG_SIZE 0xff
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#define PCIC0_CFGADDR 0x0
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#define PCIC0_CFGDATA 0x4
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#define PCIX0_POM0LAL 0x68
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#define PCIX0_POM0LAH 0x6c
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#define PCIX0_POM0SA 0x70
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#define PCIX0_POM0PCIAL 0x74
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#define PCIX0_POM0PCIAH 0x78
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#define PCIX0_POM1LAL 0x7c
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#define PCIX0_POM1LAH 0x80
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#define PCIX0_POM1SA 0x84
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#define PCIX0_POM1PCIAL 0x88
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#define PCIX0_POM1PCIAH 0x8c
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#define PCIX0_POM2SA 0x90
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#define PCIX0_PIM0SAL 0x98
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#define PCIX0_PIM0LAL 0x9c
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#define PCIX0_PIM0LAH 0xa0
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#define PCIX0_PIM1SA 0xa4
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#define PCIX0_PIM1LAL 0xa8
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#define PCIX0_PIM1LAH 0xac
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#define PCIX0_PIM2SAL 0xb0
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#define PCIX0_PIM2LAL 0xb4
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#define PCIX0_PIM2LAH 0xb8
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#define PCIX0_PIM0SAH 0xf8
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#define PCIX0_PIM2SAH 0xfc
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#define PCIX0_STS 0xe0
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#define PCI_ALL_SIZE (PPC440_REG_BASE + PPC440_REG_SIZE)
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static void ppc440_pcix_clear_region(MemoryRegion *parent,
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MemoryRegion *mem)
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{
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if (memory_region_is_mapped(mem)) {
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memory_region_del_subregion(parent, mem);
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object_unparent(OBJECT(mem));
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}
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}
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/* DMA mapping */
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static void ppc440_pcix_update_pim(PPC440PCIXState *s, int idx)
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{
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MemoryRegion *mem = &s->pim[idx].mr;
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char *name;
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uint64_t size;
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/* Before we modify anything, unmap and destroy the region */
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ppc440_pcix_clear_region(&s->bm, mem);
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if (!(s->pim[idx].sa & 1)) {
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/* Not enabled, nothing to do */
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return;
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}
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name = g_strdup_printf("PCI Inbound Window %d", idx);
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size = ~(s->pim[idx].sa & ~7ULL) + 1;
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memory_region_init_alias(mem, OBJECT(s), name, get_system_memory(),
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s->pim[idx].la, size);
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memory_region_add_subregion_overlap(&s->bm, 0, mem, -1);
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g_free(name);
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trace_ppc440_pcix_update_pim(idx, size, s->pim[idx].la);
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}
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/* BAR mapping */
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static void ppc440_pcix_update_pom(PPC440PCIXState *s, int idx)
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{
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MemoryRegion *mem = &s->pom[idx].mr;
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MemoryRegion *address_space_mem = get_system_memory();
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char *name;
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uint32_t size;
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/* Before we modify anything, unmap and destroy the region */
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ppc440_pcix_clear_region(address_space_mem, mem);
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if (!(s->pom[idx].sa & 1)) {
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/* Not enabled, nothing to do */
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return;
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}
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name = g_strdup_printf("PCI Outbound Window %d", idx);
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size = ~(s->pom[idx].sa & 0xfffffffe) + 1;
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if (!size) {
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size = 0xffffffff;
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}
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memory_region_init_alias(mem, OBJECT(s), name, &s->busmem,
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s->pom[idx].pcia, size);
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memory_region_add_subregion(address_space_mem, s->pom[idx].la, mem);
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g_free(name);
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trace_ppc440_pcix_update_pom(idx, size, s->pom[idx].la, s->pom[idx].pcia);
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}
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static void ppc440_pcix_reg_write4(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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struct PPC440PCIXState *s = opaque;
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trace_ppc440_pcix_reg_read(addr, val);
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switch (addr) {
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case PCI_VENDOR_ID ... PCI_MAX_LAT:
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stl_le_p(s->dev->config + addr, val);
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break;
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case PCIX0_POM0LAL:
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s->pom[0].la &= 0xffffffff00000000ULL;
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s->pom[0].la |= val;
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ppc440_pcix_update_pom(s, 0);
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break;
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case PCIX0_POM0LAH:
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s->pom[0].la &= 0xffffffffULL;
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s->pom[0].la |= val << 32;
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ppc440_pcix_update_pom(s, 0);
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break;
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case PCIX0_POM0SA:
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s->pom[0].sa = val;
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ppc440_pcix_update_pom(s, 0);
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break;
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case PCIX0_POM0PCIAL:
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s->pom[0].pcia &= 0xffffffff00000000ULL;
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s->pom[0].pcia |= val;
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ppc440_pcix_update_pom(s, 0);
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break;
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case PCIX0_POM0PCIAH:
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s->pom[0].pcia &= 0xffffffffULL;
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s->pom[0].pcia |= val << 32;
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ppc440_pcix_update_pom(s, 0);
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break;
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case PCIX0_POM1LAL:
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s->pom[1].la &= 0xffffffff00000000ULL;
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s->pom[1].la |= val;
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ppc440_pcix_update_pom(s, 1);
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break;
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case PCIX0_POM1LAH:
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s->pom[1].la &= 0xffffffffULL;
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s->pom[1].la |= val << 32;
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ppc440_pcix_update_pom(s, 1);
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break;
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case PCIX0_POM1SA:
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s->pom[1].sa = val;
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ppc440_pcix_update_pom(s, 1);
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break;
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case PCIX0_POM1PCIAL:
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s->pom[1].pcia &= 0xffffffff00000000ULL;
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s->pom[1].pcia |= val;
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ppc440_pcix_update_pom(s, 1);
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break;
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case PCIX0_POM1PCIAH:
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s->pom[1].pcia &= 0xffffffffULL;
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s->pom[1].pcia |= val << 32;
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ppc440_pcix_update_pom(s, 1);
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break;
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case PCIX0_POM2SA:
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s->pom[2].sa = val;
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break;
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case PCIX0_PIM0SAL:
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s->pim[0].sa &= 0xffffffff00000000ULL;
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s->pim[0].sa |= val;
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ppc440_pcix_update_pim(s, 0);
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break;
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case PCIX0_PIM0LAL:
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s->pim[0].la &= 0xffffffff00000000ULL;
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s->pim[0].la |= val;
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ppc440_pcix_update_pim(s, 0);
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break;
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case PCIX0_PIM0LAH:
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s->pim[0].la &= 0xffffffffULL;
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s->pim[0].la |= val << 32;
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ppc440_pcix_update_pim(s, 0);
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break;
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case PCIX0_PIM1SA:
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s->pim[1].sa = val;
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ppc440_pcix_update_pim(s, 1);
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break;
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case PCIX0_PIM1LAL:
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s->pim[1].la &= 0xffffffff00000000ULL;
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s->pim[1].la |= val;
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ppc440_pcix_update_pim(s, 1);
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break;
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case PCIX0_PIM1LAH:
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s->pim[1].la &= 0xffffffffULL;
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s->pim[1].la |= val << 32;
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ppc440_pcix_update_pim(s, 1);
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break;
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case PCIX0_PIM2SAL:
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s->pim[2].sa &= 0xffffffff00000000ULL;
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s->pim[2].sa = val;
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ppc440_pcix_update_pim(s, 2);
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break;
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case PCIX0_PIM2LAL:
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s->pim[2].la &= 0xffffffff00000000ULL;
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s->pim[2].la |= val;
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ppc440_pcix_update_pim(s, 2);
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break;
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case PCIX0_PIM2LAH:
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s->pim[2].la &= 0xffffffffULL;
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s->pim[2].la |= val << 32;
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ppc440_pcix_update_pim(s, 2);
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break;
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case PCIX0_STS:
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s->sts = val;
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break;
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case PCIX0_PIM0SAH:
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s->pim[0].sa &= 0xffffffffULL;
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s->pim[0].sa |= val << 32;
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ppc440_pcix_update_pim(s, 0);
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break;
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case PCIX0_PIM2SAH:
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s->pim[2].sa &= 0xffffffffULL;
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s->pim[2].sa |= val << 32;
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ppc440_pcix_update_pim(s, 2);
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break;
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default:
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error_report("%s: unhandled PCI internal register 0x%lx", __func__,
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(unsigned long)addr);
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break;
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}
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}
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static uint64_t ppc440_pcix_reg_read4(void *opaque, hwaddr addr,
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unsigned size)
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{
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struct PPC440PCIXState *s = opaque;
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uint32_t val;
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switch (addr) {
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case PCI_VENDOR_ID ... PCI_MAX_LAT:
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val = ldl_le_p(s->dev->config + addr);
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break;
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case PCIX0_POM0LAL:
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val = s->pom[0].la;
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break;
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case PCIX0_POM0LAH:
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val = s->pom[0].la >> 32;
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break;
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case PCIX0_POM0SA:
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val = s->pom[0].sa;
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break;
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case PCIX0_POM0PCIAL:
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val = s->pom[0].pcia;
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break;
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case PCIX0_POM0PCIAH:
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val = s->pom[0].pcia >> 32;
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break;
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case PCIX0_POM1LAL:
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val = s->pom[1].la;
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break;
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case PCIX0_POM1LAH:
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val = s->pom[1].la >> 32;
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break;
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case PCIX0_POM1SA:
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val = s->pom[1].sa;
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break;
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case PCIX0_POM1PCIAL:
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val = s->pom[1].pcia;
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break;
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case PCIX0_POM1PCIAH:
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val = s->pom[1].pcia >> 32;
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break;
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case PCIX0_POM2SA:
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val = s->pom[2].sa;
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break;
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case PCIX0_PIM0SAL:
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val = s->pim[0].sa;
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break;
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case PCIX0_PIM0LAL:
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val = s->pim[0].la;
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break;
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case PCIX0_PIM0LAH:
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val = s->pim[0].la >> 32;
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break;
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case PCIX0_PIM1SA:
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val = s->pim[1].sa;
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break;
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case PCIX0_PIM1LAL:
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val = s->pim[1].la;
|
||
|
|
break;
|
||
|
|
case PCIX0_PIM1LAH:
|
||
|
|
val = s->pim[1].la >> 32;
|
||
|
|
break;
|
||
|
|
case PCIX0_PIM2SAL:
|
||
|
|
val = s->pim[2].sa;
|
||
|
|
break;
|
||
|
|
case PCIX0_PIM2LAL:
|
||
|
|
val = s->pim[2].la;
|
||
|
|
break;
|
||
|
|
case PCIX0_PIM2LAH:
|
||
|
|
val = s->pim[2].la >> 32;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PCIX0_STS:
|
||
|
|
val = s->sts;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case PCIX0_PIM0SAH:
|
||
|
|
val = s->pim[0].sa >> 32;
|
||
|
|
break;
|
||
|
|
case PCIX0_PIM2SAH:
|
||
|
|
val = s->pim[2].sa >> 32;
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
error_report("%s: invalid PCI internal register 0x%lx", __func__,
|
||
|
|
(unsigned long)addr);
|
||
|
|
val = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
trace_ppc440_pcix_reg_read(addr, val);
|
||
|
|
return val;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const MemoryRegionOps pci_reg_ops = {
|
||
|
|
.read = ppc440_pcix_reg_read4,
|
||
|
|
.write = ppc440_pcix_reg_write4,
|
||
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void ppc440_pcix_reset(DeviceState *dev)
|
||
|
|
{
|
||
|
|
struct PPC440PCIXState *s = PPC440_PCIX_HOST_BRIDGE(dev);
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0; i < PPC440_PCIX_NR_POMS; i++) {
|
||
|
|
ppc440_pcix_clear_region(get_system_memory(), &s->pom[i].mr);
|
||
|
|
}
|
||
|
|
for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {
|
||
|
|
ppc440_pcix_clear_region(&s->bm, &s->pim[i].mr);
|
||
|
|
}
|
||
|
|
memset(s->pom, 0, sizeof(s->pom));
|
||
|
|
memset(s->pim, 0, sizeof(s->pim));
|
||
|
|
for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {
|
||
|
|
s->pim[i].sa = 0xffffffff00000000ULL;
|
||
|
|
}
|
||
|
|
s->sts = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* All pins from each slot are tied to a single board IRQ.
|
||
|
|
* This may need further refactoring for other boards. */
|
||
|
|
static int ppc440_pcix_map_irq(PCIDevice *pci_dev, int irq_num)
|
||
|
|
{
|
||
|
|
int slot = pci_dev->devfn >> 3;
|
||
|
|
trace_ppc440_pcix_map_irq(pci_dev->devfn, irq_num, slot);
|
||
|
|
return slot - 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ppc440_pcix_set_irq(void *opaque, int irq_num, int level)
|
||
|
|
{
|
||
|
|
qemu_irq *pci_irqs = opaque;
|
||
|
|
|
||
|
|
trace_ppc440_pcix_set_irq(irq_num);
|
||
|
|
if (irq_num < 0) {
|
||
|
|
error_report("%s: PCI irq %d", __func__, irq_num);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
qemu_set_irq(pci_irqs[irq_num], level);
|
||
|
|
}
|
||
|
|
|
||
|
|
static AddressSpace *ppc440_pcix_set_iommu(PCIBus *b, void *opaque, int devfn)
|
||
|
|
{
|
||
|
|
PPC440PCIXState *s = opaque;
|
||
|
|
|
||
|
|
return &s->bm_as;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* The default pci_host_data_{read,write} functions in pci/pci_host.c
|
||
|
|
* deny access to registers without bit 31 set but our clients want
|
||
|
|
* this to work so we have to override these here */
|
||
|
|
static void pci_host_data_write(void *opaque, hwaddr addr,
|
||
|
|
uint64_t val, unsigned len)
|
||
|
|
{
|
||
|
|
PCIHostState *s = opaque;
|
||
|
|
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
|
||
|
|
}
|
||
|
|
|
||
|
|
static uint64_t pci_host_data_read(void *opaque,
|
||
|
|
hwaddr addr, unsigned len)
|
||
|
|
{
|
||
|
|
PCIHostState *s = opaque;
|
||
|
|
uint32_t val;
|
||
|
|
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
|
||
|
|
return val;
|
||
|
|
}
|
||
|
|
|
||
|
|
const MemoryRegionOps ppc440_pcix_host_data_ops = {
|
||
|
|
.read = pci_host_data_read,
|
||
|
|
.write = pci_host_data_write,
|
||
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int ppc440_pcix_initfn(SysBusDevice *dev)
|
||
|
|
{
|
||
|
|
PPC440PCIXState *s;
|
||
|
|
PCIHostState *h;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
h = PCI_HOST_BRIDGE(dev);
|
||
|
|
s = PPC440_PCIX_HOST_BRIDGE(dev);
|
||
|
|
|
||
|
|
for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
|
||
|
|
sysbus_init_irq(dev, &s->irq[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
memory_region_init(&s->busmem, OBJECT(dev), "pci bus memory", UINT64_MAX);
|
||
|
|
h->bus = pci_register_root_bus(DEVICE(dev), NULL, ppc440_pcix_set_irq,
|
||
|
|
ppc440_pcix_map_irq, s->irq, &s->busmem,
|
||
|
|
get_system_io(), PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
|
||
|
|
|
||
|
|
s->dev = pci_create_simple(h->bus, PCI_DEVFN(0, 0), "ppc4xx-host-bridge");
|
||
|
|
|
||
|
|
memory_region_init(&s->bm, OBJECT(s), "bm-ppc440-pcix", UINT64_MAX);
|
||
|
|
memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
|
||
|
|
address_space_init(&s->bm_as, &s->bm, "pci-bm");
|
||
|
|
pci_setup_iommu(h->bus, ppc440_pcix_set_iommu, s);
|
||
|
|
|
||
|
|
memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
|
||
|
|
memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops,
|
||
|
|
h, "pci-conf-idx", 4);
|
||
|
|
memory_region_init_io(&h->data_mem, OBJECT(s), &ppc440_pcix_host_data_ops,
|
||
|
|
h, "pci-conf-data", 4);
|
||
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
|
||
|
|
"pci.reg", PPC440_REG_SIZE);
|
||
|
|
memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
|
||
|
|
memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
|
||
|
|
memory_region_add_subregion(&s->container, PPC440_REG_BASE, &s->iomem);
|
||
|
|
sysbus_init_mmio(dev, &s->container);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ppc440_pcix_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
k->init = ppc440_pcix_initfn;
|
||
|
|
dc->reset = ppc440_pcix_reset;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo ppc440_pcix_info = {
|
||
|
|
.name = TYPE_PPC440_PCIX_HOST_BRIDGE,
|
||
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
||
|
|
.instance_size = sizeof(PPC440PCIXState),
|
||
|
|
.class_init = ppc440_pcix_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void ppc440_pcix_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&ppc440_pcix_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(ppc440_pcix_register_types)
|