2013-09-03 23:12:03 +04:00
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#ifndef TARGET_ARM_TRANSLATE_H
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#define TARGET_ARM_TRANSLATE_H
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/* internal defines */
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typedef struct DisasContext {
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target_ulong pc;
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2013-09-03 23:12:10 +04:00
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uint32_t insn;
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2013-09-03 23:12:03 +04:00
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int is_jmp;
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/* Nonzero if this instruction has been conditionally skipped. */
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int condjmp;
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/* The label that will be jumped to when the instruction is skipped. */
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2015-02-13 23:51:55 +03:00
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TCGLabel *condlabel;
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2013-09-03 23:12:03 +04:00
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/* Thumb-2 conditional execution bits. */
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int condexec_mask;
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int condexec_cond;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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int thumb;
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int bswap_code;
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#if !defined(CONFIG_USER_ONLY)
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int user;
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#endif
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2015-02-05 16:37:23 +03:00
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ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
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2014-12-11 15:07:48 +03:00
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bool ns; /* Use non-secure CPREG bank on access */
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2015-05-29 13:28:53 +03:00
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int fp_excp_el; /* FP exception EL or 0 if enabled */
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2015-09-08 19:38:44 +03:00
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/* Flag indicating that exceptions from secure mode are routed to EL3. */
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bool secure_routed_to_el3;
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2014-04-15 22:18:39 +04:00
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bool vfp_enabled; /* FP enabled via FPSCR.EN */
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2013-09-03 23:12:03 +04:00
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int vec_len;
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int vec_stride;
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2014-04-15 22:18:38 +04:00
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/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
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* so that top level loop can generate correct syndrome information.
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*/
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uint32_t svc_imm;
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2013-09-03 23:12:09 +04:00
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int aarch64;
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2014-10-24 15:19:14 +04:00
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int current_el;
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2014-01-05 02:15:44 +04:00
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GHashTable *cp_regs;
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2014-03-17 20:31:47 +04:00
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uint64_t features; /* CPU features bits */
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2014-04-15 22:18:40 +04:00
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/* Because unallocated encodings generate different exception syndrome
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* information from traps due to FP being disabled, we can't do a single
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* "is fp access disabled" check at a high level in the decode tree.
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* To help in catching bugs where the access check was forgotten in some
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* code path, we set this flag when the access check is done, and assert
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* that it is set at the point where we actually touch the FP regs.
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*/
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bool fp_access_checked;
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2014-08-19 21:56:26 +04:00
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/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
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* single-step support).
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*/
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bool ss_active;
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bool pstate_ss;
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/* True if the insn just emitted was a load-exclusive instruction
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* (necessary for syndrome information for single step exceptions),
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* ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
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*/
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bool is_ldex;
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/* True if a single-step exception will be taken to the current EL */
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bool ss_same_el;
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2014-09-29 21:48:48 +04:00
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/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
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int c15_cpar;
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2013-12-17 23:42:32 +04:00
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#define TMP_A64_MAX 16
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int tmp_a64_count;
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TCGv_i64 tmp_a64[TMP_A64_MAX];
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2013-09-03 23:12:03 +04:00
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} DisasContext;
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2015-09-14 16:39:47 +03:00
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typedef struct DisasCompare {
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TCGCond cond;
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TCGv_i32 value;
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bool value_global;
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} DisasCompare;
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2015-09-14 16:39:47 +03:00
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/* Share the TCG temporaries common between 32 and 64 bit modes. */
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2013-09-03 23:12:04 +04:00
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extern TCGv_ptr cpu_env;
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2015-09-14 16:39:47 +03:00
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extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
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extern TCGv_i64 cpu_exclusive_addr;
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extern TCGv_i64 cpu_exclusive_val;
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#ifdef CONFIG_USER_ONLY
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extern TCGv_i64 cpu_exclusive_test;
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extern TCGv_i32 cpu_exclusive_info;
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#endif
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2013-09-03 23:12:04 +04:00
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2014-03-17 20:31:47 +04:00
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static inline int arm_dc_feature(DisasContext *dc, int feature)
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{
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return (dc->features & (1ULL << feature)) != 0;
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}
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2014-05-27 20:09:50 +04:00
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static inline int get_mem_index(DisasContext *s)
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{
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2015-02-05 16:37:23 +03:00
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return s->mmu_idx;
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2014-05-27 20:09:50 +04:00
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}
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2015-05-29 13:28:50 +03:00
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/* Function used to determine the target exception EL when otherwise not known
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* or default.
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*/
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static inline int default_exception_el(DisasContext *s)
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{
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/* If we are coming from secure EL0 in a system with a 32-bit EL3, then
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* there is no secure EL1, so we route exceptions to EL3. Otherwise,
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* exceptions can only be routed to ELs above 1, so we target the higher of
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* 1 or the current EL.
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*/
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2015-09-08 19:38:44 +03:00
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return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
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2015-05-29 13:28:50 +03:00
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? 3 : MAX(1, s->current_el);
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}
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2013-12-17 23:42:31 +04:00
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/* target-specific extra values for is_jmp */
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/* These instructions trap after executing, so the A32/T32 decoder must
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* defer them until after the conditional execution state has been updated.
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* WFI also needs special handling when single-stepping.
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*/
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#define DISAS_WFI 4
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#define DISAS_SWI 5
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/* For instructions which unconditionally cause an exception we can skip
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* emitting unreachable code at the end of the TB in the A64 decoder
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*/
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#define DISAS_EXC 6
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2014-03-10 18:56:30 +04:00
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/* WFE */
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#define DISAS_WFE 7
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2014-10-24 15:19:13 +04:00
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#define DISAS_HVC 8
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#define DISAS_SMC 9
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2015-07-06 12:05:44 +03:00
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#define DISAS_YIELD 10
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2013-12-17 23:42:31 +04:00
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2013-09-03 23:12:10 +04:00
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#ifdef TARGET_AARCH64
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void a64_translate_init(void);
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2015-09-02 06:01:40 +03:00
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void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
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2013-09-03 23:12:10 +04:00
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void gen_a64_set_pc_im(uint64_t val);
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2014-04-15 22:19:15 +04:00
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void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags);
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2013-09-03 23:12:10 +04:00
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#else
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static inline void a64_translate_init(void)
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{
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}
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2015-09-02 06:01:40 +03:00
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static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
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2013-09-03 23:12:10 +04:00
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{
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}
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static inline void gen_a64_set_pc_im(uint64_t val)
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{
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}
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2014-04-15 22:19:15 +04:00
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static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf,
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int flags)
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{
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}
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2013-09-03 23:12:10 +04:00
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#endif
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2015-09-14 16:39:47 +03:00
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void arm_test_cc(DisasCompare *cmp, int cc);
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void arm_free_cc(DisasCompare *cmp);
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void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
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2015-02-13 23:51:55 +03:00
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void arm_gen_test_cc(int cc, TCGLabel *label);
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2013-12-17 23:42:33 +04:00
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2013-09-03 23:12:03 +04:00
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#endif /* TARGET_ARM_TRANSLATE_H */
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