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qemu/target/i386/tcg/ops_sse_header.h.inc

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converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
/*
Implement SSE4.1, SSE4.2 (x86). This adds support for CPUID_EXT_SSE41, CPUID_EXT_SSE42, CPUID_EXT_POPCNT extensions. Most instructions haven't been tested yet. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5411 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-04 07:27:44 +04:00
* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI support
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
*
* Copyright (c) 2005 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
x86 tcg cpus: Fix Lesser GPL version number There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023122801.19514-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-10-23 15:28:01 +03:00
* version 2.1 of the License, or (at your option) any later version.
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
Update to a hopefully more future proof FSF address Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-17 00:47:01 +04:00
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
*/
#if SHIFT == 0
#define Reg MMXReg
#define SUFFIX _mmx
#else
target-i386: Rename struct XMMReg to ZMMReg The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-19 21:12:40 +03:00
#define Reg ZMMReg
target/i386: Introduce 256-bit vector helpers The new implementation of SSE will cover AVX from the get go, because all the work for the helper functions is already done. We just need to build them. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-01 10:04:17 +03:00
#if SHIFT == 1
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#define SUFFIX _xmm
target/i386: Introduce 256-bit vector helpers The new implementation of SSE will cover AVX from the get go, because all the work for the helper functions is already done. We just need to build them. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-01 10:04:17 +03:00
#else
#define SUFFIX _ymm
#endif
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#endif
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
#define dh_alias_Reg ptr
target-i386: Rename struct XMMReg to ZMMReg The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-19 21:12:40 +03:00
#define dh_alias_ZMMReg ptr
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
#define dh_alias_MMXReg ptr
#define dh_ctype_Reg Reg *
target-i386: Rename struct XMMReg to ZMMReg The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-19 21:12:40 +03:00
#define dh_ctype_ZMMReg ZMMReg *
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
#define dh_ctype_MMXReg MMXReg *
tcg: Remove dh_alias indirection for dh_typecode The dh_alias redirect is intended to handle TCG types as distinguished from C types. TCG does not distinguish signed int from unsigned int, because they are the same size. However, we need to retain this distinction for dh_typecode, lest we fail to extend abi types properly for the host call parameters. This bug was detected when running the 'arm' emulator on an s390 system. The s390 uses TCG_TARGET_EXTEND_ARGS which triggers code in tcg_gen_callN to extend 32 bit values to 64 bits; the incorrect sign data in the typemask for each argument caused the values to be extended as unsigned values. This simple program exhibits the problem: static volatile int num = -9; static volatile int den = -5; int main(void) { int quo = num / den; printf("num %d den %d quo %d\n", num, den, quo); exit(0); } When run on the broken qemu, this results in: num -9 den -5 quo 0 The correct result is: num -9 den -5 quo 1 Fixes: 7319d83a735 ("tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/876 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reported-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> Tested-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> Tested-by: Keith Packard <keithp@keithp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-17 04:06:22 +03:00
#define dh_typecode_Reg dh_typecode_ptr
#define dh_typecode_ZMMReg dh_typecode_ptr
#define dh_typecode_MMXReg dh_typecode_ptr
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(psrlw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psraw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psllw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psrld, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psrad, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(pslld, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psrlq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psllq, SUFFIX), void, env, Reg, Reg, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT >= 1
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(psrldq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(pslldq, SUFFIX), void, env, Reg, Reg, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#endif
#define SSE_HELPER_B(name, F)\
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(name, SUFFIX), void, env, Reg, Reg, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#define SSE_HELPER_W(name, F)\
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(name, SUFFIX), void, env, Reg, Reg, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#define SSE_HELPER_L(name, F)\
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(name, SUFFIX), void, env, Reg, Reg, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#define SSE_HELPER_Q(name, F)\
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(name, SUFFIX), void, env, Reg, Reg, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#if SHIFT == 0
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
DEF_HELPER_3(glue(pmulhrw, SUFFIX), void, env, Reg, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#endif
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
SSE_HELPER_W(pmulhuw, FMULHUW)
SSE_HELPER_W(pmulhw, FMULHW)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
SSE_HELPER_B(pavgb, FAVG)
SSE_HELPER_W(pavgw, FAVG)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(pmuludq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(pmaddwd, SUFFIX), void, env, Reg, Reg, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(psadbw, SUFFIX), void, env, Reg, Reg, Reg)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT < 2
x86: avoid AREG0 for FPU helpers Make FPU helpers take a parameter for CPUState instead of relying on global env. Introduce temporary wrappers for FPU load and store ops. Remove wrappers for non-AREG0 code. Don't call unconverted helpers directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-29 01:28:09 +04:00
DEF_HELPER_4(glue(maskmov, SUFFIX), void, env, Reg, Reg, tl)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#endif
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#if SHIFT == 0
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
DEF_HELPER_3(glue(pshufw, SUFFIX), void, Reg, Reg, int)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#else
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
DEF_HELPER_3(glue(pshufd, SUFFIX), void, Reg, Reg, int)
DEF_HELPER_3(glue(pshuflw, SUFFIX), void, Reg, Reg, int)
DEF_HELPER_3(glue(pshufhw, SUFFIX), void, Reg, Reg, int)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#endif
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT >= 1
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
/* FPU ops */
/* XXX: not accurate */
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#define SSE_HELPER_P4(name) \
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(name ## ps, SUFFIX), void, env, Reg, Reg, Reg) \
DEF_HELPER_4(glue(name ## pd, SUFFIX), void, env, Reg, Reg, Reg)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#define SSE_HELPER_P3(name, ...) \
DEF_HELPER_3(glue(name ## ps, SUFFIX), void, env, Reg, Reg) \
DEF_HELPER_3(glue(name ## pd, SUFFIX), void, env, Reg, Reg)
#if SHIFT == 1
#define SSE_HELPER_S4(name) \
SSE_HELPER_P4(name) \
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(name ## ss, void, env, Reg, Reg, Reg) \
DEF_HELPER_4(name ## sd, void, env, Reg, Reg, Reg)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#define SSE_HELPER_S3(name) \
SSE_HELPER_P3(name) \
target/i386: provide 3-operand versions of unary scalar helpers Compared to Paul's implementation, the new decoder will use a different approach to implement AVX's merging of dst with src1 on scalar operations. Adjust the old SSE decoder to be compatible with new-style helpers. The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-09 12:08:18 +03:00
DEF_HELPER_4(name ## ss, void, env, Reg, Reg, Reg) \
DEF_HELPER_4(name ## sd, void, env, Reg, Reg, Reg)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#else
#define SSE_HELPER_S4(name, ...) SSE_HELPER_P4(name)
#define SSE_HELPER_S3(name, ...) SSE_HELPER_P3(name)
#endif
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(shufps, SUFFIX), void, Reg, Reg, Reg, int)
DEF_HELPER_4(glue(shufpd, SUFFIX), void, Reg, Reg, Reg, int)
proper helper definition registering (all targets must do that) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 20:11:04 +04:00
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
SSE_HELPER_S4(add)
SSE_HELPER_S4(sub)
SSE_HELPER_S4(mul)
SSE_HELPER_S4(div)
SSE_HELPER_S4(min)
SSE_HELPER_S4(max)
proper helper definition registering (all targets must do that) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 20:11:04 +04:00
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
SSE_HELPER_S3(sqrt)
proper helper definition registering (all targets must do that) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 20:11:04 +04:00
target/i386: Add size suffix to vector FP helpers For AVX we're going to need both 128 bit (xmm) and 256 bit (ymm) variants of floating point helpers. Add the register type suffix to the existing *PS and *PD helpers (SS and SD variants are only valid on 128 bit vectors) No functional changes. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-15-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:49:31 +03:00
DEF_HELPER_3(glue(cvtps2pd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(cvtpd2ps, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(cvtdq2ps, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(cvtdq2pd, SUFFIX), void, env, Reg, Reg)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
DEF_HELPER_3(glue(cvtps2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(glue(cvtpd2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(glue(cvttps2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(glue(cvttpd2dq, SUFFIX), void, env, ZMMReg, ZMMReg)
#if SHIFT == 1
target/i386: provide 3-operand versions of unary scalar helpers Compared to Paul's implementation, the new decoder will use a different approach to implement AVX's merging of dst with src1 on scalar operations. Adjust the old SSE decoder to be compatible with new-style helpers. The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-09 12:08:18 +03:00
DEF_HELPER_4(cvtss2sd, void, env, Reg, Reg, Reg)
DEF_HELPER_4(cvtsd2ss, void, env, Reg, Reg, Reg)
target-i386: Rename struct XMMReg to ZMMReg The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-19 21:12:40 +03:00
DEF_HELPER_3(cvtpi2ps, void, env, ZMMReg, MMXReg)
DEF_HELPER_3(cvtpi2pd, void, env, ZMMReg, MMXReg)
DEF_HELPER_3(cvtsi2ss, void, env, ZMMReg, i32)
DEF_HELPER_3(cvtsi2sd, void, env, ZMMReg, i32)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#ifdef TARGET_X86_64
target-i386: Rename struct XMMReg to ZMMReg The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-19 21:12:40 +03:00
DEF_HELPER_3(cvtsq2ss, void, env, ZMMReg, i64)
DEF_HELPER_3(cvtsq2sd, void, env, ZMMReg, i64)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#endif
target-i386: Rename struct XMMReg to ZMMReg The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-19 21:12:40 +03:00
DEF_HELPER_3(cvtps2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_3(cvtpd2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_2(cvtss2si, s32, env, ZMMReg)
DEF_HELPER_2(cvtsd2si, s32, env, ZMMReg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#ifdef TARGET_X86_64
target-i386: Rename struct XMMReg to ZMMReg The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-19 21:12:40 +03:00
DEF_HELPER_2(cvtss2sq, s64, env, ZMMReg)
DEF_HELPER_2(cvtsd2sq, s64, env, ZMMReg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#endif
target-i386: Rename struct XMMReg to ZMMReg The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-19 21:12:40 +03:00
DEF_HELPER_3(cvttps2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_3(cvttpd2pi, void, env, MMXReg, ZMMReg)
DEF_HELPER_2(cvttss2si, s32, env, ZMMReg)
DEF_HELPER_2(cvttsd2si, s32, env, ZMMReg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#ifdef TARGET_X86_64
target-i386: Rename struct XMMReg to ZMMReg The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-19 21:12:40 +03:00
DEF_HELPER_2(cvttss2sq, s64, env, ZMMReg)
DEF_HELPER_2(cvttsd2sq, s64, env, ZMMReg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#endif
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#endif
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
target/i386: Add size suffix to vector FP helpers For AVX we're going to need both 128 bit (xmm) and 256 bit (ymm) variants of floating point helpers. Add the register type suffix to the existing *PS and *PD helpers (SS and SD variants are only valid on 128 bit vectors) No functional changes. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-15-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:49:31 +03:00
DEF_HELPER_3(glue(rsqrtps, SUFFIX), void, env, ZMMReg, ZMMReg)
DEF_HELPER_3(glue(rcpps, SUFFIX), void, env, ZMMReg, ZMMReg)
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT == 1
target/i386: provide 3-operand versions of unary scalar helpers Compared to Paul's implementation, the new decoder will use a different approach to implement AVX's merging of dst with src1 on scalar operations. Adjust the old SSE decoder to be compatible with new-style helpers. The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-09 12:08:18 +03:00
DEF_HELPER_4(rsqrtss, void, env, ZMMReg, ZMMReg, ZMMReg)
DEF_HELPER_4(rcpss, void, env, ZMMReg, ZMMReg, ZMMReg)
target-i386: Rename struct XMMReg to ZMMReg The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-19 21:12:40 +03:00
DEF_HELPER_3(extrq_r, void, env, ZMMReg, ZMMReg)
DEF_HELPER_4(extrq_i, void, env, ZMMReg, int, int)
DEF_HELPER_3(insertq_r, void, env, ZMMReg, ZMMReg)
target/i386: fix INSERTQ implementation INSERTQ is defined to not modify any bits in the lower 64 bits of the destination, other than the ones being replaced with bits from the source operand. QEMU instead is using unshifted bits from the source for those bits. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-18 10:52:24 +03:00
DEF_HELPER_5(insertq_i, void, env, ZMMReg, ZMMReg, int, int)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#endif
SSE_HELPER_P4(hadd)
SSE_HELPER_P4(hsub)
SSE_HELPER_P4(addsub)
#define SSE_HELPER_CMP(name, F, C) SSE_HELPER_S4(name)
proper helper definition registering (all targets must do that) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 20:11:04 +04:00
target/i386: reimplement AVX comparison helpers AVX includes an additional set of comparison predicates, some of which our softfloat implementation does not expose as separate functions. Rewrite the helpers in terms of floatN_compare for future extensibility. Signed-off-by: Paul Brook <paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220424220204.2493824-24-paul@nowt.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-26 00:58:15 +03:00
SSE_HELPER_CMP(cmpeq, FPU_CMPQ, FPU_EQ)
SSE_HELPER_CMP(cmplt, FPU_CMPS, FPU_LT)
SSE_HELPER_CMP(cmple, FPU_CMPS, FPU_LE)
SSE_HELPER_CMP(cmpunord, FPU_CMPQ, FPU_UNORD)
SSE_HELPER_CMP(cmpneq, FPU_CMPQ, !FPU_EQ)
SSE_HELPER_CMP(cmpnlt, FPU_CMPS, !FPU_LT)
SSE_HELPER_CMP(cmpnle, FPU_CMPS, !FPU_LE)
SSE_HELPER_CMP(cmpord, FPU_CMPQ, !FPU_UNORD)
proper helper definition registering (all targets must do that) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 20:11:04 +04:00
target/i386: implement additional AVX comparison operators The new implementation of SSE will cover AVX from the get go, so include the 24 extra comparison operators that are only available with the VEX prefix. Based on a patch by Paul Brook <paul@nowt.org>. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-26 00:54:58 +03:00
SSE_HELPER_CMP(cmpequ, FPU_CMPQ, FPU_EQU)
SSE_HELPER_CMP(cmpnge, FPU_CMPS, !FPU_GE)
SSE_HELPER_CMP(cmpngt, FPU_CMPS, !FPU_GT)
SSE_HELPER_CMP(cmpfalse, FPU_CMPQ, FPU_FALSE)
SSE_HELPER_CMP(cmpnequ, FPU_CMPQ, !FPU_EQU)
SSE_HELPER_CMP(cmpge, FPU_CMPS, FPU_GE)
SSE_HELPER_CMP(cmpgt, FPU_CMPS, FPU_GT)
SSE_HELPER_CMP(cmptrue, FPU_CMPQ, !FPU_FALSE)
SSE_HELPER_CMP(cmpeqs, FPU_CMPS, FPU_EQ)
SSE_HELPER_CMP(cmpltq, FPU_CMPQ, FPU_LT)
SSE_HELPER_CMP(cmpleq, FPU_CMPQ, FPU_LE)
SSE_HELPER_CMP(cmpunords, FPU_CMPS, FPU_UNORD)
SSE_HELPER_CMP(cmpneqq, FPU_CMPS, !FPU_EQ)
SSE_HELPER_CMP(cmpnltq, FPU_CMPQ, !FPU_LT)
SSE_HELPER_CMP(cmpnleq, FPU_CMPQ, !FPU_LE)
SSE_HELPER_CMP(cmpords, FPU_CMPS, !FPU_UNORD)
SSE_HELPER_CMP(cmpequs, FPU_CMPS, FPU_EQU)
SSE_HELPER_CMP(cmpngeq, FPU_CMPQ, !FPU_GE)
SSE_HELPER_CMP(cmpngtq, FPU_CMPQ, !FPU_GT)
SSE_HELPER_CMP(cmpfalses, FPU_CMPS, FPU_FALSE)
SSE_HELPER_CMP(cmpnequs, FPU_CMPS, !FPU_EQU)
SSE_HELPER_CMP(cmpgeq, FPU_CMPQ, FPU_GE)
SSE_HELPER_CMP(cmpgtq, FPU_CMPQ, FPU_GT)
SSE_HELPER_CMP(cmptrues, FPU_CMPS, !FPU_FALSE)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT == 1
x86: avoid AREG0 for FPU helpers Make FPU helpers take a parameter for CPUState instead of relying on global env. Introduce temporary wrappers for FPU load and store ops. Remove wrappers for non-AREG0 code. Don't call unconverted helpers directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-29 01:28:09 +04:00
DEF_HELPER_3(ucomiss, void, env, Reg, Reg)
DEF_HELPER_3(comiss, void, env, Reg, Reg)
DEF_HELPER_3(ucomisd, void, env, Reg, Reg)
DEF_HELPER_3(comisd, void, env, Reg, Reg)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#endif
target/i386: Add size suffix to vector FP helpers For AVX we're going to need both 128 bit (xmm) and 256 bit (ymm) variants of floating point helpers. Add the register type suffix to the existing *PS and *PD helpers (SS and SD variants are only valid on 128 bit vectors) No functional changes. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-15-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:49:31 +03:00
DEF_HELPER_2(glue(movmskps, SUFFIX), i32, env, Reg)
DEF_HELPER_2(glue(movmskpd, SUFFIX), i32, env, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#endif
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(packsswb, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(packuswb, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(packssdw, SUFFIX), void, env, Reg, Reg, Reg)
#define UNPCK_OP(name, base) \
DEF_HELPER_4(glue(punpck ## name ## bw, SUFFIX), void, env, Reg, Reg, Reg) \
DEF_HELPER_4(glue(punpck ## name ## wd, SUFFIX), void, env, Reg, Reg, Reg) \
DEF_HELPER_4(glue(punpck ## name ## dq, SUFFIX), void, env, Reg, Reg, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
proper helper definition registering (all targets must do that) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22 20:11:04 +04:00
UNPCK_OP(l, 0)
UNPCK_OP(h, 1)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT >= 1
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(punpcklqdq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(punpckhqdq, SUFFIX), void, env, Reg, Reg, Reg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#endif
/* 3DNow! float ops */
#if SHIFT == 0
x86: avoid AREG0 for FPU helpers Make FPU helpers take a parameter for CPUState instead of relying on global env. Introduce temporary wrappers for FPU load and store ops. Remove wrappers for non-AREG0 code. Don't call unconverted helpers directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-29 01:28:09 +04:00
DEF_HELPER_3(pi2fd, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pi2fw, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pf2id, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pf2iw, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfacc, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfadd, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfcmpeq, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfcmpge, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfcmpgt, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfmax, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfmin, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfmul, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfnacc, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfpnacc, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfrcp, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfrsqrt, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfsub, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pfsubr, void, env, MMXReg, MMXReg)
DEF_HELPER_3(pswapd, void, env, MMXReg, MMXReg)
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#endif
Implement x86 SSSE3 instructions. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5315 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-25 22:01:46 +04:00
/* SSSE3 op helpers */
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(phaddw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(phaddd, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(phaddsw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(phsubw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(phsubd, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(phsubsw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(pmaddubsw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(pmulhrsw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(pshufb, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psignb, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psignw, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(psignd, SUFFIX), void, env, Reg, Reg, Reg)
target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes Three-byte opcodes from the 0F3Ah area all have an immediate byte which is usually unsigned. Clarify in the helper code that it is unsigned; the new decoder treats immediates as signed by default, and seeing an intN_t in the prototype might give the wrong impression that one can use decode->immediate directly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-20 18:48:14 +03:00
DEF_HELPER_5(glue(palignr, SUFFIX), void, env, Reg, Reg, Reg, i32)
Implement x86 SSSE3 instructions. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5315 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-25 22:01:46 +04:00
Implement SSE4.1, SSE4.2 (x86). This adds support for CPUID_EXT_SSE41, CPUID_EXT_SSE42, CPUID_EXT_POPCNT extensions. Most instructions haven't been tested yet. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5411 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-04 07:27:44 +04:00
/* SSE4.1 op helpers */
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT >= 1
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_5(glue(pblendvb, SUFFIX), void, env, Reg, Reg, Reg, Reg)
DEF_HELPER_5(glue(blendvps, SUFFIX), void, env, Reg, Reg, Reg, Reg)
DEF_HELPER_5(glue(blendvpd, SUFFIX), void, env, Reg, Reg, Reg, Reg)
x86: avoid AREG0 for FPU helpers Make FPU helpers take a parameter for CPUState instead of relying on global env. Introduce temporary wrappers for FPU load and store ops. Remove wrappers for non-AREG0 code. Don't call unconverted helpers directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-29 01:28:09 +04:00
DEF_HELPER_3(glue(ptest, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovsxbw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovsxbd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovsxbq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovsxwd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovsxwq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovsxdq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxbw, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxbd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxbq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxwd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxwq, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovzxdq, SUFFIX), void, env, Reg, Reg)
target/i386: reimplement 0x0f 0x10-0x17, add AVX These are mostly moves, and yet are a total pain. The main issue is that: 1) some instructions are selected by mod==11 (register operand) vs. mod=00/01/10 (memory operand) 2) stores to memory are two-operand operations, while the 3-register and load-from-memory versions operate on the entire contents of the destination; this makes it easier to separate the gen_* function for the store case 3) it's inefficient to load into xmm_T0 only to move the value out again, so the gen_* function for the load case is separated too The manual also has various mistakes in the operands here, for example the store case of MOVHPS operates on a 128-bit source (albeit discarding the bottom 64 bits) and therefore should be Mq,Vdq rather than Mq,Vq. Likewise for the destination and source of MOVHLPS. VUNPCK?PS and VUNPCK?PD are the same as VUNPCK?DQ and VUNPCK?QDQ, but encoded as prefixes rather than separate operands. The helpers can be reused however. For MOVSLDUP, MOVSHDUP and MOVDDUP I chose to reimplement them as helpers. I named the helper for MOVDDUP "movdldup" in preparation for possible future introduction of MOVDHDUP and to clarify the similarity with MOVSLDUP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-18 00:22:36 +03:00
DEF_HELPER_3(glue(pmovsldup, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovshdup, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(pmovdldup, SUFFIX), void, env, Reg, Reg)
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(pmuldq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(packusdw, SUFFIX), void, env, Reg, Reg, Reg)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT == 1
x86: avoid AREG0 for FPU helpers Make FPU helpers take a parameter for CPUState instead of relying on global env. Introduce temporary wrappers for FPU load and store ops. Remove wrappers for non-AREG0 code. Don't call unconverted helpers directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-29 01:28:09 +04:00
DEF_HELPER_3(glue(phminposuw, SUFFIX), void, env, Reg, Reg)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#endif
x86: avoid AREG0 for FPU helpers Make FPU helpers take a parameter for CPUState instead of relying on global env. Introduce temporary wrappers for FPU load and store ops. Remove wrappers for non-AREG0 code. Don't call unconverted helpers directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-29 01:28:09 +04:00
DEF_HELPER_4(glue(roundps, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(roundpd, SUFFIX), void, env, Reg, Reg, i32)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT == 1
target/i386: provide 3-operand versions of unary scalar helpers Compared to Paul's implementation, the new decoder will use a different approach to implement AVX's merging of dst with src1 on scalar operations. Adjust the old SSE decoder to be compatible with new-style helpers. The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-09 12:08:18 +03:00
DEF_HELPER_5(roundss_xmm, void, env, Reg, Reg, Reg, i32)
DEF_HELPER_5(roundsd_xmm, void, env, Reg, Reg, Reg, i32)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#endif
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_5(glue(blendps, SUFFIX), void, env, Reg, Reg, Reg, i32)
DEF_HELPER_5(glue(blendpd, SUFFIX), void, env, Reg, Reg, Reg, i32)
DEF_HELPER_5(glue(pblendw, SUFFIX), void, env, Reg, Reg, Reg, i32)
DEF_HELPER_5(glue(dpps, SUFFIX), void, env, Reg, Reg, Reg, i32)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT == 1
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_5(glue(dppd, SUFFIX), void, env, Reg, Reg, Reg, i32)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#endif
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_5(glue(mpsadbw, SUFFIX), void, env, Reg, Reg, Reg, i32)
Implement SSE4.1, SSE4.2 (x86). This adds support for CPUID_EXT_SSE41, CPUID_EXT_SSE42, CPUID_EXT_POPCNT extensions. Most instructions haven't been tested yet. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5411 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-04 07:27:44 +04:00
#endif
/* SSE4.2 op helpers */
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT == 1
x86: avoid AREG0 for FPU helpers Make FPU helpers take a parameter for CPUState instead of relying on global env. Introduce temporary wrappers for FPU load and store ops. Remove wrappers for non-AREG0 code. Don't call unconverted helpers directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-29 01:28:09 +04:00
DEF_HELPER_4(glue(pcmpestri, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(pcmpestrm, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(pcmpistri, SUFFIX), void, env, Reg, Reg, i32)
DEF_HELPER_4(glue(pcmpistrm, SUFFIX), void, env, Reg, Reg, i32)
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
DEF_HELPER_3(crc32, tl, i32, tl, i32)
Implement SSE4.1, SSE4.2 (x86). This adds support for CPUID_EXT_SSE41, CPUID_EXT_SSE42, CPUID_EXT_POPCNT extensions. Most instructions haven't been tested yet. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5411 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-04 07:27:44 +04:00
#endif
target-i386: add pclmulqdq instruction Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-31 14:58:30 +04:00
/* AES-NI op helpers */
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT >= 1
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_4(glue(aesdec, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(aesdeclast, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(aesenc, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(aesenclast, SUFFIX), void, env, Reg, Reg, Reg)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#if SHIFT == 1
target-i386: add AES-NI instructions Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-31 14:58:31 +04:00
DEF_HELPER_3(glue(aesimc, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_4(glue(aeskeygenassist, SUFFIX), void, env, Reg, Reg, i32)
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#endif
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Add to the helpers all the operands that are needed to implement AVX. Extracted from a patch by Paul Brook <paul@nowt.org>. Message-Id: <20220424220204.2493824-26-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-08-27 01:00:50 +03:00
DEF_HELPER_5(glue(pclmulqdq, SUFFIX), void, env, Reg, Reg, Reg, i32)
target-i386: add pclmulqdq instruction Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-31 14:58:30 +04:00
#endif
target/i386: implement F16C instructions F16C only consists of two instructions, which are a bit peculiar nevertheless. First, they access only the low half of an YMM or XMM register for the packed-half operand; the exact size still depends on the VEX.L flag. This is similar to the existing avx_movx flag, but not exactly because avx_movx is hardcoded to affect operand 2. To this end I added a "ph" format name; it's possible to reuse this approach for the VPMOVSX and VPMOVZX instructions, though that would also require adding two more formats for the low-quarter and low-eighth of an operand. Second, VCVTPS2PH is somewhat weird because it *stores* the result of the instruction into memory rather than loading it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-10-19 14:22:06 +03:00
/* F16C helpers */
#if SHIFT >= 1
DEF_HELPER_3(glue(cvtph2ps, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_4(glue(cvtps2ph, SUFFIX), void, env, Reg, Reg, int)
#endif
target/i386: implement FMA instructions The only issue with FMA instructions is that there are _a lot_ of them (30 opcodes, each of which comes in up to 4 versions depending on VEX.W and VEX.L; a total of 96 possibilities). However, they can be implement with only 6 helpers, two for scalar operations and four for packed operations. (Scalar versions do not do any merging; they only affect the bottom 32 or 64 bits of the output operand. Therefore, there is no separate XMM and YMM of the scalar helpers). First, we can reduce the number of helpers to one third by passing four operands (one output and three inputs); the reordering of which operands go to the multiply and which go to the add is done in emit.c. Second, the different instructions also dispatch to the same softfloat function, so the flags for float32_muladd and float64_muladd are passed in the helper as int arguments, with a little extra complication to handle FMADDSUB and FMSUBADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-10-19 14:22:06 +03:00
/* FMA3 helpers */
#if SHIFT == 1
DEF_HELPER_6(fma4ss, void, env, Reg, Reg, Reg, Reg, int)
DEF_HELPER_6(fma4sd, void, env, Reg, Reg, Reg, Reg, int)
#endif
#if SHIFT >= 1
DEF_HELPER_7(glue(fma4ps, SUFFIX), void, env, Reg, Reg, Reg, Reg, int, int)
DEF_HELPER_7(glue(fma4pd, SUFFIX), void, env, Reg, Reg, Reg, Reg, int, int)
#endif
target/i386: reimplement 0x0f 0x3a, add AVX The more complicated operations here are insertions and extractions. Otherwise, there are just more entries than usual because the PS/PD/SS/SD variations are encoded in the opcode rater than in the prefixes. These three-byte opcodes also include AVX new instructions, whose implementation in the helpers was originally done by Paul Brook <paul@nowt.org>. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-06 11:34:11 +03:00
/* AVX helpers */
#if SHIFT >= 1
target/i386: reimplement 0x0f 0x38, add AVX There are several special cases here: 1) extending moves have different widths for the helpers vs. for the memory loads, and the width for memory loads depends on VEX.L too. This is represented by X86_SPECIAL_AVXExtMov. 2) some instructions, such as variable-width shifts, select the vector element size via REX.W. 3) VSIB instructions (VGATHERxPy, VPGATHERxy) are also part of this group, and they have (among other things) two output operands. 3) the macros for 4-operand blends (which are under 0x0f 0x3a) have to be extended to support 2-operand blends. The 2-operand variant actually came a few years earlier, but it is clearer to implement them in the opposite order. X86_TYPE_WM, introduced earlier for unaligned loads, is reused for helpers that accept a Reg* but have a M argument. These three-byte opcodes also include AVX new instructions, for which the helpers were originally implemented by Paul Brook <paul@nowt.org>. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-14 19:52:44 +03:00
DEF_HELPER_4(glue(vpermilpd, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(vpermilps, SUFFIX), void, env, Reg, Reg, Reg)
target/i386: reimplement 0x0f 0x3a, add AVX The more complicated operations here are insertions and extractions. Otherwise, there are just more entries than usual because the PS/PD/SS/SD variations are encoded in the opcode rater than in the prefixes. These three-byte opcodes also include AVX new instructions, whose implementation in the helpers was originally done by Paul Brook <paul@nowt.org>. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-06 11:34:11 +03:00
DEF_HELPER_3(glue(vpermilpd_imm, SUFFIX), void, Reg, Reg, i32)
DEF_HELPER_3(glue(vpermilps_imm, SUFFIX), void, Reg, Reg, i32)
target/i386: reimplement 0x0f 0x38, add AVX There are several special cases here: 1) extending moves have different widths for the helpers vs. for the memory loads, and the width for memory loads depends on VEX.L too. This is represented by X86_SPECIAL_AVXExtMov. 2) some instructions, such as variable-width shifts, select the vector element size via REX.W. 3) VSIB instructions (VGATHERxPy, VPGATHERxy) are also part of this group, and they have (among other things) two output operands. 3) the macros for 4-operand blends (which are under 0x0f 0x3a) have to be extended to support 2-operand blends. The 2-operand variant actually came a few years earlier, but it is clearer to implement them in the opposite order. X86_TYPE_WM, introduced earlier for unaligned loads, is reused for helpers that accept a Reg* but have a M argument. These three-byte opcodes also include AVX new instructions, for which the helpers were originally implemented by Paul Brook <paul@nowt.org>. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-14 19:52:44 +03:00
DEF_HELPER_4(glue(vpsrlvd, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(vpsravd, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(vpsllvd, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(vpsrlvq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(vpsravq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(vpsllvq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_3(glue(vtestps, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_3(glue(vtestpd, SUFFIX), void, env, Reg, Reg)
DEF_HELPER_4(glue(vpmaskmovd_st, SUFFIX), void, env, Reg, Reg, tl)
DEF_HELPER_4(glue(vpmaskmovq_st, SUFFIX), void, env, Reg, Reg, tl)
DEF_HELPER_4(glue(vpmaskmovd, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_4(glue(vpmaskmovq, SUFFIX), void, env, Reg, Reg, Reg)
DEF_HELPER_6(glue(vpgatherdd, SUFFIX), void, env, Reg, Reg, Reg, tl, i32)
DEF_HELPER_6(glue(vpgatherdq, SUFFIX), void, env, Reg, Reg, Reg, tl, i32)
DEF_HELPER_6(glue(vpgatherqd, SUFFIX), void, env, Reg, Reg, Reg, tl, i32)
DEF_HELPER_6(glue(vpgatherqq, SUFFIX), void, env, Reg, Reg, Reg, tl, i32)
target/i386: reimplement 0x0f 0x3a, add AVX The more complicated operations here are insertions and extractions. Otherwise, there are just more entries than usual because the PS/PD/SS/SD variations are encoded in the opcode rater than in the prefixes. These three-byte opcodes also include AVX new instructions, whose implementation in the helpers was originally done by Paul Brook <paul@nowt.org>. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-06 11:34:11 +03:00
#if SHIFT == 2
target/i386: reimplement 0x0f 0x38, add AVX There are several special cases here: 1) extending moves have different widths for the helpers vs. for the memory loads, and the width for memory loads depends on VEX.L too. This is represented by X86_SPECIAL_AVXExtMov. 2) some instructions, such as variable-width shifts, select the vector element size via REX.W. 3) VSIB instructions (VGATHERxPy, VPGATHERxy) are also part of this group, and they have (among other things) two output operands. 3) the macros for 4-operand blends (which are under 0x0f 0x3a) have to be extended to support 2-operand blends. The 2-operand variant actually came a few years earlier, but it is clearer to implement them in the opposite order. X86_TYPE_WM, introduced earlier for unaligned loads, is reused for helpers that accept a Reg* but have a M argument. These three-byte opcodes also include AVX new instructions, for which the helpers were originally implemented by Paul Brook <paul@nowt.org>. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-14 19:52:44 +03:00
DEF_HELPER_3(vpermd_ymm, void, Reg, Reg, Reg)
target/i386: reimplement 0x0f 0x3a, add AVX The more complicated operations here are insertions and extractions. Otherwise, there are just more entries than usual because the PS/PD/SS/SD variations are encoded in the opcode rater than in the prefixes. These three-byte opcodes also include AVX new instructions, whose implementation in the helpers was originally done by Paul Brook <paul@nowt.org>. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-06 11:34:11 +03:00
DEF_HELPER_4(vpermdq_ymm, void, Reg, Reg, Reg, i32)
DEF_HELPER_3(vpermq_ymm, void, Reg, Reg, i32)
#endif
#endif
target/i386: implement SHA instructions The implementation was validated with OpenSSL and with the test vectors in https://github.com/rust-lang/stdarch/blob/master/crates/core_arch/src/x86/sha.rs. The instructions provide a ~25% improvement on hashing a 64 MiB file: runtime goes down from 1.8 seconds to 1.4 seconds; instruction count on the host goes down from 5.8 billion to 4.8 billion with slightly better IPC too. Good job Intel. ;) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-10 11:31:17 +03:00
/* SHA helpers */
#if SHIFT == 1
DEF_HELPER_3(sha1rnds4_f0, void, Reg, Reg, Reg)
DEF_HELPER_3(sha1rnds4_f1, void, Reg, Reg, Reg)
DEF_HELPER_3(sha1rnds4_f2, void, Reg, Reg, Reg)
DEF_HELPER_3(sha1rnds4_f3, void, Reg, Reg, Reg)
DEF_HELPER_3(sha1nexte, void, Reg, Reg, Reg)
DEF_HELPER_3(sha1msg1, void, Reg, Reg, Reg)
DEF_HELPER_3(sha1msg2, void, Reg, Reg, Reg)
DEF_HELPER_5(sha256rnds2, void, Reg, Reg, Reg, i32, i32)
DEF_HELPER_3(sha256msg1, void, Reg, Reg, Reg)
DEF_HELPER_3(sha256msg2, void, Reg, Reg, Reg)
#endif
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#undef SHIFT
#undef Reg
#undef SUFFIX
#undef SSE_HELPER_B
#undef SSE_HELPER_W
#undef SSE_HELPER_L
#undef SSE_HELPER_Q
target/i386: Prepare ops_sse_header.h for 256 bit AVX Adjust all #ifdefs to match the ones in ops_sse.h. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-23-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-25 01:01:44 +03:00
#undef SSE_HELPER_S3
#undef SSE_HELPER_S4
#undef SSE_HELPER_P3
#undef SSE_HELPER_P4
converted SSE/MMX ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 20:47:36 +04:00
#undef SSE_HELPER_CMP
#undef UNPCK_OP
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